JP2005243840A - Charge coupled device, solid-state image pickup device, and their driving methods - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a storing phase and a barrier phase are formed by the concentration difference of an impurity at the time of inverting the surface of a substrate for reducing a dark current in a CCD, a driving circuit becomes complicated. <P>SOLUTION: Gate electrodes 44 which are clock-driven at a transferring time are provided on the surface side of a semiconductor substrate 30. On the other hand, electrode areas 36 and 38 arranged along the charge transferring direction are alternately formed in a P-sub 32. At the time of stopping a charge packet in a channel, the surface of an n-well 40 is inverted by impressing voltages upon the gate electrodes 44 and, on the other hand, different voltages are impressed upon the electrode areas 36 and 38. When a voltage higher than that impressed upon the electrode areas 38 is impressed upon the electrode areas 36, channel potentials on the electrode areas 36 are formed deeply and channel potentials on the electrode areas 38 are formed relatively shallowly. As a result, the storing phase and the barrier phase are formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a charge coupled device used for transferring signal charges and the like and a solid-state imaging device using the same, and more particularly to reduction of dark current.

  A charge coupled device (CCD) controls the internal potential of a semiconductor substrate having an oxide film formed on the surface in accordance with a voltage applied to a gate electrode disposed on the oxide film. As a result, a potential well and a potential barrier separating the potential wells can be formed in the vicinity of the semiconductor substrate surface, and signal charges can be accumulated in the potential well as charge packets. Further, by arranging a plurality of gate electrodes in a certain direction and sequentially changing the voltage applied to them, the charge packets can be transferred along with the potential well along the arrangement direction of the gate electrodes.

  This CCD is used as a means for reading out signal charges generated in light receiving pixels arranged in a matrix to an output unit in a CCD image sensor which is a solid-state imaging device. In the CCD image sensor, the CCD horizontally transfers a plurality of vertical shift registers that transfer the signal charges of each column in the vertical direction (direction along the columns), and the signal charges that are output row by row from the plurality of vertical shift registers. A horizontal shift register for transferring in the direction (direction along the row) is configured. In the frame transfer type CCD image sensor, the CCD itself provided for each column of the imaging unit constitutes a light receiving pixel of each column, and generates a signal charge corresponding to the amount of received light.

  Now, in the CCD, there are problems in that many interface states are formed at the boundary between the semiconductor substrate surface and the oxide film, and the charges generated thereby are mixed into the signal charge accumulated in the potential well as dark current noise. Become. In order to cope with this, at present, the CCD is generally configured as a buried channel type in which an n-type semiconductor layer is formed on the surface of a p-type semiconductor substrate, for example. In this configuration, the potential well position in the substrate vertical direction (substrate thickness direction) can be shifted into the semiconductor substrate, avoiding the semiconductor substrate surface where the interface states exist, thereby reducing dark current noise. can do.

  However, the depletion layer forming the potential well extends to the interface, and charges generated at the interface state due to depletion of the interface flow into the potential well. Therefore, if the time accumulated in the potential well is long, degradation of the signal-to-noise ratio (signal-to-noise ratio) due to dark current is also a problem.

Similarly, the interface state also becomes a problem in the photodiode that constitutes the light receiving pixel of the solid-state imaging device. In the photodiode, in order to solve this problem, for example, in a photodiode configured by forming an n-type impurity region on the surface of a p-type substrate, a semiconductor in which an interface state exists by forming a p ⁺ layer on the surface. A buried photodiode structure is employed in which the vicinity of the substrate surface is not depleted.

Similar to this buried photodiode, the dark current can be further reduced by not depleting the surface of the buried channel CCD. Specifically, an inversion layer is formed on the surface of the semiconductor substrate by controlling the voltage of the gate electrode of the CCD. For example, in a buried channel CCD in which an n-type layer is formed on the surface of the p-type layer described above, when the gate voltage is a predetermined negative voltage, the substrate surface is inverted by holes supplied from the p ⁺ layer in the element isolation region. It becomes.

  Incidentally, in the inversion state, the surface potential remains fixed (pinning state) even if the absolute value of the voltage is further increased. That is, in the inverted state, the channel potential cannot be controlled by the gate voltage. Therefore, by providing a difference in impurity profile in advance between the portion serving as a potential well (accumulation phase) and the portion serving as a potential barrier (barrier phase) along the CCD transfer direction, the accumulation phase and the barrier phase are provided. Cause a potential difference. As a result, the potential of the barrier phase is shallower than that of the accumulation phase, and charge packets can be separated by this barrier phase.

  With this structure, charge packets can be held in the channel even when the CCD is inverted. On the other hand, in order to transfer the held charge packet along the channel, the inversion state is released. Then, by controlling the gate voltage, the state of the channel under each gate electrode is changed in a predetermined order and cycle, and the charge packet can be transferred in a predetermined direction by alternately setting the storage phase and the barrier phase.

  FIG. 8 is a schematic cross-sectional view along the transfer direction of a CCD according to the prior art. In this CCD, a p-type semiconductor layer (P-well 4) and an n-type semiconductor layer (N-well 6) constituting a charge transfer region are respectively formed on the surface of an n-type silicon substrate (N-sub 2) by an ion implantation process and a heat. It is a buried channel structure formed sequentially by a diffusion process. That is, the potential of the depletion layer formed in the P-well 4 and the N-well 6 has an extreme value at a position away from the substrate surface, and the vicinity of the position becomes a channel for accumulating and transferring signal charges. An oxide film 8 is formed on the substrate surface, and a plurality of gate electrodes 10 are arranged on the N-well 6 with the oxide film 8 interposed therebetween as an insulating film. By applying a clock (in this example, three-phase clocks φ1 to φ3) to the gate electrode group and controlling the channel potential, a charge packet is transferred in the channel along the arrangement direction of the gate electrodes 10. On the other hand, when the transfer is stopped and the charge packet consisting of signal charges is stopped and held in the channel, the generation of dark current at the interface between the substrate (N-well 6) and the oxide film 8 during the stop period is suppressed. For this purpose, a negative voltage is applied to each gate electrode 10 to collect holes on the surface of the N-well 6 to induce an inversion layer. In order to provide a channel potential difference between the accumulation phase and the barrier phase in the inverted state, an additional n-type impurity is diffused under the gate electrodes 10-2 and 10-3, and a high concentration n-type is formed in the N-well 6. A semiconductor region 12 is formed. As a result, in a state where the surface is pinned, the channel potential under the gate electrodes 10-2 and 10-3 becomes deeper than under the gate electrode 10-1, which retains the charge packet as an accumulation phase, while the gate electrode A portion having a shallow channel potential below 10-1 constitutes a barrier phase that separates adjacent charge packets.

In Patent Document 1 below, the potential profile of the charge well becomes a flat band at the interface by adjusting the impurity profile of the channel region formed by each of the n-type and p-type semiconductor layers and the voltage applied to the gate electrode. Thus, the structure which prevents the depletion in an interface is proposed.
Japanese Patent No. 2604250

  As described above, in order to hold the charge packets in the channel in the inverted state, if the portions having different impurity profiles are provided corresponding to the accumulation phase and the barrier phase, the portions having different impurity profiles are changed during the charge packet transfer operation. It will be necessary to drive with different gate voltages. Therefore, there is a problem that the drive circuit becomes complicated. For example, in the example shown in FIG. 8, when the amplitudes of the clocks φ2 and φ3 applied to the gate electrodes 10-2 and 10-3 are 0 to −8V, the clock φ1 applied to the gate electrode 10-1 is φ2 and φ3. It is necessary to set the amplitude shifted in the positive voltage direction, for example, +3 to -5V.

  Further, in order to increase the amount of charge handled by the CCD, it is required to enlarge the portion corresponding to the storage phase, and accordingly, the length in the channel direction of the portion corresponding to the barrier phase is shortened. Here, the channel lengths of the pair of accumulation phases and barrier phases are in accordance with the pixel size in the CCD image sensor. Therefore, along with the increase in the number of pixels of the CCD image sensor, the channel lengths of the pair of accumulation phases and barrier phases of the CCD used therefor are reduced. As a result, there has been a problem that it is difficult to form each barrier phase accurately with no variation, particularly due to impurity diffusion. Further, for example, if each impurity region constituting the accumulation phase or the barrier phase extends under the adjacent gate electrode, a potential dip or the like may occur in the channel direction during the transfer operation, and transfer efficiency may be deteriorated.

  The present invention has been made to solve the above-described problems, and a charge coupled device capable of holding a charge packet in a channel in an inversion state while having a simple driving circuit and realizing good charge transfer. An object of the present invention is to provide a solid-state imaging device using the same.

  (1) A charge-coupled device according to the present invention includes a first conductivity type upper semiconductor layer formed on a surface of a semiconductor substrate and a second conductivity type lower semiconductor layer located under the upper semiconductor layer. A charge transfer region that forms a channel; and a plurality of transfer electrodes arranged along the charge transfer direction on the charge transfer region, and the charge packets are controlled by controlling the potential of the channel by the transfer electrode. A plurality of lower electrodes arranged along the charge transfer direction under the channel and changing the potential of the channel via the lower semiconductor layer according to a voltage applied from the outside. Have.

  According to the present invention, the potential of the lower semiconductor layer is changed according to the voltage applied to the lower electrode, and the depth of the channel potential is changed by the influence of the potential change of the lower semiconductor layer. Thereby, the depth of the potential of the channel is spatially modulated in the charge transfer direction, and a deep portion and a shallow portion can be formed in the potential well in the buried channel in the substrate depth direction. The deep portion forms an accumulation phase that accumulates charge packets, and the shallow portion forms a barrier phase that separates adjacent charge packets. The lower electrode can be disposed, for example, embedded in the lower semiconductor layer. On the other hand, the lower electrode may be disposed in contact with the lower semiconductor layer. In particular, when the lower semiconductor layer continues to the back surface of the semiconductor substrate, the lower electrode can be disposed on the back surface of the semiconductor substrate. .

  (2) In another charge-coupled device according to the present invention, the lower electrode includes a first lower electrode and a second lower electrode whose potentials are separately controlled from the outside, and the first lower electrode and the first lower electrode Two lower electrodes are mixed and arranged in the charge transfer direction in a predetermined arrangement order. According to the present invention, by controlling the first lower electrode and the second lower electrode to different potentials, the depth of the channel potential is spatially modulated in the charge transfer direction, and the accumulation phase and the barrier phase are It is formed.

  In still another charge coupled device according to the present invention, the first lower electrode and the second lower electrode are alternately arranged by a predetermined number, each having an arrangement period of the charge packet sequence in the channel as a repetition period. The According to the present invention, α first lower electrodes A and β second lower electrodes B are alternately arranged. α and β are natural numbers and include one. For example, when α is 2 and β is 1, the first lower electrode and the second lower electrode are arranged in a pattern of A, A, B, A, A, B,. In the channel region, an accumulation phase is formed corresponding to the position on one of A and B, and a barrier phase is formed corresponding to the position on the other. Therefore, in the present invention, (α + β) lower electrodes are arranged for each channel length corresponding to the arrangement period of the charge packet sequence. For example, when the charge coupled device is three-phase driven, a channel length corresponding to three transfer electrodes is an arrangement period of charge packets, and within each period α first lower electrodes and β pieces A second lower electrode is disposed.

  A method of driving these charge-coupled devices, wherein the driving method according to the present invention is configured to stop a clock applied to the transfer electrode and to stop a plurality of the charge packets in the channel. The potential applied to control the voltage applied to the lower electrode to form a potential well at the stop position of each charge packet and the voltage applied to the second lower electrode to separate adjacent potential wells. A potential well array forming step for forming a barrier; and an inversion layer forming step for inducing an inversion layer on the surface of the upper semiconductor layer by applying a predetermined inversion voltage to the transfer electrode. When the inversion layer is formed on the surface of the upper semiconductor layer by controlling the potential of the transfer electrode in order to suppress the dark current when the charge packet is retained in the channel, the transfer electrode cannot control the channel potential. According to the invention, the channel potential is controlled by the first lower electrode and the second lower electrode, the potential well and the potential barrier are formed along the charge transfer direction, and the charge packet is held in the potential well. Can do.

  Furthermore, in the driving method according to the present invention, when the charge packet is transferred by applying the clock to the transfer electrode, the first lower electrode and the second lower electrode have the same potential. According to the present invention, when the charge packet is transferred, the first lower electrode and the second lower electrode are set to the same potential, thereby suppressing the fluctuation of the channel potential in the charge transfer direction by the lower electrode. Therefore, each transfer electrode can be driven with a clock having the same amplitude.

  (3) Another charge coupled device according to the present invention is arranged along the charge transfer region below the lower electrode, and the lower semiconductor according to a voltage applied from the outside independently of the lower electrode A back electrode layer for changing the potential of the channel through the layer is provided, and a predetermined number of the lower electrodes are arranged at respective electrode formation positions provided at predetermined intervals in the charge transfer direction.

  In another charge-coupled device according to the present invention, the electrode formation position is below either a stopping position for stopping the charge packets in the channel or a separation position for separating the stopped charge packets. Is provided. According to the present invention, the region where the lower electrode and the back electrode layer are disposed under the channel and the region where only the back electrode layer is disposed without the lower electrode are alternately provided along the charge transfer direction. By these two different types of regions, the same effects as those of the first lower electrode and the second lower electrode described above can be obtained.

  A preferred aspect of the present invention is a charge coupled device in which the back electrode layer is formed of a semiconductor region of a first conductivity type.

  A method of driving these charge coupled devices, wherein the driving method according to the present invention is configured to stop the clock applied to the transfer electrode and to stop the plurality of charge packets in the channel. And the voltage applied to each of the back electrode layers to control either one of the potential well serving as a retention position of each charge packet and the potential barrier separating the potential wells from each other in the channel. A potential well array forming step in which the other is formed at a position corresponding to the gap between the electrode forming positions, and a predetermined inversion voltage is applied to the transfer electrode, so that the upper semiconductor layer An inversion layer forming step for inducing an inversion layer on the surface.

  (4) In another preferred aspect of the charge coupled device according to the present invention, the lower electrode is a first conductivity type semiconductor region formed inside the lower semiconductor layer.

  In the driving method of the charge coupled device according to the present invention, the voltage applied to the lower electrode is controlled in the operation of stopping the clock applied to the transfer electrode and retaining the charge packet in the channel, A potential well forming step of forming a potential well serving as a charge packet stop position; and an inversion layer forming step of inducing an inversion layer on the surface of the upper semiconductor layer by applying a predetermined inversion voltage to the transfer electrode. Including.

  (5) A solid-state imaging device according to the present invention includes a shift register including the charge-coupled device according to the present invention, and a plurality of light receiving pixels that are formed on the semiconductor substrate and generate a signal charge according to the amount of received light. The signal charge is transferred by the shift register.

  (6) Another solid-state imaging device according to the present invention generates a plurality of vertical shift registers configured by the charge coupled device according to the present invention and a signal charge formed on the semiconductor substrate in accordance with the amount of received light. A plurality of light receiving pixels arranged in a matrix, and the plurality of vertical shift registers sequentially transfer the signal charges in a direction along a column in synchronization with a read cycle of the signal charges for one row. The transfer rate of signal charge in the vertical shift register is relatively slow, and the dwell time when the charge packet is at the same position in the channel is relatively long. According to the present invention, a potential well and a potential barrier are formed in the channel along the charge transfer direction using the lower electrode during the dwell time, and the substrate surface is in an inverted state while holding the charge packet in the potential well. can do. Thereby, the dark current in the said stop time can be suppressed.

  A method of driving the solid-state imaging device, wherein the driving method according to the present invention is configured to transfer the charge packet composed of the signal charge into the channel between transfer operations of the vertical shift register for each reading cycle. In the operation of stopping, the voltage applied to the lower electrode is controlled, a potential well forming step for forming a potential well serving as a stopping position of the charge packet, and a predetermined inversion voltage is applied to the transfer electrode, An inversion layer forming step of inducing an inversion layer on the surface of the upper semiconductor layer.

  (7) Another solid-state imaging device according to the present invention is a frame transfer type solid-state imaging device having an imaging unit in which a plurality of light receiving pixels are configured by a plurality of vertical shift registers including the charge coupled device. In a frame transfer type solid-state imaging device, signal charges generated according to the amount of incident light are accumulated in an exposure period in a potential well formed along a channel of a vertical shift register. Is applied to transfer the charge packet. During this exposure period, charge packets are held at the same position for a relatively long time. Therefore, according to the present invention, the substrate surface can be inverted while forming a potential well and a potential barrier in the channel along the charge transfer direction using the lower electrode during the exposure period. As a result, dark current during the accumulation of signal charges in the potential well during the exposure period can be suppressed.

  A method of driving the solid-state imaging device, wherein the driving method according to the present invention is configured to perform an exposure operation in which a signal charge generated according to the amount of received light is accumulated in the channel as the charge packet for each light receiving pixel. A voltage applied to the lower electrode is controlled, a potential well forming step for forming a potential well for accumulating the signal charge for each light receiving pixel, and a predetermined inversion voltage is applied to the transfer electrode, An inversion layer forming step of inducing an inversion layer on the surface of the upper semiconductor layer.

    According to the configuration of the present invention, the occurrence and disappearance of potential fluctuations along the channel can be controlled according to the voltage applied to the lower electrode. With this configuration, when a charge packet is retained in the channel with the substrate surface in an inverted state, a potential well (storage phase) and a potential barrier (barrier phase) along the channel are formed. That is, the accumulation phase and the barrier phase can be formed without manipulating the impurity concentration of the channel. When transferring charge packets in a channel, each transfer electrode can be driven with a clock of the same amplitude by controlling the potential fluctuation caused by the lower electrode to disappear, simplifying the drive circuit Is planned. In addition, since it is not necessary to form the accumulation phase and the barrier phase by diffusing impurities into the channel, good charge transfer is realized without being affected by variations in impurity diffusion.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic plan view of a CCD image sensor according to an embodiment of the present invention. This CCD image sensor is a frame transfer type, and the imaging unit 20 includes light receiving pixels arranged in a matrix. The accumulation unit 22 accumulates signal charges for one screen obtained by the imaging unit 20, and the horizontal transfer unit 24 horizontally transfers signal charges read from the accumulation unit 22 in units of one row to the output unit 26 at high speed.

  The imaging unit 20 and the storage unit 22 are each configured by a plurality of vertical shift registers arranged in the row direction (direction along the row, that is, the horizontal direction), and each vertical shift register is configured by a CCD. Each vertical shift register 20v constituting the imaging unit 20 constitutes one row of light receiving pixels. That is, the vertical shift register 20v is configured so that light can enter the charge transfer channel, and the incident light accumulates charges generated in the depletion layer of the channel in a potential well formed corresponding to the pixel. The vertical shift register 22v in each column of the storage unit 22 is continuous with the vertical shift register 20v in the same column. When the exposure period ends, the signal charge is vertically transferred (frame transfer) from the imaging unit 20 to the storage unit 22 at high speed. The accumulation unit 22 is covered with a light shielding film and can hold signal charges obtained during the exposure period. The storage unit 22 performs vertical transfer (line transfer) of signal charges row by row in synchronization with the horizontal scanning period, and the signal charge for one row output from the final stage is transferred to the horizontal transfer unit 24 as described above. It is.

The vertical shift registers 20v and 22v of this apparatus are constituted by the CCD according to the present invention. Since the vertical shift registers 20v and 22v need to be able to be driven separately, they are applied with clocks independent of each other. Here, since they are three-phase clocks, they are represented by common symbols φ1 to φ1 for simplicity. Represented by φ3. The clocks φ1 to φ3 are clocks that are out of phase with each other by 2π / 3, have the same voltage amplitude, and both transition between two voltages V _L and V _H (V _L <V _H ).

  FIG. 2 is a schematic vertical sectional view along the charge transfer direction of the CCD constituting the vertical shift registers 20v and 22v. The semiconductor substrate 30 in the charge transfer region of the CCD includes a p-type semiconductor region composed of a P-sub layer (hereinafter simply referred to as P-sub) 32 and a P-well layer (hereinafter simply referred to as P-well) 34, and an inside thereof. A plurality of electrode regions 36 and 38 arranged along the transfer direction, and an N-well layer (hereinafter simply referred to as N-well) which is an n-type semiconductor layer located on the surface of the semiconductor substrate and provided on the P-well 34 40 is formed. An oxide film 42 is formed on the surface of the semiconductor substrate 30 as an insulating film, and a plurality of gate electrodes 44 are arranged along the transfer direction as transfer electrodes thereon.

  This CCD has a buried channel structure. That is, the potential of the depletion layer formed in the N-well 40 and the P-well 34 has an extreme value at a position away from the substrate surface, and the vicinity of the position becomes a channel for accumulating and transferring signal charges.

  In addition, the CCD is driven in three phases as described above, and correspondingly, the gate electrode 44 applies the gate electrode 44-1 to which the clock φ1 is applied, the gate electrode 44-2 to which the clock φ2 is applied, and the clock φ3. The gate electrodes 44-1 to 44-3 are periodically arranged.

  The electrode regions 36 and 38 are doped with impurities at a high concentration as described above, and are thereby formed with low resistance. The electrode regions 36 and 38 are controlled in potential independently of each other. The electrode regions 36 and 38 are alternately arranged, the position of the electrode region 38 in the transfer direction corresponds to the position of the gate electrode 44-1, and the position of the electrode region 36 is the position of the gate electrodes 44-2 and 44-3. Corresponds to the intermediate position.

  FIG. 3 is a schematic plan view of the charge transfer region of the CCD. The electrode regions 36 and 38 are both formed so as to cross the charge transfer region 50 where the N-well 40 is formed, perpendicularly to the charge transfer direction. Here, the electrode region 36 protrudes long from one outer region of the charge transfer region 50, and the electrode region 38 protrudes long from the other outer region. The electrode regions 36 and 38 are connected to wirings provided on, for example, the surface of the semiconductor substrate 30 at the protruding portions.

  FIG. 4 is a schematic vertical sectional view orthogonal to the charge transfer direction of the CCD, and shows a cross section at a position Y-Y ′ shown in FIG. 3. The electrode region 38 is guided to the substrate surface by a bridge portion 60 formed perpendicular to the P-well 34 outside the N-well 40, and is connected to the wiring 62 through a contact hole provided in the oxide film 42. The electrode region 36 is similarly connected to the wiring. The electrode regions 36 and 38 are connected to an external circuit through these wirings, and a voltage is applied from the external circuit.

For example, the above-described structure of the CCD can be formed using a silicon semiconductor substrate constituting the P-sub 32 as a base. Electrode regions 36 and 38 are formed by introducing n-type impurities into the surface of the silicon semiconductor substrate by ion implantation or the like. Thereafter, a silicon layer is epitaxially grown on the substrate surface. For example, a p-type impurity corresponding to the concentration of P-well 34 can be introduced into the growth film in advance. N-type impurities are introduced into the surface of the formed epitaxial layer by a process such as ion implantation and thermal diffusion to form an N-well 40 constituting the CCD of the imaging unit 20 and the storage unit 22. Further, other impurity regions constituting the horizontal transfer portion 24, the output portion 26, the element isolation region (channel stop region), and the like are also formed on the surface of the epitaxial layer. An oxide film 42 is formed on the surface of the epitaxial layer. For example, the oxide film 42 is formed by thermal oxidation. For example, a polysilicon layer is deposited on the oxide film 42 and patterned to form electrodes and wirings including the gate electrode 44. In order to form electrodes and wirings, a plurality of polysilicon layers and a metal layer such as aluminum or tungsten are used as necessary. For example, the gate electrode 44 is connected to a metal wiring formed in an upper layer via a contact hole, and is connected to a clock terminal supplied with φ1 to φ3 from the outside by the metal wiring. The electrode regions 36 and 38 are also connected to the wiring 62 through the bridge portion 60 as described above, and are connected to terminals to which a voltage is supplied from an external circuit through this wiring. Bridge unit 60, for example, and n ⁺ region formed by ion implantation of impurities, composed of n ⁺ region formed by depositing polysilicon in a hole drilled by dry etching.

  FIG. 5 is a schematic diagram showing a potential profile of the CCD in the substrate depth direction. 5A shows the vertical transfer operation, and FIG. 5B shows the accumulation operation. The vertical shift register of the imaging unit 20 performs an accumulation operation during the exposure period, and the vertical shift register of the accumulation unit 22 performs an accumulation operation between line transfers in one horizontal scanning period. In the figure, the vertical axis represents the potential, and the downward direction is positive. The horizontal axis is a position perpendicular to the substrate surface, with the left corresponding to the substrate front side and the right corresponding to the substrate back side. Each axis is an arbitrary scale.

During the transfer operation, three-phase clocks φ1 to φ3 are applied to the gate electrode 44. A potential curve 70 indicates a potential profile when the clock voltage V _H is applied to the gate electrode 44, and a potential curve 72 indicates a potential profile when the clock voltage _VL is applied to the gate electrode 44. The clock voltages V _H and V _L applied to the gate electrode 44 are determined according to the set value of the maximum charge handling amount of the CCD, the impurity profile, etc. Usually, the voltage V _H is a positive voltage of about several volts, while the voltage V _L is designed to be a negative voltage of about 0 or several volts. Here, _VL is a negative potential at which an inversion layer is formed at the interface between the oxide film 42 and the N-well 40. The voltages applied to the electrode regions 36 and 38 have the same potential, and are set to a predetermined voltage V _tr that is reverse biased or balanced with respect to the P-well 34. A predetermined voltage V _sub is applied to the P- _sub 32.

  For reference, FIG. 5 shows a potential curve 74 representing a potential profile in a vertical cross section that does not pass through the electrode regions 36 and 38 for reference. This potential curve 74 represents a situation where the influence of the electrode regions 36 and 38 can be ignored, for example, at a position sufficiently away from the electrode regions 36 and 38.

In driving during the transfer operation, the channel potential under each gate electrode 44 is controlled according to the voltage of the clock applied to the gate electrode 44. Here, the channel potential is defined as an extreme value in the depth direction at P-well 34 and N-well 40 (maximum value of potential depth). The channel potential under the gate electrode 44 to which V _H is applied becomes larger (deeper) than under the gate electrode 44 to which V _L is applied, and a charge packet is held in a deep portion (potential well) of this channel potential. The During transfer operation, at least one of the gate electrode 44-1～44-3 is applied to V _L, the channel potential is shallow portion under the gate electrode 44 applies the V _L (potential barrier) is, The charge packets stored under the adjacent gate electrode 44 are separated from each other. The charge packet is moved along the channel by sequentially switching the position of the accumulation phase where the potential well is formed and the position of the barrier phase where the potential barrier is formed by the three-phase clock.

On the other hand, during the accumulation operation, the interface between the oxide film 42 and the N-well 40 is basically always in an inverted state. Therefore, _VL is applied to each gate electrode 44. On the other hand, by applying a potential difference to the electrode regions 36 and 38, a potential well (accumulation phase) and a potential barrier (barrier phase) are formed in the channel. A potential curve 76 indicates a potential profile when the voltage V _st is applied to the electrode region and the channel potential of the channel above the electrode region is deepened. A potential curve 78 indicates a voltage V _br lower than the voltage V _{st in the} electrode region. The potential profiles when the channel potential on the electrode region is made shallower by applying, are shown. Here, the case where V _br is set to the same value as V _tr and V _st is set to a voltage higher than V _tr is shown, and the potential curve 78 basically matches the potential curve 72. Incidentally, the _{V st} is set to the same value as the _{V tr Conversely,} it may be set _{V br} lower voltage than _{V tr, also} be set to a value different from both of the _{V st,} V _br V _tr You can also.

Here, a potential well is formed under two of the set of three gate electrodes 44 driven in three phases, and a potential barrier is formed under the remaining one. In this CCD, as shown in FIG. 2, the electrode region 36 is disposed below the intermediate position between the two gate electrodes 44-2 and 44-3, and the electrode region 38 is disposed below the gate electrode 44-1. ing. This controls the channel potential under the gate electrodes 44-2 and 44-3 by the electrode region 36 and holds the charge packet therein, while the channel potential under the gate electrode 44-1 is held by the electrode region 38. This is to control and form a potential barrier here. Therefore, the transition from the transfer operation to the accumulation operation is performed in a state where charge packets are accumulated under the gate electrodes 44-2 and 44-3. V _H is applied to the gate electrodes 44-2 and 44-3, and the transfer is stopped in a state where the charge packet is held under the gate electrodes 44. The voltage of the electrode region 36 is set to the voltage V _st and the voltage of the electrode region 38 is set to V _br . Thereafter, the voltage levels of the clocks φ2 and φ3 corresponding to the gate electrodes 44-2 and 44-3 are switched from V _H to V _L. As a result, the voltage _VL is applied to each of the gate electrodes 44-1 to 44-3, and the interface between the oxide film 42 and the N-well 40 under each gate electrode 44 is inverted. In this state, the potential profile in the cross section along the position corresponding to the electrode region 36, for example, the position Z1-Z1 ′ shown in FIG. 2, corresponds to the potential curve 76, and the potential in the cross section along the position Z2-Z2 ′. The profile corresponds to the potential curve 78.

  Here, the electrode regions 36 and 38 can also serve as an overflow drain. For example, when an electronic shutter operation is performed in the imaging unit 20, conventionally, a voltage is applied to the back surface of the substrate, and signal charges held in the channel are discharged to the back surface of the substrate. Similarly, in this CCD, when the signal charges accumulated in the imaging unit 20 or the accumulation unit 22 are discharged in a batch without being read out to the output unit 26, a high positive voltage is applied to the electrode regions 36 and 38. Thus, the potential barrier formed by the P-well 34 between the channel and the electrode regions 36 and 38 is lowered. As a result, the signal charge held in the channel passes through the P-well 34 and is sucked and discharged to the electrode regions 36 and 38.

  In the transfer operation, the electrode regions 36 and 38 are set to the same potential as already described. The electrode regions 36 and 38 are discretely arranged with a p-type region in between with respect to the charge transfer direction. In a horizontal plane including these electrode regions 36 and 38, along the arrangement direction of the electrode regions 36 and 38. The potential can vary periodically. However, the potential fluctuation is smoothed and alleviated on the channel due to the distance between the channel and the electrode regions 36 and 38. On the other hand, when it is desired to suppress the potential fluctuation caused by the electrode regions 36 and 38 on the channel more preferably, the potential fluctuation itself on the horizontal plane including the electrode regions 36 and 38 may be reduced. For this purpose, the potentials of the electrode regions 36 and 38 are lowered according to the potentials of the surrounding p-type regions (P-sub 32 and P-well 34) (corresponding to being moved upward in FIG. 5). Here, when the potentials of the electrode regions 36 and 38 are lowered, the potentials of the surrounding p-type regions that are dragged therewith are also lowered, but the potentials of the electrode regions 36 and 38 are not affected by the electrode regions 36 and 38. The potential fluctuation amplitude on the horizontal plane including the electrode regions 36 and 38 can be reduced as the potential approaches the potential on the potential curve 74. This potential fluctuation can be a problem in that it basically degrades the transfer efficiency of charge packets during the transfer operation, but it does not cause any particular problem during the storage operation. Therefore, at the time of a transfer operation in which it is not necessary to control the channel potential by the electrode regions 36 and 38, the potential of the electrode regions 36 and 38 is changed as described above to reduce the potential fluctuation, and the electrode regions 36, It is possible to drive so as to control the channel potential according to the voltage applied to 38.

Note that the transition from the accumulation operation to the transfer operation is performed in the reverse procedure to the transition from the transfer operation to the accumulation operation. That is, first, _VH is applied to the gate electrodes 44-2 and 44-3, and then the electrode region 36 and the electrode region 38 are set to the same potential. Thereafter, driving of the clocks φ1 to φ3 is started to start transfer of charge packets.

  Further, although the above-described CCD image sensor is a frame transfer type, the CCD of the interline type CCD image sensor can be configured in the same manner. For example, the CCD constituting the vertical shift register of the interline CCD image sensor is configured as the above-described CCD, thereby reducing the dark current by inverting the interface between the oxide film 42 and the N-well 40 between line transfers. This is possible without inconvenience such as complication of the drive circuit.

  Furthermore, the above-described present invention can also be applied to CCDs other than the three-phase drive and CCDs constituting the horizontal transfer unit 24. In addition, a configuration in which the n-type and p-type of each semiconductor region are inverted, and a configuration in which electrodes corresponding to the electrode regions 36 and 38 and disposed under the channel are formed of metal are possible.

  Various arrangements other than those described above are possible for the arrangement of the electrode regions for controlling the channel potential while inverting the interface between the oxide film 42 and the N-well 40 during the accumulation operation. Some examples are shown below as examples. In these embodiments, the same components as those described above are denoted by the same reference numerals to simplify the description.

  FIG. 6 is a schematic vertical sectional view along the charge transfer direction of the CCD according to the present embodiment. This configuration is different from the configuration shown in FIG. 2 in that one electrode region 36 or one electrode region 38 is disposed under each gate electrode 44. For example, one electrode region 36 is disposed under each of the gate electrodes 44-2 and 44-3 that hold charge packets during the accumulation operation, while an electrode region 38 is disposed under the gate electrode 44-1. Be placed. That is, when the electrode region 36 is represented by the symbol “A” and the electrode region 38 is represented by the symbol “B”, the electrode regions are A, A, B, A, A, B,... In synchronization with the arrangement period of the gate electrodes 44. It is arranged with the pattern.

During the transfer operation, the electrode regions 36 and 38 are set to the same potential _Vtr . On the other hand, during the accumulation operation, V _st is applied to the electrode region 36 and the channel above it is used as the storage phase, and V _br is applied to the electrode region 38 and the channel above it is used as the barrier phase.

  FIG. 7 is a schematic vertical sectional view along the charge transfer direction of the CCD according to the present embodiment. 2 is different from the configuration shown in FIG. 2 in that the electrode region 38 is not formed only by the electrode region 36 and that the N-type semiconductor layer is formed over the entire charge transfer region under the P-sub 32. A −sub layer (hereinafter simply referred to as “N-sub”) 90 is provided. A voltage is applied to the N-sub 90 from an external circuit.

During the transfer operation, the electrode region 36 is applied with a voltage corresponding to the potential of the P-sub 32 when it is not provided. On the other hand, during the accumulation operation, V _st is applied to the electrode region 36 and a predetermined positive voltage V _st ′ is applied to the N-sub 90. The electrode region 36 has a strong influence on the channel below the gate electrodes 44-2 and 44-3, and has a relatively weak influence on the channel below the gate electrode 44-1. That is, by controlling V _st and V _st ′, the channel potential below the gate electrodes 44-2 and 44-3 is relatively deep and the channel potential below the gate electrode 44-1 is relatively shallow. In the accumulation operation in which the interface between the oxide film 42 and the N-well 40 is inverted, charge packets can be held under the gate electrodes 44-2 and 44-3.

  Note that the N-sub 90 can be omitted only for forming an accumulation phase and a barrier phase in the channel during the accumulation operation. On the other hand, by providing the N-sub 90 as in this configuration, a uniform overflow drain can be realized for the channel under each gate electrode 44. That is, when the signal charges of the imaging unit 20 or the storage unit 22 are discharged all at once, a large positive voltage is applied to the N-sub 90 so that the signal charge on the channel is reduced regardless of the arrangement of the electrode regions 36. Are discharged.

1 is a schematic plan view of a CCD image sensor according to an embodiment of the present invention. It is a typical vertical sectional view along the charge transfer direction of the CCD constituting the vertical shift register of the CCD image sensor according to the embodiment. 2 is a schematic plan view of a charge transfer region of the CCD. FIG. 2 is a schematic vertical sectional view orthogonal to the charge transfer direction of the CCD. FIG. It is a schematic diagram which shows the electric potential profile of the substrate depth direction of this CCD. FIG. 3 is a schematic vertical sectional view along the charge transfer direction of the CCD according to the first embodiment. It is a typical vertical sectional view along the charge transfer direction of the CCD according to the second embodiment. It is typical sectional drawing along the transfer direction of CCD by a prior art.

Explanation of symbols

  20 Image pickup unit, 22 Storage unit, 24 Horizontal transfer unit, 26 Output unit, 30 Semiconductor substrate, 32 P-sub layer, 34 P-well layer, 36, 38 Electrode region, 40 N-well layer, 42 Oxide film, 44 Gate electrode, 50 charge transfer region, 60 bridge portion, 62 wiring, 90 N-sub layer.

Claims (16)

A charge transfer region in which a buried channel is formed by an upper semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate and a lower semiconductor layer of a second conductivity type located below the upper semiconductor layer; and the charge transfer A charge coupled device having a plurality of transfer electrodes arranged in a charge transfer direction on the region and controlling a potential of the channel by the transfer electrode to transfer a charge packet in the channel;
A plurality of lower electrodes arranged along the charge transfer direction under the channel and changing the potential of the channel via the lower semiconductor layer according to a voltage applied from the outside;
A charge-coupled device. The charge coupled device of claim 1.
The lower electrode includes a first lower electrode and a second lower electrode whose potential is controlled from the outside separately from each other,
The first lower electrode and the second lower electrode are mixed with each other in a predetermined arrangement order and arranged in the charge transfer direction;
A charge-coupled device. The charge coupled device of claim 2.
The first lower electrode and the second lower electrode are alternately arranged by a predetermined number, each with an arrangement period of charge packet trains in the channel as a repetition period,
A charge-coupled device. The charge coupled device of claim 1.
A back electrode layer disposed along the charge transfer region under the lower electrode and changing the potential of the channel through the lower semiconductor layer according to a voltage applied from the outside independently of the lower electrode Have
A predetermined number of the lower electrodes are disposed at each electrode formation position provided at predetermined intervals in the charge transfer direction;
A charge-coupled device. The charge coupled device according to claim 4.
The electrode forming position is provided below one of a stopping position for stopping the charge packets in the channel or a separation position for separating the stopped charge packets;
A charge-coupled device. The charge coupled device according to claim 4 or 5,
The back electrode layer is formed of a semiconductor region of a first conductivity type;
A charge-coupled device. The charge coupled device according to any one of claims 1 to 6,
The lower electrode is a semiconductor region of a first conductivity type formed in the lower semiconductor layer;
A charge-coupled device. A method for driving a charge coupled device according to any one of claims 1 to 7, comprising:
In the operation of stopping the clock applied to the transfer electrode and stopping the charge packet in the channel,
A potential well forming step of controlling a voltage applied to the lower electrode to form a potential well serving as a stop position of the charge packet;
An inversion layer forming step of applying a predetermined inversion voltage to the transfer electrode to induce an inversion layer on a surface of the upper semiconductor layer;
A driving method comprising: A method for driving a charge coupled device according to claim 2 or claim 3, comprising:
In an operation of stopping a clock applied to the transfer electrode and stopping a plurality of the charge packets in the channel,
The voltage applied to the first lower electrode is controlled to form a potential well at the stopping position of each charge packet, and the voltage applied to the second lower electrode is controlled to A potential well row forming step for forming a potential barrier to be separated;
An inversion layer forming step of applying a predetermined inversion voltage to the transfer electrode to induce an inversion layer on a surface of the upper semiconductor layer;
A driving method comprising: The driving method according to claim 9, wherein
The method of driving a charge coupled device, wherein when the clock is applied to the transfer electrode to transfer the charge packet, the first lower electrode and the second lower electrode have the same potential. A method for driving a charge coupled device according to claim 4 or claim 5, comprising:
In an operation of stopping a clock applied to the transfer electrode and stopping a plurality of the charge packets in the channel,
The voltage applied to each of the lower electrode and the back electrode layer is controlled so that either one of the potential well serving as a stopping position of each charge packet and the potential barrier separating the potential wells are included in the channel. Forming a potential well row at a position corresponding to an electrode forming position and forming the other at a position corresponding to a gap between the electrode forming positions;
An inversion layer forming step of applying a predetermined inversion voltage to the transfer electrode to induce an inversion layer on a surface of the upper semiconductor layer;
A driving method characterized by comprising: A shift register comprising the charge coupled device according to any one of claims 1 to 7,
A plurality of light receiving pixels formed on the semiconductor substrate and generating signal charges according to the amount of received light;
Have
A solid-state imaging device, wherein the signal charge is transferred by the shift register. A plurality of vertical shift registers comprising the charge coupled device according to any one of claims 1 to 7,
A plurality of light receiving pixels arranged on the semiconductor substrate and arranged in a matrix to generate a signal charge according to the amount of received light;
Have
The solid-state imaging device, wherein the plurality of vertical shift registers sequentially transfer the signal charges in a direction along a column in synchronization with a read cycle of the signal charges for one row. The method for driving the solid-state imaging device according to claim 13,
In the operation of stopping the charge packet consisting of the signal charge in the channel between the transfer operations of the vertical shift register for each read cycle,
A potential well forming step of controlling a voltage applied to the lower electrode to form a potential well serving as a stop position of the charge packet;
An inversion layer forming step of applying a predetermined inversion voltage to the transfer electrode to induce an inversion layer on a surface of the upper semiconductor layer;
A driving method comprising:   A frame transfer type solid-state imaging device having an imaging unit in which a plurality of light receiving pixels are configured by a plurality of vertical shift registers including the charge coupled device according to any one of claims 1 to 7. The method for driving the solid-state imaging device according to claim 15,
In an exposure operation for accumulating signal charges generated according to the amount of received light in the channel as the charge packets for each light receiving pixel,
A potential well forming step of controlling a voltage applied to the lower electrode to form a potential well for storing the signal charge for each light receiving pixel;
An inversion layer forming step of applying a predetermined inversion voltage to the transfer electrode to induce an inversion layer on a surface of the upper semiconductor layer;
A driving method comprising:

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