JP2005241748A - Driving circuit for display apparatus and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit for a display apparatus capable of controlling power consumption according to a required function. <P>SOLUTION: The driving circuit includes an operational amplifier OP capable of controlling operation which amplifies a reference voltage with a gain of approximately 1. An input of the operational amplifier OP is connected to a reference voltage holding circuit and the reference voltage holding circuit is connected to an input terminal IN in which the reference voltage is selected via a switch S1. An output of the operational amplifier OP is connected to an output terminal OUT. Furthermore, the input terminal IN is connected to the output terminal OUT via a switch S2. The driving circuit is controlled by control signals Z1, Z2 and X. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a driving circuit that emits light from a pixel of a display device and a driving method thereof.

  Conventionally, when an image is displayed on a liquid crystal display, an electroluminescence (EL) display, or the like, a driving circuit for supplying power to each pixel constituting the screen has been used.

  FIG. 7 shows an example of the configuration of the drive circuit 100 of the display device 200 in which the image signal S is arranged in 64 pixels in the horizontal direction and each pixel is expressed by a digital signal of 4 bits (16 gradations). The drive circuit 100 includes a reference voltage supply circuit 50, a reference voltage selection circuit 52, and an image signal input unit 54, and drives the display device 200 in a so-called line sequential manner. The reference voltage supply circuit 50 divides the voltage V supplied from the power supply by resistors R1 to R16 and supplies the divided voltage as reference voltages V1 to V16 to the reference voltage selection circuit 52. The image signal input unit 54 receives the input of the image signal S, and sets any one of the 16 bit lines to “H level” according to the gradation of each pixel of the image signal represented by a 4-bit digital signal. To the reference voltage selection circuit 52. The reference voltage selection circuit 52 includes pixel unit selection circuits 52-1 to 52-64 for 64 pixels each including 16 transistors Tr1 to Tr16. Each bit line of the image signal for one pixel is connected to the gate terminals of the transistors Tr1 to Tr16 included in each pixel unit selection circuit 52-1 to 52-64. Reference voltages V1 to V16 are supplied from the reference voltage supply circuit 50 to the source terminals of the transistors Tr1 to Tr16, respectively. Accordingly, only the transistors whose bit lines connected to the gate terminals of the transistors Tr1 to Tr16 are at “H level” are turned on, and the pixel unit selection circuits 52-1 to 52-64 have the reference voltage V1. ~ V16 is selected and output. Each pixel constituting the display device 200 includes a capacitive component C, and the capacitive component C is charged and discharged until the reference voltages V1 to V16 output from the pixel unit selection circuits 52-1 to 52-64 are obtained. . The charged / discharged reference voltage of the capacitive component C becomes a driving voltage for each pixel, and each pixel of the display device 200 is caused to emit light.

  Here, the display device 200 is a liquid crystal display, an electroluminescence (EL) display, or the like in which pixels connected to the pixel unit selection circuits 52-1 to 52-64 are arranged in a matrix. It does not matter whether these display devices 200 are so-called passive types or active types.

  The voltage output from the drive circuit 100 is selected by the reference voltage selection circuit 52 as one of the reference voltages V1 to V16. For example, in the pixel for which the reference voltage V1 is selected as the drive voltage, the same reference voltage V1 is supplied to all the pixels. Therefore, assuming that the characteristics of each pixel of the display device are equal, any pixel to which the reference voltage V1 is supplied can emit light with equal intensity corresponding to the reference voltage V1. Similarly, any pixel for which the reference voltages V2 to V16 are selected can emit light with an intensity corresponding to each of the reference voltages V2 to V16.

  However, as the number of pixels included in the display device 200 increases, the power consumption of the display device 200 increases, and accordingly, the supply power of the power source included in the reference voltage supply circuit 50 needs to be increased. Further, there is a problem that the capacity value of the entire display device 200 in which the capacitance component C included in each pixel is added becomes large, and the time for charging and discharging the driving voltage of each pixel to the reference voltages V1 to V16 becomes long.

In order to solve these problems, as shown in FIG. 8, a drive circuit to which an operational amplifier OP for amplifying the voltage output to each pixel unit selection circuit 52-1 ′ to 52-64 ′ is added is disclosed. ing. Thereby, power can be supplied to the display device 200 independently of the power supplied from the power supply of the reference voltage supply circuit 50, and the time for charging and discharging the capacitance component C of each pixel to the reference voltage can be shortened. In addition, in the pixel in which the same reference voltage is selected by disconnecting the connection between the operational amplifier and the capacitance component C of each pixel after the predetermined time has elapsed, and directly connecting the capacitance component C of each pixel to the reference voltage. Pixels can also emit light with equal intensity.
Japanese Patent No. 3226567

  However, in the above prior art, the period during which the operational amplifier is operated and the period during which the capacitance component C of each pixel is directly connected to the reference voltage are alternatives, and the degree of freedom of operation in the drive circuit is small. For this reason, there is a problem in that the reference voltage must be continuously supplied to the operational amplifier during a period in which the operational amplifier is operated, and power consumption in the entire circuit cannot be reduced. In addition, the power consumption of the drive circuit is reduced within the required charge / discharge time range between the still image and the moving image even though the time required to charge and discharge the capacitance component C of each pixel required for the drive circuit is different. On the other hand, even if the power consumption is sacrificed, it is difficult to realize the reduction in the time for charging / discharging the capacitance component C of each pixel. That is, the power consumption cannot be controlled in accordance with the performance of the operation speed at which each pixel is driven.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a display device driving circuit and a driving method thereof that can control power consumption in accordance with required performance.

  The present invention is a drive circuit for a display device, which includes an input terminal to which a reference voltage is applied, a reference voltage holding circuit that holds and outputs the reference voltage, and a reference voltage held by the reference voltage holding circuit. An amplifier having a gain of approximately 1 connected to an output terminal to which an output point is connected and an output connected to a pixel of the display device, and a first amplifier connected between the input terminal and the reference voltage holding circuit. 1 switch and a second switch connected between the input terminal and the output terminal.

  Here, the amplifier includes a comparator that compares the voltage level of the output point of the reference voltage held by the reference voltage holding circuit and the output terminal to change the output level, and from the comparator Depending on the output level, the output terminal can be connected to a power supply or ground, and the amplifier can be inactivated based on the output level from the comparator.

  According to the present invention, the power consumption or the operation speed at which each pixel is driven can be controlled in accordance with the performance required for the drive circuit of the display device.

<First Embodiment>
The drive circuit 150 of the display device 200 according to the first embodiment of the present invention includes a reference voltage supply circuit 60, a reference voltage selection circuit 62, and an image signal input unit 64 as shown in FIG. The reference voltage supply circuit 60 is configured by connecting a switch S3, resistors R1 to R16, and a switch S4 in series. The switch S3 is a P-channel MOS transistor, and the switch S4 is an N-channel MOS transistor.

  The switches S3 and S4 are turned on and off by control signals Y1 and Y2 input to the gate terminals. When both the switches S3 and S4 are turned on, the voltage V supplied from the power source is applied to the resistors R1 to R16. And supplied to the reference voltage selection circuit 62 through the wirings L1 to L16 as reference voltages V1 to V16. On the other hand, when both the switches S3 and S4 are off, the reference voltage is not supplied to the wirings L1 to L16.

  The image signal input unit 64 is the same as the image signal input unit 54 of FIG.

  The reference voltage selection circuit 62 includes pixel unit selection circuits 62-1 to 62-64 for 64 pixels. Each pixel unit selection circuit 62-1 to 62-64 has the same configuration, and as shown in FIG. 2, the pixel unit selection circuit 62-1 includes 16 transistors Tr1 to Tr16, which are connected to the gate terminals of the transistors Tr1 to Tr16. Are connected to each bit line of an image signal for one pixel. Further, wirings L1 to L16 from the reference voltage supply circuit 60 are connected to the source terminals of the transistors Tr1 to Tr16, respectively. Accordingly, only the transistors whose bit lines connected to the gate terminals of the transistors Tr1 to Tr16 are at “H level” are turned on, and any of the wirings L1 to L16 is connected to the pixel unit selection circuit 62-1. Is done. At this time, if the reference voltages V1 to V16 are output to the wirings L1 to L16, any one of the reference voltages V1 to V16 is output to the input terminal IN of the pixel unit selection circuit 62-1.

  In addition, an operational amplifier OP is added to the pixel unit selection circuit 62-1 as an amplifier capable of controlling operation with a gain of approximately 1 in order to amplify the reference voltages V1 to V16 output to the input terminal IN. A reference voltage holding circuit is connected to the input terminal IN ′ of the operational amplifier OP, and the reference voltage holding circuit is connected to the input terminal IN from which the reference voltage is output via the switch S1. The output of the operational amplifier OP is connected to the output terminal OUT of the pixel unit selection circuit 62-1, and the operation of the operational amplifier OP is controlled by the control signal X. Further, the input terminal IN is connected to the output terminal OUT via the switch S2.

For example, the reference voltage holding circuit is configured by a capacitor Cvin. The switch S1 is an N-channel MOS transistor, and is controlled to be turned on / off by a control signal Z1. The switch S2 is also an N-channel MOS transistor, and is controlled to be turned on / off by the control signal Z2. The capacitor Cvin continues to hold the reference voltage Vin output to the input terminal IN when the switch S1 is turned on even after the switch S1 is turned off. In this way, the operational amplifier OP operates to set the output terminal OUT connected to the capacitance component C of each pixel to the voltage Vin held in the reference voltage holding circuit, whereby the capacitance component C of each pixel of the display device 200 is operated. Is charged and discharged quickly. Then, after the predetermined time has elapsed, the connection between the operational amplifier OP and the output terminal OUT having a variation in gain characteristics is disconnected, and the switch S2 is turned on to directly connect the input terminal IN to the output terminal OUT, so that the same reference voltage is selected. Any pixel can emit light with equal intensity.
In the above embodiment, each switch is an N-channel or P-channel MOS transistor, but other configurations such as an analog switch may be used.

FIG. 3 is a timing chart showing the operation of the drive circuit according to the first embodiment of the present invention. Timings t _{0 to} t ₄ , t _{4 to} t ₈ , and t _{8 to} t ₁₂ each represent one horizontal period, and the reference voltages selected by the pixel unit selection circuits 62-1 to 62-64 for each of these periods. Vin changes.

At timing t ₀ , the reference voltage supply circuit 60 turns on the switches S 3 and S 4 by the control signals Y 1 and Y 2 and supplies the reference voltages V 1 to V 16 to the reference voltage selection circuit 62. At this time, the reference voltage Vin output to the input terminal IN of the pixel unit selection circuit 62-1 is changed by a signal from the image signal input unit 64. In addition, the switch S1 of the pixel unit selection circuit 62-1 is turned on by the control signal Z1, and the switch S2 is turned off by the control signal Z2. As a result, the capacitance component C of each pixel is disconnected from the load of the reference voltage supply circuit 60 and only Cvin having a small capacitance value is connected. Therefore, the capacitor Cvin connected to the input terminal IN ′ of the operational amplifier OP is connected to the reference voltage Vin. Charges and discharges quickly.

At timing _{t 1,} the switch S1 is turned off by the control signal Z1, capacitor Cvin is holds the reference voltage Vin, the switch S2 is turned on by the control signal Z2. Thus, the output terminal OUT connected to the capacitance component C of the pixel is directly connected to the input terminal IN. When the voltage level of the output terminal OUT is higher than the input terminal IN, the output terminal OUT is connected to the input terminal IN through the input terminal IN. Thus, a current flows through the wirings L1 to L16. Conversely, when the voltage level on the output terminal OUT side is lower than the input terminal IN, current flows from the wirings L1 to L16 to the output terminal OUT side via the input terminal IN. As described above, since each capacitor component C of each pixel exchanges charges via the wirings L1 to L16, each output terminal OUT connected to the capacitor component C of each pixel is connected while reducing power consumption. It can be brought close to a desired voltage.

At timing _{t 2,} the control signals Y1, Y2, a reference voltage supply circuit 60 turns off the switch S3, S4. For this reason, the reference voltage supply circuit 60 does not consume power. At the same time, the switch S2 is turned off by the control signal Z2, and the operational amplifier OP is brought into an operating state by the control signal X. Due to the operation of the operational amplifier OP, the output terminal OUT is rapidly charged and discharged to the reference voltage Vin held in the capacitor Cvin connected to the input terminal IN ′.

At timing t ₃ , the reference voltage supply circuit 60 turns on the switches S 3 and S 4 by the control signals Y 1 and Y 2 and supplies the reference voltages V 1 to V 16 to the reference voltage selection circuit 62 again. At the same time, the switch S2 is turned on by the control signal Z2, and the operational amplifier OP is deactivated by the control signal X. As a result, the output terminal OUT is directly connected to the input terminal IN, and any pixel in which the same reference voltage is selected can emit light with equal intensity.

In the timing chart of FIG. 3, at timings t _{4 to} t ₇ , the same operation as the timings t _{0 to} t ₃ is performed, and thereafter the same operation is repeated.

FIG. 4 is a timing chart showing another operation of the drive circuit according to the first embodiment of the present invention. Timings t _{0 to} t ₃ , t _{3 to} t ₆ , and t _{6 to} t ₉ each represent one horizontal period, and each pixel unit selection circuit 62-1 to 62-64 selects a reference voltage for each period. Vin changes.

At timing t ₀ , the reference voltage supply circuit 60 turns on the switches S 3 and S 4 by the control signals Y 1 and Y 2 and supplies the reference voltages V 1 to V 16 to the reference voltage selection circuit 62. At this time, the reference voltage Vin output to the input terminal IN of the pixel unit selection circuit 62-1 is changed by a signal from the image signal input unit 64. In addition, the switch S1 of the pixel unit selection circuit 62-1 is turned on by the control signal Z1, and the switch S2 is turned off by the control signal Z2. As a result, the capacitor Cvin connected to the input terminal IN ′ of the operational amplifier OP is quickly charged and discharged to the reference voltage Vin.

At timing _{t 1,} the switch S1 is turned off by the control signal Z1, capacitor Cvin is holds the reference voltage Vin, the switch S2 is turned on by the control signal Z2. At the same time, the operational amplifier OP is brought into an operating state by the control signal X. At this time, even if the reference voltage output from the wirings L1 to L16 fluctuates because the load of the capacitance component C of the pixel is large, the input terminal IN ′ of the operational amplifier OP holds the reference voltage Vin, so that the operational amplifier OP Operates so that the output terminal OUT becomes the reference voltage Vin. As described above, the capacitance component C of each pixel connected to each output terminal OUT is charged / discharged by the reference voltage supply circuit 60 directly connected via the input terminal IN as well as charging / discharging by the operational amplifier OP. It is driven to the reference voltage Vin in a very short time.

At timing t ₂ , the operational amplifier OP is deactivated by the control signal X. As a result, the output terminal is directly connected only to the reference voltage via the input terminal IN, and any pixel with the same reference voltage selected can emit light with equal intensity.

In the timing chart of FIG. 4, at timings t _{3 to} t ₅ , the same operation as the timings t _{0 to} t ₂ is performed, and thereafter the same operation is repeated.

  FIGS. 3 and 4 are examples of timing charts showing the operation of the drive circuit according to the first embodiment of the present invention. In accordance with the performance required for the drive circuit of the display device, power consumption or The operation speed is appropriately changed so as to control the operation speed at which each pixel is driven.

In other words, when it is desired to increase the operation speed even when the power consumption increases, the operational amplifier OP is operated as soon as possible after the reference voltage Vin is held in the reference voltage holding circuit. Further, the operation period of the operational amplifier OP and the period in which the input terminal IN and the output terminal OUT are directly connected are overlapped, and the overlap period is lengthened. On the other hand, when it is desired to reduce power consumption even when the operation speed is slow, a period for directly connecting the input terminal IN and the output terminal OUT is provided after the reference voltage holding circuit holds the reference voltage Vin. Does not operate the operational amplifier OP. Then, when the operational amplifier OP is subsequently operated, it is operated as late as possible. Further, during the operation period of the operational amplifier OP, the input terminal IN and the output terminal OUT are disconnected by the switch S2, and the operation of the reference voltage supply circuit 60 is stopped.
<Second Embodiment>
The drive circuit of the display device 200 in the second embodiment of the present invention is the same as that in the first embodiment, but the operational amplifier OP is set to the reference voltage Vin whose output terminals OUT are held in the reference voltage holding circuit. When it reaches, it is automatically deactivated.

  As shown in FIG. 5, the operational amplifier 40 in the second embodiment includes a comparator 10, a latch circuit 12, a delay circuit 14, a delay circuit 22, an AND circuit 24, a fluctuation detection circuit 30, and switches TR1, TR2, and TR4. Consists of. In the operational amplifier 40, the switches TR2 and TR4 are N-channel MOS transistors. The switch TR1 is a P-channel MOS transistor.

  A reference voltage holding circuit is connected to the input terminal IN ′, and a capacitance component C constituting a pixel of the display device 200 is connected to the output terminal OUT. The comparator 10 constitutes a differential amplifier. When the switch TR3 is on, the comparator 10 compares the voltage levels of the input terminal IN 'and the output terminal OUT, and changes the voltage level of the output terminal OUT according to the magnitude relationship. In the comparator 10, the output level of the comparator 10 is switched between “H level” and “L level” with a line where the voltage levels of the input terminal IN ′ and the output terminal OUT are just equal. The output level of the output terminal A of the comparator 10 is “L level” when the voltage level of the input terminal IN ′ is smaller than the voltage level of the output terminal OUT, and the voltage level of the input terminal IN ′ is the voltage of the output terminal OUT. In an area larger than the level, it becomes “H level”. The output terminal A of the comparator 10 is connected to the input terminals of the delay circuit 14 and the fluctuation detection circuit 30 via NOT elements. When the switch TR3 is off, no power is supplied to the comparator 10 from the power source Vc, and the operation of the comparator 10 can be stopped.

The fluctuation detection circuit 30 includes a delay circuit 32 and an XOR element 34. An inverted signal φ of the output from the output terminal A of the comparator 10 is input to the XOR element 34 and the input terminal of the delay circuit 32. The delay circuit 32 delays the inverted signal φ by a predetermined delay time τ _{2 and} outputs it as a delay signal φ ′. The delay signal φ ′ is input to the input terminal of the XOR element 34. The XOR element 34 calculates and outputs an exclusive OR of the inverted signal φ and the delayed signal φ ′. Therefore, during the period when the inversion signal φ is not changing, the output of the fluctuation detection circuit 30 is maintained at “L level”. On the other hand, when the inverted signal φ changes from “H level” to “L level” or from “L level” to “H level”, the output of the fluctuation detection circuit 30 changes from “L level” to “H level”. When the delay time τ _{2 has} elapsed since the change of the inversion signal φ, the “H level” is returned to the “L level” again. The output of the fluctuation detection circuit 30 is input to the source terminal of the switch TR4.

  The drain terminal of the switch TR4 is connected to the input terminal of the latch circuit 12. The output terminal of the latch circuit 12 is connected to the input terminal of the OR element 20. When the switch TR4 is on, the inversion level of the output of the fluctuation detection circuit 30 is held by the latch circuit 12, and is output to the output terminal as the output signal β. In the operational amplifier 40, the latch circuit 12 is configured by a loop circuit of NOT elements, but is not limited to this.

A control signal X supplied from the outside of the operational amplifier 40 is input to the OR element 20 together with the output β of the latch circuit 12. The output terminal of the OR element 20 is directly connected to the switches TR3 and TR4. The output terminal of the OR element 20 is directly connected to the input terminal of the AND element 24, and is also connected to the input terminal of the AND element 24 through the delay circuit 22. The output terminal of the AND element 24 is directly connected to the input terminal of the AND element 28 and is also connected to the OR element 26 via the NOT element. Here, the delay time τ ₃ of the delay circuit 22 is set longer than the delay time τ ₁ of the delay circuit 14.

  With such a configuration, the OR element 26, the AND element 28, and the switches TR3 and TR4 are controlled by the control signal X and the output β of the latch circuit 12.

The delay circuit 14 receives the inverted signal φ, delays the output level by a predetermined delay time τ ₁ and outputs the delayed output level. The output terminal of the delay circuit 14 is connected to the input terminals of the OR element 26 and the AND element 28. The output terminal of the OR element 26 is connected to the gate terminal of the switch TR1. The output terminal of the AND element 28 is connected to the gate terminal of the switch TR2. Therefore, switching between the source terminal and the drain terminal of the switches TR1 and TR2 is controlled with a delay time τ ₁ in accordance with the change of the inverted signal φ.

  The source terminal of the switch TR1 is connected to the power supply Vc, and the drain terminal is connected to the output terminal OUT. The source terminal of the switch TR2 is connected to the ground (GND), and the drain terminal is connected to the output terminal OUT. The switch TR1 is turned on when the output of the delay circuit 14 is “L level” and the output of the AND element 24 is “H level”, and the output of the delay circuit 14 is “H level” or the output of the AND element 24 is “L”. “Level” turns off. On the other hand, the switch TR2 is turned on when the output of the delay circuit 14 is “H level” and the output of the AND element 24 is “H level”, and the output of the delay circuit 14 or the output of the AND element 24 is “L level”. If there is, it is turned off. If the switch TR1 is on, the output terminal OUT is connected to the power source Vc and the capacitive component C is charged. If the switch TR2 is on, the output terminal OUT is connected to the ground GND and the capacitive component C is discharged.

  FIG. 6 is a timing chart showing the operation of the drive circuit according to the second embodiment of the present invention.

The operation of the operational amplifier 40 is brought into an operation state when the control signal X is first raised to “H level”. At this time, the control signal X is a clock pulse that maintains the “H level” longer than the period of the delay time τ ₂ of the delay circuit 32. When the control signal X becomes “H level”, the output γ of the OR element 20 becomes “H level”, the switch TR3 of the comparator 10 is turned on, and the comparator 10 operates. At this time, since the output γ is delayed by the delay circuit 22 and input to the AND element 24, the output of the AND element 24 is maintained at “L level” only during the delay time τ ₃ . Therefore, the switches TR1 and TR2 are turned off during this period. This is to maintain the switches TR1 and TR2 in the OFF state until the output of the comparator 10 is input to the OR element 26 and the AND element 28 via the delay circuit 14.

First, a case where the voltage level of the input terminal IN ′ is extremely higher than the voltage level of the output terminal OUT will be described. In this case, the output terminal A of the comparator 10 becomes “H level”, and the inverted signal φ becomes “L level”. When the inverted signal φ is delayed by the delay circuit τ ₁ by the delay circuit 14 and the output of the AND element 24 subsequently becomes “H level”, the output of the OR element 26 becomes “L level”, and the output of the AND element 28 becomes “ "L level" is maintained. As a result, the switch TR1 is turned on and the switch TR2 is turned off. As a result, the output terminal OUT is connected to the power source Vc and the capacitance component C is charged, and the voltage level of the output terminal OUT increases.

Further, the output of the fluctuation detection circuit 30 becomes “H level” only during the delay time τ ₂ after the control signal X is raised to “H level”. Therefore, the output β of the latch circuit 12 becomes “L level” only during the delay time τ ₂ after the control signal X is raised to “H level”, and thereafter is maintained at “H level”. Therefore, even if the control signal X becomes “L level”, the output γ of the OR element 20 remains “H level” and the operational state of the operational amplifier 40 is maintained.

  When the capacitance component C of the output terminal OUT connected to the power supply Vc is charged, the voltage level of the output terminal OUT approaches the voltage level of the input terminal IN ′, and the voltage level of the output terminal OUT becomes the voltage level of the input terminal IN ′. Over. Then, the output terminal A of the comparator 10 changes from “H level” to “L level”, and the inverted signal φ changes from “L level” to “H level”.

At this time, the output of the fluctuation detection circuit 30 becomes “H level” only during the delay time τ ₂ after the inversion signal φ changes. Accordingly, the output β of the latch circuit 12 becomes “L level” only during the delay time τ ₂ after the inversion signal φ changes.

  At this time, if the control signal X is “L level”, the output γ of the OR element 20 is “L level”. Accordingly, the switch TR4 is turned off, and the output β of the latch circuit 12 is maintained at “L level” even after the output of the fluctuation detection circuit 30 is restored to “L level”. Further, the switch TR3 of the comparator 10 is turned off, the operation of the comparator 10 is stopped, and the output of the AND element 24 immediately becomes “L level”. Therefore, the output of the OR element 26 becomes “H level”, and the AND element 28 The output of is maintained at “L level”. Thereby, the operation of the comparator 10 is stopped and the switches TR1 and TR2 are turned off.

The delay circuit 14 has a capacitance component C of the output terminal OUT for the delay time τ ₁ so that the fluctuation detection circuit 30 reliably detects the change of the inverted output φ when the input terminal IN ′ and the output terminal OUT are at the same voltage level. The charging / discharging is maintained. However, as soon as the fluctuation detection circuit 30 detects a change in the inverted output φ, the comparator 10 is stopped and the switches TR1 and TR2 are turned off. As a result, the output terminal OUT is disconnected from the power supply Vc and the ground GND, and the operational amplifier 40 becomes inoperative.

  Next, a case where the voltage level of the input terminal IN ′ is slightly higher than the voltage level of the output terminal OUT will be described. In this case, the same operation is performed as when the voltage level of the input terminal IN ′ is extremely higher than the voltage level of the output terminal OUT, but the voltage level of the output terminal OUT immediately approaches the voltage level of the input terminal IN ′. The voltage level of the output terminal OUT exceeds the voltage level of the input terminal IN ′. Therefore, when the control signal X becomes “L level”, the output β of the latch circuit 12 is already “L level”. Thereby, when the control signal X becomes “L level”, the operation of the comparator 10 is stopped, the switches TR1 and TR2 are turned off, and the operational amplifier 40 is inactivated.

Next, a case where the voltage level of the input terminal IN ′ is extremely smaller than the voltage level of the output terminal OUT will be described. In this case, the output terminal A of the comparator 10 becomes “L level”, and the inverted signal φ becomes “H level”. When the delay circuit 14 delays the delay time τ ₁ and then the output of the AND element 24 becomes “H level”, the output of the OR element 26 maintains “H level” and the output of the AND element 28 becomes “H level”. " As a result, the switch TR1 is turned off and the switch TR2 is turned on. As a result, the output terminal OUT is connected to the ground GND, the capacitive component C is discharged, and the voltage level of the output terminal OUT decreases.

Further, the output of the fluctuation detection circuit 30 becomes “H level” only during the delay time τ ₂ after the control signal X is raised to “H level”. Therefore, the output β of the latch circuit 12 becomes “L level” only during the delay time τ ₂ after the control signal X is raised to “H level”, and thereafter is maintained at “H level”. Therefore, even if the control signal X becomes “L level”, the output γ of the OR element 20 remains “H level” and the operational state of the operational amplifier 40 is maintained.

  When the capacitance component C of the output terminal OUT connected to the ground GND is discharged, the voltage level of the output terminal OUT approaches the voltage level of the input terminal IN ′, and the voltage level of the output terminal OUT becomes the voltage level of the input terminal IN ′. Below. Then, the output terminal A of the comparator 10 changes from “L level” to “H level”, and the inverted signal φ changes from “H level” to “L level”.

At this time, the output of the fluctuation detection circuit 30 becomes “H level” only during the delay time τ ₂ after the inversion signal φ changes. Accordingly, the output β of the latch circuit 12 becomes “L level” only during the delay time τ ₂ after the inversion signal φ changes.

  At this time, if the control signal X is “L level”, the output γ of the OR element 20 is “L level”. Accordingly, the switch TR4 is turned off, and the output β of the latch circuit 12 is maintained at “L level” even after the output of the fluctuation detection circuit 30 is restored to “L level”. Further, the switch TR3 of the comparator 10 is turned off, the operation of the comparator 10 is stopped, and the output of the AND element 24 immediately becomes "L level". Therefore, the output of the OR element 26 maintains "H level", and AND The output of the element 28 becomes “L level”. Thereby, the operation of the comparator 10 is stopped and the switches TR1 and TR2 are turned off.

  As a result, the output terminal OUT is disconnected from the power supply Vc and the ground GND, and the operational amplifier 40 becomes inoperative.

  Next, a case where the voltage level of the input terminal IN ′ is slightly lower than the voltage level of the output terminal OUT will be described. In this case, the same operation as when the voltage level of the input terminal IN ′ is extremely smaller than the voltage level of the output terminal OUT is performed, but the voltage level of the output terminal OUT immediately approaches the voltage level of the input terminal IN ′. The voltage level of the output terminal OUT is lower than the voltage level of the input terminal IN ′. Therefore, when the control signal X becomes “L level”, the output β of the latch circuit 12 is already “L level”. Thereby, when the control signal X becomes “L level”, the operation of the comparator 10 is stopped, the switches TR1 and TR2 are turned off, and the operational amplifier 40 is inactivated.

  As described above, when the voltage level of the output terminal OUT becomes equal to the voltage level of the input terminal IN ′, the operational amplifier 40 is automatically deactivated.

  Although the operational amplifier 40 includes the delay circuit 14, the delay circuit 14 may be configured by a parasitic capacitance. Further, the delay circuit 14 and the delay circuit 32 may be realized by one delay circuit. The operational amplifier 40 is not limited to the above-described form, and includes a comparator that changes the output level by comparing the voltage levels of the input terminal IN ′ and the output terminal OUT. Accordingly, the output terminal OUT is connected to the power source or the ground, and various changes can be made within the range characterized in that the operational amplifier is inactivated based on the output level from the comparator.

  If such an operational amplifier 40 is used for the operational amplifier OP in the first embodiment of the present invention shown in FIG. 2, the operation speed is controlled and the power consumption is adjusted in accordance with the performance required for the drive circuit of the display device. Further reduction can be achieved.

It is a block diagram which shows the whole structure of the drive circuit of the display apparatus in the 1st Embodiment of this invention. 1 is a circuit diagram showing a configuration of a drive circuit in a first embodiment of the present invention. 3 is a timing chart illustrating the operation of the drive circuit according to the first embodiment of the present invention. 6 is a timing chart showing another operation of the drive circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the structure of an operational amplifier suitable for use in the second embodiment of the present invention. 6 is a timing chart showing the operation of the drive circuit according to the second embodiment of the present invention. It is a block diagram which shows the whole structure of the drive circuit of the conventional display apparatus. It is a circuit diagram which shows the structure of the conventional drive circuit.

Explanation of symbols

10 comparators, 12 latch circuits, 14 delay circuits, 20 OR elements, 22 delay circuits, 24 AND elements, 26 OR elements, 28 AND elements, 30 fluctuation detection circuits, 32 delay circuits, 34 XOR elements, 40 operational amplifiers, 50, 60 Reference voltage supply circuit, 52, 62 Reference voltage selection circuit, 54, 64 Image signal input unit, 100, 150 Drive circuit, 200 Display device.

Claims (4)

An input terminal to which a reference voltage selected according to an image signal is applied;
A reference voltage holding circuit that holds and outputs the reference voltage;
An amplifier capable of controlling operation with a gain of approximately 1 connected to an output terminal to which an output point of a reference voltage held by the reference voltage holding circuit is connected and an output is connected to a pixel of a display device;
A first switch connected between the input terminal and the reference voltage holding circuit;
A second switch connected between the input terminal and the output terminal;
A drive circuit for a display device, comprising: In the display device drive circuit according to claim 1,
The amplifier includes a comparator that compares the voltage level of the output point of the reference voltage held by the reference voltage holding circuit and the output terminal to change the output level, and outputs the output level from the comparator. In response, connect the output terminal to a power source or ground,
A drive circuit for a display device, wherein the amplifier is inactivated based on an output level from the comparator. In the drive circuit of the display device according to any one of claims 1 to 2,
The reference voltage holding circuit holds the reference voltage by turning on the first switch while turning off the second switch for a predetermined period,
A driving method of a display device, wherein after the predetermined period has elapsed, the first switch is turned off to start the operation of the amplifier. In the drive circuit of the display device according to any one of claims 1 to 2,
The reference voltage holding circuit holds the reference voltage by turning on the first switch while turning off the second switch for a predetermined period,
A method for driving a display device, comprising: turning off the first switch, turning on the second switch, and starting the operation of the amplifier after the predetermined period has elapsed.

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