JP2005136038A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A non-volatile semiconductor memory device and a method for manufacturing the same are provided that can improve the withstand voltage of a high withstand voltage transistor and reduce the cost.
On a first conductivity type semiconductor substrate, a first gate electrode 3a / 4a / 5a / 6a on a first gate insulating film 2a, a first diffusion layer 7a, and a first diffusion layer 7a thereon. An information storage element including one diffusion layer insulating film 8a, a second gate electrode 3b / 4b / 5b / 6b on the second gate insulating film 2b, a second diffusion layer 7b, and a second diffusion layer 7b thereon. Information processing element including two diffusion layer insulating films 8b, and a third gate electrode 3c / 4c / on a third gate insulating film 2c thicker than the first gate insulating film 2a and the second gate insulating film 2b. 5c / 6c, a third diffusion layer 7c, and a signal potential generating element including a third diffusion layer insulating film 8c thereon, the third diffusion layer insulating film 8c being the third gate insulating film 2c. It is thinner and has substantially the same thickness as the first diffusion layer insulating film 8a and / or the second diffusion layer insulating film 8b.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In recent years, with the development of mobile devices and Internet home appliances, silicon memory cards that are portable and do not lose information even when the power is turned off are rapidly spreading. Unlike a conventional magnetic medium, the nonvolatile semiconductor memory used in such a silicon memory card can electrically rewrite data, and can have a large capacity and a low cost.

  Among them, the flash memory can collectively reset information in units of chunks (usually called sectors or blocks) of about several Kbytes. As an array configuration of such a flash memory, there are a NOR type and a NAND type, and a NAND type is used for storing large-capacity data like a normal memory card (see, for example, Patent Document 1).

  FIG. 14 is a plan view of a cell array portion of such a NAND flash memory, and FIG. 15 is a cross-sectional view taken along the line A-A ′ of FIG. A plurality of element regions 101 are formed on a p-type semiconductor substrate and separated by an element isolation region 102. In the element region 101, a plurality of memory cells and select transistors arranged at both ends thereof are connected in series while sharing an n-type diffusion layer 103 serving as a source and a drain to form a NAND string. The memory cell is separated into each NAND string by separating the charge storage layer 104 on the element isolation region 102. These have a stacked gate structure including a charge storage layer 104, an intergate insulating film 106, a control gate 107, and a gate cap film 108 on a gate insulating film 105. The charge storage layer 104 or the charge storage layer 104 of the selection transistor and the control gate 107 are connected to a gate signal line (not shown), and the n-type diffusion layer 103 serving as the drain or source covers each stacked gate. The other is connected to the bit line 111 through the bit line contact 110 formed in the interlayer insulating film 109, and the other is connected to the common source line 113 through the common source line contact 112.

  In the flash memory having such a structure, data is rewritten by transferring charges between the gate electrode and the ultra-thin gate insulating film between the semiconductor using a tunnel phenomenon or a hot electron phenomenon. For example, when electrons are excessively injected into the charge storage layer, the threshold voltage of the MOSFET under the control gate becomes a positive value higher than that in the neutral state where no electrons are injected, and When excessive electrons are emitted (or excessive holes are injected into the charge storage layer), the threshold voltage becomes a negative value lower than that in the neutral state.

  If a state where electrons are injected into the charge storage layer is defined as a “0” state, and a state where electrons are emitted is defined as a “1” state, a threshold voltage (positive) in the “0” state and “1” are defined. If the intermediate potential (eg, 0V) of the threshold voltage (negative) in the state is applied to the control gate, the intermediate potential (Vcc: eg 3V) is applied to the bit line, and 0V is applied to the common source line, the cell If the threshold voltage of the cell is '0' higher than 0V, the cell current does not flow between the bit line and the source line. If the threshold voltage is lower than 0V, the cell current flows. The “0” and “1” states can be discriminated.

  The flash memory stores information by recognizing such “0” and “1” states as 1-bit information. An operation for changing the memory cell to the ‘1’ state is written, an operation for changing the state to the ‘0’ state is erased, and an operation for discriminating between the ‘0’ state and the ‘1’ state is referred to as reading.

  When charge is transferred using a tunnel phenomenon, information writing is performed as follows. Even when the hot electron phenomenon is used, it is basically the same. That is, a selection signal is input to the control gate, an information signal is input to the bit line, and a cell to which the signal is input is selected. In general, when a high voltage (Vpp) of 10 V or more is applied as a selection signal and a reference potential (Vss: 0 V, for example) is input as an information signal, a high electric field is generated between the charge storage layer and the semiconductor substrate. Inverted electrons formed on the surface of the semiconductor substrate are injected into the charge storage layer. This is because an FN tunneling phenomenon occurs when a high electric field is applied between the ultrathin gate insulating films, and inverted electrons are injected from the semiconductor substrate into the charge storage layer. On the other hand, when a power supply potential (for example, 3 V) is input as an information signal, the electric field between the charge storage layer and the semiconductor substrate is weakened, the FN tunneling phenomenon does not occur, and no charge is injected. That is, it is possible to select a cell for injecting a charge and a cell for non-injection from among a group of memory cells connected to the same control gate.

  On the contrary, in the information erasing, the potential relationship applied to the control gate and the semiconductor substrate may be reversed from that in the information writing. That is, a reference potential (Vss) is applied to the control gate, a high voltage (Vpp) is applied to the semiconductor substrate, and the direction of the electric field applied to the gate insulating film between the charge storage layer and the semiconductor substrate is opposite to the writing state. By doing so, electrons stored in the charge storage layer are emitted to the semiconductor substrate by FN tunneling through the gate insulating film.

  The intermediate potential (Vcc) and the high voltage (Vpp) for driving such a memory cell are controlled and applied by peripheral transistors arranged outside the memory cell array. A low voltage driving transistor (hereinafter referred to as a Vcc transistor) to which an intermediate potential (Vcc) is applied includes a gate insulating film having a thickness equal to or less than that of a memory cell, and the electric field applied to the diffusion layer is a memory. Lower than cell. On the other hand, a high voltage driving (high withstand voltage) transistor (hereinafter referred to as a Vpp transistor) that applies a high voltage (Vpp) has a Vpp structure including a gate insulating film much thicker than a memory cell.

  FIG. 16 shows a cross-sectional structure diagram of a general memory cell, a Vcc transistor, and a Vpp transistor. In the memory cell, a stacked gate including a stacked and patterned charge storage layer 203a, insulating layer 204a, control gate 205a, and gate cap film 206a is formed on a gate insulating film 202a formed on a p-type semiconductor substrate 201a. The n-type diffusion layer 207a is formed so as to sandwich the region below the stacked gate. These are covered with an interlayer insulating film 209a.

  Similar to the memory cell, the Vcc transistor includes a charge storage layer 203b, an insulating layer 204b, a control gate 205b, and a gate cap film 206b stacked and patterned on the gate insulating film 202b formed on the p-type semiconductor substrate 201b. A stacked gate is formed, and an n-type diffusion layer 207b is formed so as to sandwich a region below the stacked gate. These are covered with an interlayer insulating film 209b, and a contact hole 210b is formed on the diffusion layer.

  In the Vpp transistor, a stacked gate composed of a stacked and patterned charge storage layer 203c, insulating layer 204c, control gate 205c, and gate cap film 206c is formed on a thick gate insulating film 202c formed on a p-type semiconductor substrate 201c. In addition, an n-type diffusion layer 207c serving as a source and drain region is formed so as to sandwich the region below the stacked gate. These are covered with an interlayer insulating film 209c, and a contact hole 210c is formed on the diffusion layer.

In such a Vpp transistor, the impurity concentration of the diffusion layer is set to be nearly one digit lower than that of the memory cell or the Vcc transistor. This is because the junction breakdown voltage of the PN junction decreases as the impurity concentration in the P region and N region increases. Further, the insulating film thickness on the diffusion layer is about several tens of nm thicker than the memory cell and the Vcc transistor. Therefore, in order to form the low concentration diffusion layer as described above, it is necessary to implant impurities by ion implantation using a high acceleration voltage that passes through such a thick diffusion layer insulating film.
JP 2002-57230 A

  Thus, the diffusion layer forming conditions of the Vpp transistor are greatly different from those of the memory cell and the Vcc transistor, and it is difficult to form the diffusion layer at the same time. That is, even if impurities are implanted under conditions for forming a diffusion layer of a memory cell or a Vcc transistor without masking the entire surface, the thick diffusion layer insulating film cannot be passed. On the other hand, when the diffusion layer of the memory cell or the Vcc transistor is formed under the condition for forming the diffusion layer of the Vpp transistor, the effective gate length is shortened because impurities are implanted at the gate end of the memory cell at a high acceleration, so-called short channel effect. Causes threshold voltage drop and off-characteristic deterioration. Therefore, there is a problem that it is difficult to reduce the cost by making the diffusion layer forming process common.

  Further, since high-acceleration voltage ion implantation causes lateral impurity scattering, the effective gate length is shortened, resulting in deterioration of punch-through breakdown voltage and drain breakdown voltage of the Vpp transistor.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can eliminate the conventional problems, improve the breakdown voltage of the Vpp transistor, and reduce the cost. .

  According to one aspect of the present invention, a first conductivity type semiconductor substrate, a first gate electrode formed in a predetermined region on the semiconductor substrate via a first gate insulating film, and the semiconductor substrate A second diffusion type first diffusion layer formed so as to sandwich a region under the first gate insulating film, and a first diffusion layer insulating film formed on the first diffusion layer An information storage element, a second gate electrode formed via a second gate insulating film in a predetermined region on the semiconductor substrate, and a region under the second gate insulating film sandwiched between the semiconductor substrate A second diffusion layer of the second conductivity type formed as described above, an information processing element comprising a second diffusion layer insulating film formed on the second diffusion layer, and a predetermined region on the semiconductor substrate. And a third gate insulating film thicker than the first gate insulating film and the second gate insulating film. A third diffusion electrode of the second conductivity type formed on the semiconductor substrate so as to sandwich a region under the third gate insulating film, and on the third diffusion layer A signal potential generating element including a third diffusion layer insulating film formed on the first diffusion layer insulating film, wherein the third diffusion layer insulating film is thinner than the third gate insulating film, and the first diffusion layer insulating film and A nonvolatile semiconductor memory device is provided that has substantially the same thickness as the second diffusion layer insulating film.

  According to one aspect of the present invention, a first insulating film is formed in an information storage element forming region on a first conductivity type semiconductor substrate, a second insulating film is formed in an information arithmetic element forming region, and a signal potential generating element forming region. Forming a third insulating film thicker than the first insulating film and the second insulating film, and laminating and patterning a gate electrode material on the entire surface, and forming a first gate on the first insulating film. Forming a second gate electrode on the second insulating film, a third gate electrode on the third insulating film, and implanting a first ion species without masking on the entire surface, Forming a first diffusion layer in the information storage element formation region and a second diffusion layer in the information calculation element formation region, removing at least the exposed third insulation film, and removing the third insulation film The first diffusion layer insulating film and the second expansion layer are thinner and formed on the first diffusion layer. Forming a third diffusion layer insulating film having substantially the same thickness as the second diffusion layer insulating film formed on the layer, and implanting a second ion species without masking on the entire surface, Forming a first diffusion layer in the memory element formation region, a second diffusion layer in the information calculation element formation region, and a third diffusion layer in the signal potential generation element formation region. A method for manufacturing a nonvolatile semiconductor memory device is provided.

  According to one embodiment of the present invention, it is possible to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can improve the breakdown voltage of a high breakdown voltage transistor and can reduce the cost.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view in the gate vertical direction of the NAND flash memory according to this embodiment. Here, the memory cell is shown in FIG. 5A, the Vcc transistor in the peripheral transistor is shown in FIG. 5B, the Vpp transistor is shown in FIG.

  In the memory cell shown in FIG. 1A, a gate electrode 3a / 4a / 5a / 6a having a laminated structure is formed on a p-well 1a formed on a p-type silicon substrate via a gate insulating film 2a. The gate insulating film 2a is formed with a film thickness of 10 nm or less (for example, 10 nm) through which the FN tunnel current flows, over the entire surface of the substrate surface where the channel is formed. In the gate electrode, a charge storage layer 3a made of polycrystalline silicon, an inter-gate insulating film 4a, a control gate 5a, a gate cap film 6a made of a silicon nitride film, etc. are sequentially laminated in a self-aligning manner so that the side edges are aligned. It is processed vertically.

  A diffusion layer 7a into which an n-type impurity such as arsenic having a polarity opposite to that of the p-type impurity such as boron in the channel region is interposed is formed across the region below the gate electrode of the p-well 1a, and is formed on the surface of the diffusion layer 7a. The diffusion layer insulating film 8a is formed. The diffusion layer insulating film 8a has a thickness (for example, 5 nm) that is slightly thinner than the gate insulating film 4a.

  In the Vcc transistor shown in FIG. 1B, a gate electrode 3b / 4b / 5b / 6b having a laminated structure is formed on a p-well 1b formed on a p-type silicon substrate via a gate insulating film 2b. The gate insulating film 2b is formed with a film thickness of 10 nm or less (for example, 10 nm) that can be driven at a low voltage over the entire surface of the substrate surface where the channel is formed. The gate electrode has a stacked gate structure similar to that of the memory cell. The charge storage layer 3b, the intergate insulating film 4b, the control gate 5b, and the gate cap film 6b are sequentially stacked. The charge storage layer 3b and the control gate 5b are stacked. Are connected (not shown), and the potential of the charge storage layer 3b can be controlled.

  Similar to the memory cell, a diffusion layer 7b into which an n-type impurity such as arsenic having a polarity opposite to that of the p-type impurity such as boron in the channel region is implanted is formed across the region below the gate electrode of the p-well 1b. A diffusion layer insulating film 8b is formed on the surface of the layer 7b. The diffusion layer insulating film 8b has a thickness (for example, 5 nm) that is slightly thinner than the gate insulating film 4b.

  In the Vpp transistor shown in FIG. 1C, a stacked structure of gate electrodes 3c / 4c / 5c / 6c is formed on a p-well 1c formed on a p-type silicon substrate via a gate insulating film 2c. The gate insulating film 2c is formed on the entire surface of the substrate surface where the channel is formed with a film thickness of several tens of nm or less (for example, 40 nm) that can be driven at a high voltage. The gate electrode has a stacked gate structure similar to that of the memory cell, and a charge storage layer 3c, an intergate insulating film 4c, a control gate 5c, and a gate cap film 6c are sequentially stacked.

  Similar to the memory cell, diffusion layers 7c and 7c 'into which an n-type impurity having a polarity opposite to that of the p-type impurity such as boron in the channel region is implanted, sandwiching the region under the gate electrode of the p well 1a. Since the Vpp transistor requires a high breakdown voltage at the gate and drain, the diffusion layer 7c is set at a lower concentration than the memory cell and the Vcc transistor, but the diffusion layer 7c ′ formed in the contact connection region has a contact Because of ohmic contact, the concentration is high. The surface of the diffusion layer diffusion layers 7c and 7c ′ is very thin compared to the gate insulating film 2c, and is substantially the same film thickness (thickness of the film) as the diffusion layer insulating films 8a and 8b of the memory cell and Vcc transistor. A diffusion layer insulating film 8c having a thickness of 10 nm or less (for example, 5 nm) is formed, which is a difference in variation (approximately 10% is allowed).

On these elements, thick interlayer insulating films 9a, 9b, 9c such as BPSG and SiO ₂ are covered, and contacts 10b, 10c, etc. connected to the diffusion layers are formed.

  Such a NAND flash memory is formed as follows. That is, first, as shown in FIGS. 2A, 2B, and 2C, a memory cell having a normal stacked gate structure is formed on a p-type silicon substrate on which high-concentration p-wells 1a, 1b, and 1c are formed. In the same manner as the gate forming process of the flash memory, the insulating films 2a ′, 2b ′, 2c ′ that become the gate insulating films 2a, 2b, and 2c and the gate electrode material are sequentially stacked on each element forming region. At this time, the insulating film 2c 'formed in the Vpp formation region has a thickness of several tens of nm (for example, 40 nm), and is thicker than the insulating film formed in the memory cell and Vcc formation region. Next, the gate electrode material is vertically processed to form each gate electrode (3a / 4a / 5a / 6a, 3b / 4b / 5b / 6b, 3c / 4c / 5c / 6c) of the memory cell, Vcc transistor, and Vpp transistor. To do. At this time, each insulating film 2a ', 2b', 2c 'is not processed and covers each element formation region.

In this state, as shown in FIGS. 3A, 3B, and 3C, in order to form the diffusion layer 7a of the memory cell, arsenic is deposited on the entire surface of the silicon substrate without a mask, for example on the order of 10 ¹³ cm ^2. Ion implantation. Here, arsenic is ion-implanted into the Vcc transistor formation region (7b '), but in the Vpp transistor formation region, conditions such as an acceleration voltage are set so that a thick insulating film serves as a mask. Ion implantation is not performed.

  Next, as shown in FIGS. 4A, 4B, and 4C, the exposed insulating film (in the region where the gate electrode is not formed) is removed by dry etching. At this time, only the insulating film on the Vpp formation region may be removed or the entire surface may be removed. Then, clean insulating films (diffusion layer insulating films 8a, 8b, 8c) having a film thickness of 10 nm or less (for example, 5 nm) are re-formed in the region from which the insulating film has been removed by thermal oxidation or the like.

Then, as shown in FIGS. 5A, 5B, and 5C, phosphorus is ion-implanted into the Vpp transistor formation region, for example, on the order of 10 ¹² cm ² using a mask to form the diffusion layer 7c. . Further, using a mask, arsenic is ion-implanted into predetermined regions of the Vcc transistor formation region and the Vpp transistor formation region, for example, on the order of 10 ¹⁴ cm ² to form diffusion layers 7b and 7c ′.

  Further, as shown in FIGS. 6A, 6B, and 6C, element insulating materials or interlayer insulating films 9a, 9b, and 9c are formed on the entire surface. Then, contacts 10b and 10c are formed on the diffusion layer 7b of the Vcc transistor and the diffusion layer 7c 'of the Vpp transistor.

  In the NAND flash memory formed in this way, the diffusion layer can be formed at a low acceleration voltage by thinning the diffusion layer insulating film of the Vpp transistor. It is possible to suppress a decrease in length.

  In addition, since the ion implantation can be performed on the entire surface when forming the diffusion layer of the memory cell, the mask process can be omitted, the cost can be greatly reduced, and the yield is reduced due to dust generated in the mask process. Can be suppressed. However, a mask process may be added for other reasons.

  Furthermore, the high concentration diffusion layer in the diffusion layer of the Vpp transistor can be formed at the same time by adopting the same structure as the diffusion layer of the Vcc transistor.

In this embodiment, the gate electrode is directly covered with the interlayer insulating film, but the side wall may be formed of a deposited film such as SiO ₂ , SiN, or TEOS.

(Embodiment 2)
FIG. 7 shows a cross-sectional view in the gate vertical direction of the NAND flash memory according to this embodiment.

  In the memory cell shown in FIG. 7A, similarly to the first embodiment, a gate electrode 13a / 14a / 15a / having a stacked structure is formed on a p-well 11a formed on a p-type silicon substrate via a gate insulating film 12a. 16a is formed. The gate insulating film 12a is formed with a film thickness of 10 nm or less (for example, 10 nm) through which the FN tunnel current flows, over the entire surface of the substrate surface where the channel is formed. In the gate electrode, a charge storage layer 13a made of polycrystalline silicon, an inter-gate insulating film 14a, a control gate 15a, a gate cap film 16a made of a silicon nitride film, etc. are sequentially laminated in a self-aligning manner so that the side ends are aligned. It is processed vertically. Further, a gate side wall 21a is formed so as to cover the side end portion.

  A diffusion layer 17a into which n-type impurity having a polarity opposite to that of the p-type impurity (for example, boron) in the channel region is injected across the region below the gate electrode of the p-well 11a, and an atomic mass from the diffusion layer 17a. A diffusion layer 17a ′ into which phosphorus, which is a small n-type impurity, is implanted is formed, and a diffusion layer insulating film 18a is formed on the surfaces of the diffusion layers 17a and 17a ′. The diffusion layer insulating film 18a has a thickness (for example, 5 nm) that is slightly thinner than the gate insulating film 14a.

  In the Vcc transistor shown in FIG. 7B, similarly to the first embodiment, a gate electrode 13b / 14b / 15b / having a stacked structure is formed on a p-well 11b formed on a p-type silicon substrate via a gate insulating film 12b. 16b is formed. The gate insulating film 12b is formed to a thickness of 10 nm or less (for example, 10 nm) that can be driven at a low voltage over the entire surface of the substrate surface where the channel is formed. The gate electrode has a stacked gate structure similar to that of the memory cell. The charge storage layer 13b, the intergate insulating film 14b, the control gate 15b, and the gate cap film 16b are sequentially stacked. The charge storage layer 13b and the control gate 15b are stacked. Are connected (not shown), and the potential of the charge storage layer 13b can be controlled. Further, a gate side wall 21b is formed so as to cover the side end portion.

  Similar to the memory cell, a diffusion layer 17b in which an n-type impurity having a polarity opposite to that of the p-type impurity (for example, boron) in the channel region is implanted and is in contact with the gate electrode lower region across the region below the gate electrode of the p well 11b. A high concentration diffusion layer 17b ′ is formed, and a diffusion layer insulating film 18b is formed on the surfaces of the diffusion layers 17b and 17b ′. The diffusion layer insulating film 18b has a thickness (for example, 5 nm) that is slightly thinner than the gate insulating film 14b.

  In the Vpp transistor shown in FIG. 7C, as in the first embodiment, a gate electrode 13c / 14c / 15c / having a stacked structure is formed on a p-well 11c formed on a p-type silicon substrate via a gate insulating film 12c. 16c is formed. The gate insulating film 12c is formed to a thickness of several tens of nm or less (for example, 40 nm) capable of high voltage driving over the entire surface of the substrate surface where the channel is formed. The gate electrode has a stacked gate structure similar to that of the memory cell, and a charge storage layer 13c, an intergate insulating film 14c, a control gate 15c, and a gate cap film 16c are sequentially stacked. Furthermore, a gate side wall 21c is formed so as to cover the side end portion.

  Similarly to the memory cell, a n-type impurity having a polarity opposite to that of the p-type impurity (for example, boron) in the channel region is implanted across the region below the gate electrode of the p-well 11c, and the diffusion layer 17c is in contact with the region under the gate electrode. A high concentration diffusion layer 17c 'is formed. Since the Vpp transistor requires a high breakdown voltage at the gate and drain, the impurity concentration of the diffusion layer is also set lower than that of the memory cell or Vcc transistor. The surfaces of the diffusion layer diffusion layers 17c and 17c ′ are very thin as compared with the gate insulating film 12c, and are substantially the same thickness (thickness of the film) as the diffusion layer insulating films 8a and 8b of the memory cell and the Vcc transistor. A diffusion layer insulating film 8c having a thickness of 10 nm or less (for example, 5 nm) is formed, which is a difference in variation (approximately 10% is allowed).

On these elements, contacts 20b, 20c, etc., which are covered with thick interlayer insulating films 19a, 19b, 19c such as BPSG and SiO ₂ and connected to the diffusion layers are formed.

  Such a NAND flash memory is formed as follows. That is, as in the first embodiment, first, as shown in FIGS. 8A, 8B, and 8C, a p-type silicon substrate on which high-concentration p-wells 11a, 11b, and 11c are formed is usually formed. In the same manner as the gate forming step of the flash memory including the memory cells having the stacked gate structure, the insulating films 12a ′, 12b ′, 12c ′ to be the gate insulating films 12a, 12b, 12c, and the gate electrode material are formed on each element forming region. Are sequentially stacked. At this time, the insulating film 12c 'formed in the Vpp formation region is several tens of nm thick, and is thicker (for example, 40 nm) than the insulating film formed in the memory cell and Vcc formation region. Next, the gate electrode material is vertically processed to form each gate electrode (13a / 14a / 15a / 16a, 13b / 14b / 15b / 16b, 13c / 14c / 15c / 16c) of the memory cell, Vcc transistor, and Vpp transistor. To do. At this time, the insulating film is not processed and covers each element formation region.

In this state, as shown in FIGS. 9A, 9B, and 9C, in order to form the diffusion layer 17a of the memory cell, arsenic is deposited on the entire surface of the silicon substrate without a mask, for example on the order of 10 ¹³ cm ^2. Ion implantation. Here, arsenic is ion-implanted into the Vcc transistor formation region (7b ″), but conditions such as an acceleration voltage are set in the Vpp transistor formation region so that a thick insulating film serves as a mask. Do not do.

  Next, as shown in FIGS. 10A, 10B, and 10C, the exposed insulating film (in the region where the gate electrode is not formed) is removed by dry etching. At this time, only the insulating film on the Vpp formation region may be removed or the entire surface may be removed. Then, a clean insulating film having a thickness of 10 nm or less (for example, 5 nm) is re-formed in the region from which the insulating film has been removed by thermal oxidation or the like.

Then, as shown in FIGS. 11A, 11B, and 11C, phosphorus is ion-implanted over the entire surface of the silicon substrate in order to form the diffusion layer 17c of the Vpp transistor. At this time, in order to prevent other elements from being affected even if implantation without a mask is performed, phosphorus having a low atomic mass with a low dose (for example, on the order of 10 ¹² cm ² ) is used. The diffusion layers 17a ′ and 17b (formed so as to overlap 17b ″) are formed by accelerating at a lower acceleration voltage than the above.

Next, as shown in FIGS. 12A, 12B, and 12C, an insulating film made of SiO ₂ or SiN is deposited on the entire surface and etched back, whereby gate sidewalls 21a, 21b and 21c are formed in a self-aligning manner. Then, after masking the memory cell formation region, arsenic is ion-implanted into the Vcc transistor formation region on the order of 10 ¹⁴ cm ^2, for example, to form a diffusion layer 17b ′ using the gate side wall as a mask, and LDD (Lightly Doped) (Drain) structure. At this time, ions may be implanted into the Vpp transistor formation region at the same time to form a contact connection region 17c ′.

  Further, as shown in FIGS. 13A, 13B, and 13C, element insulating materials or interlayer insulating films 19a, 19b, and 19c are formed on the entire surface. Then, contacts 20b and 20c are formed on the diffusion layer 17b of the Vcc transistor and the diffusion layer 17c 'of the Vpp transistor.

  As described above, since the diffusion layer can be formed at a low acceleration voltage by thinning the diffusion layer insulating film of the Vpp transistor as in the first embodiment, the effective channel length due to the spread of the diffusion layer in the lateral direction can be reduced. It is possible to suppress the decrease.

  Similarly to the first embodiment, ion implantation can be performed on the entire surface when the diffusion layer of the memory cell is formed, and the impurity implanted into the diffusion layer of the Vpp transistor is more atomized than the diffusion layer impurity of the memory cell or Vcc transistor. Since the mass is small and the implantation dose is low, even when the diffusion layer of the Vpp transistor is formed, ion implantation can be performed on the entire surface without deteriorating the characteristics of the memory cell and the Vcc transistor. Therefore, the mask process can be further omitted, and the cost can be greatly reduced, and a decrease in yield due to dust generated in the mask process can be suppressed. However, a mask process may be added for other reasons.

  In these embodiments, arsenic is implanted when the diffusion layer of the memory cell is formed, when the contact region of the diffusion layer of the Vpp transistor is formed, etc., but is not limited to arsenic, and when the diffusion layer of the Vpp transistor is formed. Any n-type impurity having a combination in which the atomic mass is larger than that of the implanted impurity may be used, and antimony or the like can be used.

  Further, it is possible to appropriately select and use the operating principle and array configuration of the nonvolatile semiconductor memory device, the type of transistor, the type of gate insulating film, and the like.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

The figure which shows the structure of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the structure of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The figure which shows the manufacturing process of the non-volatile semiconductor memory device by one embodiment of this invention. The top view of the cell array part of NAND type flash memory. Sectional drawing of the cell array part of NAND type flash memory. The figure which shows the structure of the conventional NAND type flash memory.

Explanation of symbols

1, 11 p-well
2, 12 Gate insulating film 3, 13 Charge storage layer 4, 14 Inter-gate insulating film 5, 15 Control gate 6, 16 Gate cap film 7, 17 Diffusion layer 8, 18 Diffusion layer insulating film 9, 19 Interlayer insulating film 10, 20 contacts 21 gate sidewalls 101 element regions 102 element isolation regions 103 n-type diffusion layers 104 charge storage layers 105 gate insulating films 106 inter-gate insulating films 107 control gates 108 gate cap films 109 interlayer insulating films 110 bit line contacts 111 bit lines 112 commons Source line contact 113 Common source line 201 Semiconductor substrate
202 Insulating film 203 Charge storage layer 204 Intergate insulating film 205 Control gate 206 Gate cap film 207 Diffusion layer 209 Interlayer insulating film 210 Contact

Claims (15)

A first conductivity type semiconductor substrate;
A first gate electrode formed through a first gate insulating film in a predetermined region on the semiconductor substrate, and a region under the first gate insulating film sandwiched between the semiconductor substrate An information storage element comprising a first diffusion layer of a second conductivity type, and a first diffusion layer insulating film formed on the first diffusion layer,
A second gate electrode formed through a second gate insulating film in a predetermined region on the semiconductor substrate, and a region under the second gate insulating film sandwiched between the semiconductor substrate. An information processing element comprising a second diffusion layer of a second conductivity type, and a second diffusion layer insulating film formed on the second diffusion layer;
A third gate electrode formed in a predetermined region on the semiconductor substrate via a third gate insulating film thicker than the first gate insulating film and the second gate insulating film; and A signal comprising a third diffusion layer of a second conductivity type formed so as to sandwich a region under the third gate insulating film, and a third diffusion layer insulating film formed on the third diffusion layer A potential generating element;
The third diffusion layer insulating film is thinner than the third gate insulating film and has substantially the same thickness as the first diffusion layer insulating film and / or the second diffusion layer insulating film. A non-volatile semiconductor memory device.   The information calculation element is a low voltage operation type FET element that drives a power supply potential, and the signal potential generation element is a high voltage operation type FET element that drives an input potential for information storage operation that is higher than a reference signal potential. 2. The nonvolatile semiconductor memory device according to claim 1, wherein   The first diffusion layer and the second diffusion layer include a first ion species, the third diffusion layer includes a second ion species, the second diffusion layer, and the third diffusion layer. The nonvolatile semiconductor memory device according to claim 1, wherein the contact connection region of the diffusion layer includes a third ion species.   The first diffusion layer and / or the second diffusion layer is an ionic species included in the third diffusion layer together with at least the first ionic species, and is different from the first ionic species. The nonvolatile semiconductor memory device according to claim 1, comprising an ionic species.   The nonvolatile semiconductor memory device according to claim 3, wherein the first ion species has an atomic mass larger than that of the second ion species.   The first ionic species concentration in the first diffusion layer and / or the second diffusion layer is higher than the second ionic species concentration in the third diffusion layer. 6. The nonvolatile semiconductor memory device according to any one of 5 above.   7. The high concentration region into which the third ion species is implanted is formed on the surface of the second diffusion layer without being adjacent to the region under the gate insulating film, respectively. The nonvolatile semiconductor memory device according to any one of the above.   8. The high concentration region into which the third ion species is implanted is formed on the surface of the third diffusion layer without being adjacent to the region under the gate insulating film, respectively. The nonvolatile semiconductor memory device according to any one of the above.   The nonvolatile semiconductor memory device according to claim 3, wherein the third ion species has an atomic mass larger than that of the second ion species. A first insulating film on the information storage element forming region on the first conductivity type semiconductor substrate, a second insulating film on the information arithmetic element forming region, the first insulating film on the signal potential generating element forming region, and the Forming a third insulating film thicker than the second insulating film;
A gate electrode material is laminated and patterned on the entire surface, a first gate electrode is formed on the first insulating film, a second gate electrode is formed on the second insulating film, and a third gate electrode is formed on the third insulating film. Forming a gate electrode;
Implanting a first ion species without masking on the entire surface, forming a first diffusion layer in the information storage element formation region, and forming a second diffusion layer in the information arithmetic element formation region;
At least the exposed third insulating film is removed and formed on the first diffusion layer insulating film and the second diffusion layer which are thinner than the third insulating film and formed on the first diffusion layer. Forming a third diffusion layer insulating film having substantially the same thickness as the second diffusion layer insulating film formed;
A second ion species is implanted into the entire surface without a mask, the first diffusion layer is formed in the information storage element formation region, the second diffusion layer is formed in the information calculation element formation region, and the signal potential generation element formation region is formed. A method for manufacturing a nonvolatile semiconductor memory device, comprising the step of forming a third diffusion layer.   The method of manufacturing a nonvolatile semiconductor memory device according to claim 10, wherein the first ion species has an atomic mass larger than that of the second ion species.   The nonvolatile semiconductor according to claim 10 or 11, wherein the first ionic species concentration in the first diffusion layer and / or the second diffusion layer is higher than the second ionic species concentration. A method for manufacturing a storage device. Forming an insulating film on the side walls of the first to third gate electrodes;
The non-volatile device according to claim 10, further comprising a step of implanting a third ion species into the information arithmetic element formation region and forming a high concentration region in the second diffusion layer. For manufacturing a conductive semiconductor memory device.   14. The method according to claim 10, further comprising a step of implanting a third ion species in the signal potential generating element forming region and forming a high concentration region in the third diffusion layer. A method for manufacturing a nonvolatile semiconductor memory device.   15. The method for manufacturing a nonvolatile semiconductor memory device according to claim 13, wherein the third ion species has an atomic mass larger than that of the second ion species.

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