JP2005136092A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate bipolar transistor device provided with a countermeasure against latch-up without increasing the total cell area and a manufacturing method thereof.
A first conductivity type high resistance layer, a first conductivity type buffer layer located under the first conductivity type high resistance layer, and a second conductivity type base formed on the first conductivity type high resistance layer. Layer 13, first conductivity type emitter region 15 formed on the upper surface of second conductivity type base layer 13, emitter electrode 16 connected to emitter region 15, and channel of second conductivity type base layer 13 A gate electrode 18 formed insulatively on the region 17, a guard ring portion 19 in which diffusion around the cell region is deepened, and a lower surface of the first conductivity type buffer layer 12, and the guard ring portion 19 is provided. The second conductivity type collector layers 20 and 21 having a lower impurity concentration than the other regions and the collector electrode 22 connected to the collector layers 20 and 21 are provided immediately below the other regions.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as an insulated gate bipolar transistor (IGBT) device having improved latch-up resistance and a manufacturing method thereof.

  A power device is known as a switching semiconductor element that controls a relatively large current. Power devices include power transistors, power MOSFETs, and IGBTs (Insulated Gate Bipolar Transistors). Among these, IGBTs are electric vehicles as devices that have the advantages of ease of voltage drive and low loss due to conductivity modulation effects. It is used for inverters.

FIG. 10 is a cross-sectional area of a conventional IGBT cell region described in Patent Document 1 and a guard ring portion serving as a high withstand voltage means disposed outside the cell region. In the conventional IGBT 100, a high resistance n ⁻ type semiconductor layer 102 is formed on a P ⁺ type semiconductor layer 101 (collector layer), and a P type semiconductor layer 103 (base layer) is formed to a depth of 1 to 6 microns. A P-type semiconductor layer 104 and a P-type semiconductor layer 105 (guard ring portion) are formed. An N ⁺ type semiconductor layer 106 (emitter layer) is also formed. A gate electrode 108 is formed on the gate oxide film 107 as a gate insulating film formed by oxidizing the surface of the N ⁻ type semiconductor layer 102. In addition, the interlayer insulating film 109 is formed, and the emitter electrode 110, the gate electrode lead line 111, and the emitter electrode lead line that are in ohmic contact with the P type semiconductor layer 103, the N ⁺ type semiconductor layer 106, and the P type semiconductor layer 104. 110a is formed. Further, a collector electrode 112 in which a metal film is deposited on the back surface of the P ⁺ type semiconductor layer 101 is formed.

  Conventional IGBTs have a problem of destruction due to latch-up due to their characteristics. As described above, in the IGBT having a guard ring portion for improving the breakdown voltage of the element, a large amount of holes are injected from the collector layer immediately below the guard ring portion, and a large amount of current is concentrated in the outermost cell. Cause destruction by latch-up.

According to Patent Document 1, the latch-up mechanism is as follows. That is, in the above configuration, a current path is formed between the collector electrode 112 and the emitter electrode 110 by forming a channel by applying a voltage to the gate electrode 108. For such normal operation, a surge voltage higher than the normal operating voltage may be applied between the collector electrode 112 and the emitter electrode 110. In such a case, a depletion layer spreads in the high resistance n ⁻ type semiconductor layer 102. Here, in the A region, a depletion layer extends in the adjacent base region 103 and the N ⁻ type semiconductor layer 102 located between the adjacent base regions 103 and overlaps with each other, thereby relaxing the electric field. The maximum electric field value EA is obtained at the pn junction at the bottom of the base region 103.

On the other hand, a P-type semiconductor layer 104 is formed outside the end portion of the base region 103, and the region (B region) from the end portion of the P-type semiconductor layer 104 to the end portion of the N ⁻ -type semiconductor layer 102 is the above. The electric field relaxation effect disappears, and the maximum electric field value EB is obtained at the outer peripheral portion of the P-type semiconductor layer 104 or the surface of the N ⁻ semiconductor layer 102 in the vicinity thereof. In order to reduce the EB value and improve the breakdown voltage of the B region close to the EA value, a guard ring portion 105 that is repeatedly arranged is provided to reduce the maximum electric field EB of the B region and improve the breakdown voltage of the element. Yes.

The electric field value EC in the guard ring region increases when a surge voltage is applied to the collector electrode 112, and the electron-hole pair due to collision ionization is outside the guard ring portion located at the outermost periphery in the guard ring region. It occurs in large quantities. At this time, the electric field value EC in the guard ring region is larger in the corner pattern portion bent at a certain radius of curvature than in the linear pattern portion in the planar pattern of the guard ring portion 105. Of the generated carriers, holes flow out to the nearby emitter electrode 110 or emitter electrode lead wire 110a, electrons flow to the P ⁺ type semiconductor layer substrate 101, and new holes are injected. At this time, the current generates a flow indicated by an arrow in FIG. Among these, the hole current a reaches the emitter electrode pad through the thin emitter electrode lead wire 110 a drawn along the P-type semiconductor layer 104, so that the resistance is large due to the wiring, and the current that flows directly to the emitter electrode 110. The amount is smaller than b. As a result, more current is concentrated in the cell region near the curved pattern portion of the guard ring portion.

As a result, a large current a flows through the P-type semiconductor layer 103 in the cell region near the guard ring curve pattern portion, and a pn junction between the N ⁺ semiconductor layer 106 and the p-type semiconductor layer 103 is forward-biased due to the occurrence of a voltage drop. The operation of the parasitic transistor is induced and is easily destroyed due to current concentration.

Therefore, in order to avoid the breakdown due to the latch-up, a p-type semiconductor layer is formed on the surface of the N ⁻ semiconductor layer between the cell region and the guard ring portion, and the emitter electrode in the cell region is extended to the outer periphery. A technique has been developed in which the current concentration generated in the vicinity of the guard ring portion when the surge voltage is applied is bypassed to the emitter electrode 110 in contact with the P-type semiconductor layer 103 so as to be in contact with the P-type semiconductor layer 103 (for example, , See Patent Document 1).

  However, in order to provide the latch-up resistance in the IGBT, when the technique described in Patent Document 1 is used, a wide P-type semiconductor layer is provided between the guard ring portion and the cell region, so that the entire cell area is large. There was a problem.

Further, the latch-up resistance is not yet sufficient, and more effective latch-up measures have been demanded.
JP-A-7-249765

  SUMMARY OF THE INVENTION An object of the present invention is to perform an effective latch-up countermeasure that eliminates an increase in the total cell area which is a problem in order to provide latch-up resistance in an IGBT.

  In view of the above-described problems, an object of the present invention is to provide a semiconductor device provided with a countermeasure against latch-up without increasing the total cell area and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device and a manufacturing method thereof according to the present invention are configured as follows.

  A first semiconductor device (corresponding to claim 1) is formed on a first conductive type high resistance layer, a first conductive type buffer layer located under the first conductive type high resistance layer, and an upper portion of the first conductive type high resistance layer. A second conductivity type base layer, a first conductivity type emitter region formed on the upper surface of the second conductivity type base layer, an emitter electrode connected to the emitter region and the base region, a second conductivity type A gate electrode formed on the channel region of the base layer via silicon oxide, a guard ring portion, and a lower surface of the first conductivity type buffer layer, immediately below the region where the guard ring portion is provided, It is characterized by comprising a collector layer of a second conductivity type having a lower impurity concentration than other regions and a collector electrode connected to the collector layer.

  In the second semiconductor device (corresponding to claim 2), the impurity concentration of the second conductivity type collector layer immediately below the guard ring portion in the above device is preferably the second conductivity type collector in the other region. It is characterized by being an order of magnitude smaller than the impurity concentration of the layer.

  A first semiconductor device manufacturing method (corresponding to claim 3) includes a step of forming a first conductivity type high resistance layer on an upper surface of a first conductivity type semiconductor substrate to be a buffer layer, and a second conductivity type base. Forming a layer and a second conductivity type guard ring, forming a first conductivity type emitter region on the upper surface of the second conductivity type base layer, and forming an emitter electrode joined to the emitter region A step of forming a gate electrode through a silicon oxide film on the channel region of the second conductivity type base layer, and a region immediately below the region where the guard ring portion is provided from the lower surface side of the first conductivity type semiconductor substrate. And the collector layer forming step of adding the second conductivity type impurity at a concentration lower than the impurity concentration in the other region, and the step of joining the collector electrode to the collector layer.

  According to a second method for manufacturing a semiconductor device (corresponding to claim 4), in the above method, preferably, the collector layer forming step uniformly distributes impurities of the second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate. And a step of performing ion implantation only on the back surface of the semiconductor substrate immediately below the other region by masking the back surface of the semiconductor substrate immediately below the region where the guard ring portion is provided. .

  According to a third method of manufacturing a semiconductor device (corresponding to claim 5), in the above method, preferably the collector layer forming step is performed immediately below the region where the guard ring portion is provided than below the other region. A mask forming step of forming a thickened mask on the lower surface of the semiconductor substrate, and a step of ion-implanting impurities of the second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate. It is done.

  A first conductivity type high resistance layer, a first conductivity type buffer layer located therebelow, a second conductivity type base layer formed on top of the first conductivity type high resistance layer, and a second conductivity type A first conductivity type emitter region formed on the upper surface of the base layer, an emitter electrode connected to the emitter region, and a gate formed on the channel region of the second conductivity type base layer via a silicon oxide film Impurity concentration is lower in the region immediately below the electrode, the guard ring portion with deep diffusion around the cell region, and the lower surface of the first conductivity type buffer layer provided with the guard ring portion. Since the second conductivity type collector layer and the collector electrode connected to the collector layer are provided, the latch-up resistance, which is a weak point of the insulated gate bipolar transistor, can be improved without increasing the device area. It is possible.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments (examples) of the invention will be described with reference to the accompanying drawings.

FIG. 1 is a partial cross-sectional view of an IGBT according to this embodiment. The IGBT 10 includes a first conductivity type high resistance layer (N ⁻ type semiconductor layer) 11, a first conductivity type buffer layer (N ⁺ type semiconductor layer) 12 located therebelow, and a first conductivity type high resistance layer. The second conductivity type base layer (P type semiconductor layer) 13 and P type semiconductor layer 14 formed on the top, and the first conductivity type emitter region (N ⁺⁾ formed on the upper surface of the second conductivity type base layer. Type semiconductor layer) 15, an emitter electrode 16 connected to the emitter region 15, a gate electrode 18 formed on the channel region 17 of the base layer 13 of the second conductivity type, and diffusion around the emitter region. A deeper guard ring 19 and a second conductivity type collector formed on the lower surface of the first conductivity type buffer layer 12 and having a lower impurity concentration than other regions immediately below the region where the guard ring portion is provided. Layer (P ⁺ type semiconductor layer) 20, 21 and a collector electrode 22 connected to the collector layers 20 and 21. Preferably, the impurity concentration of the second conductivity type collector layer 21 immediately below the guard ring portion is an order of magnitude smaller than the impurity concentration of the second conductivity type collector layer 20 in other regions. That is, the concentration of the collector layer is set to be lower than that in the other regions immediately below the guard ring. Specifically, the guard ring directly below the 1.0 × ¹⁰ 18 ^{(cm -3)} or 1.0 × ¹⁰ 19 ^{(cm -3)} in the range, other areas of 1.0 × ¹⁰ 19 (cm ^{- 3} ) It is desirable to form in the range of 1.0 × 10 ²⁰ (cm ⁻³ ) or less.

In the above configuration, a current path is formed between the collector electrode 22 and the emitter electrode 16 by forming a channel by applying a voltage to the gate electrode 18. In contrast to such normal operation, when a surge voltage higher than the normal operating voltage is applied between the collector electrode 22 and the emitter electrode 16, a depletion layer spreads in the high resistance N ⁻ type semiconductor layer 11. Here, in the A region, the depletion layer extends in the adjacent base region 13 and the N ⁻ -type semiconductor layer 11 located between the adjacent base regions 13 and overlaps with each other, thereby relaxing the electric field. The maximum electric field value EA is obtained at the pn junction at the bottom of the base region 13.

On the other hand, a P-type semiconductor layer 14 is formed outside the end portion of the base region 13. In the region (B region) from the end portion of the P-type semiconductor layer 14 to the end portion of the N ⁻ -type semiconductor layer 11, The electric field relaxation effect disappears, and the maximum electric field value EB is taken on the outer peripheral portion of the P-type semiconductor layer 14 or the surface of the N ⁻ -type semiconductor layer 11 in the vicinity thereof. Here, in general, EA <EB. In order to reduce the EB value and improve the breakdown voltage of the B region close to the EA value, a guard ring portion 19 arranged repeatedly is provided to reduce the maximum electric field EB of the B region and improve the breakdown voltage of the element. Yes.

The electric field value EC in the guard ring region increases when a surge voltage is applied to the collector electrode 22, and the electron-hole pair due to collision ionization is outside the guard ring portion 19 located at the outermost periphery in the guard ring region. In large quantities. At this time, the electric field value EC in the guard ring region is larger in the corner pattern portion bent at a certain radius of curvature than in the linear pattern portion in the planar pattern of the guard ring portion 19. Of the generated carriers, holes flow out to the nearby emitter electrode 16 or emitter electrode routing line 16a, electrons flow to the P ⁺ type semiconductor layer substrate 21, and new holes are injected. However, at this time, since the impurity concentration of the P-type semiconductor layer 21 immediately below the guard ring portion is lower than that of the other regions 20, the injection of holes is reduced. As a result, current concentration is relaxed and latch-up breakdown is prevented.

  FIG. 2 is a flowchart showing a process of manufacturing an insulated gate bipolar transistor (IGBT) by the method of manufacturing a semiconductor device according to the embodiment of the present invention. The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive type high-resistance layer on a first conductive type semiconductor substrate (step S10), a second conductive type base layer, and a second conductive type. Forming a guard ring portion (step S11), forming a first conductivity type emitter region on the upper surface of the second conductivity type base layer (step S12), and forming an emitter electrode joined to the emitter region. A step of forming (step S13), a step of forming an insulating gate electrode on the channel region of the base layer of the second conductivity type (step S14), and a step of grinding the semiconductor substrate of the first conductivity type (step S15). And collector layer formation in which the impurity concentration is just below the region where the guard ring portion is provided from the lower surface of the second conductivity type semiconductor substrate at a concentration lower than the impurity concentration in other regions. Extent and (step S16), and includes a step (step S17) of bonding the collector electrode to the collector layer.

In the step of forming the first conductivity type high resistance layer on the first conductivity type semiconductor substrate (step S10), first, a relatively low resistance N ⁺ type silicon substrate (first conductivity type semiconductor substrate) 12A is formed. Prepare (FIG. 3A). A relatively high resistance N ⁻ type semiconductor layer (first resistance type high resistance layer) 11 is epitaxially grown on the N ⁺ type silicon substrate 12A (FIG. 3B).

In the step of forming the second conductivity type base layer and the second conductivity type guard ring portion (step S11), first, a P type impurity is selectively added to the surface of the epitaxially grown N ⁻ type semiconductor layer 11. Then, a P-type base region (second conductivity type base layer) 13, a P-type semiconductor layer 14, and a guard ring portion 19 are formed (FIG. 4A). In the step of forming the first conductivity type emitter region on the upper surface of the second conductivity type base layer (step S12), an N type impurity is selectively added to the surface of the P type base region 13 to form an N ⁺ type emitter. Region (first conductivity type emitter region) 15 is formed (FIG. 4B). A surface portion of the P-type base region 13 sandwiched between the N ⁺ -type emitter region 15 and the N ⁻ -type semiconductor layer 11 becomes a channel region 17.

Next, in the step of forming an insulating gate electrode on the channel region of the second conductivity type base layer (step S14), the gate electrode 18 is formed on each channel region 17 via the gate oxide film 23, Further, in the step of forming an emitter electrode joined to the emitter region (step S13), the emitter electrode 16 is formed over a part of each N ⁺ -type emitter region 15 and the P-type base region 13 (FIG. 4C). ).

Next, in the step of grinding the first conductivity type semiconductor substrate (step S15), the N ⁺ type silicon substrate 12A, which is the first conductivity type semiconductor substrate, is ground to a predetermined thickness.

  In the collector layer forming step (step S16) in which the impurity concentration is just below the region where the guard ring portion is provided from the lower surface of the semiconductor substrate of the first conductivity type at a concentration lower than the impurity concentration in other regions. The step of uniformly ion-implanting impurities of the second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate 12A ground in step S15 (FIG. 5A), and the region where the guard ring portion is provided 5 (b)) in which a mask (for example, an oxide film or a nitride film) 24 is formed on the back surface of the semiconductor substrate immediately below the semiconductor substrate and ions are implanted only into the back surface of the semiconductor substrate immediately below the other regions. Thereby, the impurity concentration in the collector layer 21 immediately below the region where the guard ring portion is provided can be made lower than the impurity concentration in the other region 20.

  In the step of joining the collector electrode to the collector layer (step S17), the collector electrode 22 is formed on the collector layer 21 and the lower surface of the other region 20 (FIG. 5C).

  Note that the impurity concentration immediately below the region where the guard ring portion is provided from the surface opposite to the first conductivity type buffer layer of the second conductivity type semiconductor substrate is smaller than the impurity concentration in other regions. In the collector layer forming step (step S16) in which the impurity is added in FIG. 6, as shown in FIG. 6, a mask immediately below the region where the guard ring portion is provided is thicker than the region directly below the other region (for example, And a mask forming step (FIG. 6A) for forming an oxide film or a nitride film on the back surface of the semiconductor substrate 12A and ion implantation of impurities of the second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate. You may perform a process so that it may consist of a process (FIG.6 (b)). Thereby, the impurity concentration in the collector layer 21 immediately below the region where the guard ring portion is provided can be made lower than the impurity concentration in the other region 20.

FIG. 7 is a graph showing the impurity concentration distribution of the P ⁺ type semiconductor layer in the IGBT part and the guard ring part of the IGBT manufactured as described above. A curve C10 shows the depth distribution of the impurity concentration in the IGBT portion, and a curve C11 shows the depth distribution of the impurity concentration in the guard ring portion. It can be seen that the impurity concentration is lower in the guard ring part than in the IGBT part.

  FIG. 8 is a graph showing the hole current density in the cut line 1 during the ON operation. Curve C12 is the hole current density in the conventional structure, and curve C13 is the hole current density in the new structure. It can be seen that the hole current density is smaller in the new structure.

  FIG. 9 is a graph showing latch-up characteristics according to a device simulation drift diffusion model. The horizontal axis represents the collector-emitter voltage, and the vertical axis represents the collector current. A curve C14 shows a conventional structure, and a curve C15 shows a new structure. It can be seen that the latch-up tolerance has increased.

  As described above, according to the present invention, it is possible to improve the latch-up resistance, which is a weak point of the insulated gate bipolar transistor, without increasing the device area.

  The present invention can be used to manufacture an insulated gate bipolar transistor with increased latch-up resistance.

1 is a partial cross-sectional view of an insulated gate bipolar transistor (IGBT) according to an embodiment of the present invention. It is a flowchart which shows the process of manufacturing an insulated gate bipolar transistor (IGBT) with the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the semiconductor substrate in each process. It is sectional drawing of the semiconductor substrate in each process. It is sectional drawing of the semiconductor substrate in each process. It is sectional drawing of the semiconductor substrate in each process. It is a graph which shows the carrier concentration distribution of the P ⁺ type semiconductor layer in a guard ring part. It is a graph which shows the hole current density in the cut line 1 at the time of ON operation. It is a graph which shows a latchup characteristic. It is a partial cross-sectional view of a conventional insulated gate bipolar transistor (IGBT).

Explanation of symbols

10 IGBT
11 N ⁻ type semiconductor layer 12 N ⁺ type semiconductor layer 13 P type semiconductor layer (base region)
15 Emitter region 17 Channel region 18 Gate electrode 19 Guard ring portion 20 Collector layer 21 Collector layer 22 Collector electrode

Claims (5)

A first conductivity type high-resistance layer and a first conductivity type buffer layer located therebelow;
A second conductivity type base layer formed on top of the first conductivity type high resistance layer;
A first conductivity type emitter region formed on an upper surface of the second conductivity type base layer;
An emitter electrode connected to the emitter region;
A gate electrode formed on the channel region of the base layer of the second conductivity type via a silicon oxide film;
A guard ring that deepens the diffusion around the cell area;
A collector layer of a second conductivity type formed on the lower surface of the buffer layer of the first conductivity type and having a lower impurity concentration than the other region immediately below the region where the guard ring portion is provided;
A semiconductor device comprising a collector electrode connected to the collector layer.   The impurity concentration of the collector layer of the second conductivity type immediately below the guard ring part is smaller by one digit than the impurity concentration of the collector layer of the second conductivity type in the other region. 1. The semiconductor device according to 1. Forming a first conductivity type high resistance layer on the upper surface of the first conductivity type semiconductor substrate to be a buffer layer;
Forming a second conductivity type base layer and a second conductivity type guard ring portion;
Forming a first conductivity type emitter region on an upper surface of the second conductivity type base layer;
Forming an emitter electrode bonded to the emitter region;
Forming a gate electrode on the channel region of the base layer of the second conductivity type via a silicon oxide film;
Collector layer formation in which the impurity concentration of the second conductivity type is added at a concentration lower than the impurity concentration in the other region, immediately below the region where the guard ring portion is provided from the lower surface side of the first conductivity type semiconductor substrate Process,
A method of manufacturing a semiconductor device, comprising: a step of bonding a collector electrode to the collector layer. The collector layer forming step includes a step of uniformly ion-implanting impurities of a second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate;
4. The method according to claim 3, further comprising a step of masking a back surface of the semiconductor substrate immediately below the region where the guard ring portion is provided and implanting ions only to the back surface of the semiconductor substrate immediately below the other region. The manufacturing method of the semiconductor device of description. The collector layer forming step includes forming a mask on the lower surface of the semiconductor substrate in which the thickness immediately below the region where the guard ring portion is provided is thicker than directly below the other region;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of ion-implanting impurities of a second conductivity type over the entire lower surface of the first conductivity type semiconductor substrate.

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