JP2005129187A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time from the start of power supply to the confirmation of power supply rise to the start of operation.
SOLUTION: A normal operation control circuit 9 capable of normal operation when a power source rises to a predetermined level, and connected to the normal operation control circuit 9 when the normal operation control circuit 9 is powered on. Based on the result of the operation confirmation of the operation confirmation sequencer control circuit 4 for sending the operation confirmation signal to the operation confirmation sequencer 5 and the normal operation control circuit 9 performed by this operation confirmation signal, the normal operation control circuit 9 is And a confirmation instruction / determination circuit 6 for instructing the operation.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device such as an LSI having a part that operates intermittently, and relates to reduction of power consumption.

  Conventionally, a semiconductor device such as an LSI having a part that operates intermittently, the part (hereinafter referred to as a “normal operation circuit”) is turned off when not in operation and turned on when necessary. I was trying to save power consumption.

  In addition, the operation of the normal operation circuit needs to be started after the voltage of the normal operation circuit sufficiently rises. As such a technique, a technique for starting a normal operation when a predetermined time has elapsed since the power-on of the semiconductor device (hereinafter referred to as “first conventional technique”), or a dummy data in a memory provided on the LSI is provided. And confirm that the LSI's internal power supply is in a stable state based on whether or not the dummy data read from the memory has been properly processed after the LSI's power is turned on. There is a technology (hereinafter referred to as “second conventional technology”) that starts the process. The first and second prior arts are described in Patent Document 1 below.

Japanese Unexamined Patent Publication No. 2002-208300 (second page, FIG. 1)

  However, since the first conventional technique starts normal operation after the voltage has risen reliably, it is necessary to set the start timing of normal operation with a certain margin. Therefore, the normal operation circuit has a problem that there is a margin in the time from when the voltage rises to the start of normal operation, and the time for consuming the power becomes long.

  The second prior art requires time until the memory voltage rises to such an extent that data can be read, and the memory voltage does not necessarily rise sufficiently when the voltage of the normal operation circuit rises sufficiently. . Therefore, the normal operation circuit has a problem that it takes a time from when the voltage rises until the dummy data is read, and the time for consuming the power becomes long.

  Therefore, the present invention has been made to solve the above-described problems, and shortens the time until the normal operation actually starts after the voltage of the normal operation circuit rises to an operable level. Accordingly, an object is to reduce power consumption of the semiconductor device.

  The semiconductor device according to the present invention is supplied with power at the start of operation and can operate normally when the power source rises to a predetermined level, and operates on the normal operation circuit when the power supply of the normal operation circuit is started. Confirmation signal sending means for sending a confirmation signal, and command means for commanding the normal operation circuit to the normal operation circuit based on the operation result of the normal operation circuit based on the operation confirmation signal sent from the confirmation signal sending means.

  According to the present invention, since the operation command is output to the normal operation circuit after confirming that the voltage of the normal operation circuit has risen, the normal operation circuit is in a period from when the voltage rises sufficiently until the operation is started. There is no need to make room. Further, since the operation command for the normal operation circuit is always output after the voltage of the normal operation circuit rises, the operation can be reliably started. Further, since the confirmation signal sending means sends an operation confirmation signal to the normal operation circuit when the voltage of the normal operation circuit rises, the command means starts the normal operation of the normal operation circuit quickly after the voltage of the normal operation circuit rises. There is an effect that can be made.

An embodiment of the present invention will be described below.
Embodiment 1 FIG.
1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. The illustrated semiconductor device 1 is, for example, divided into two power source regions, that is, a region 2 to which power is constantly supplied and a region 3 having a circuit used for normal operation. The power supply is configured to be supplied. The area 2 is provided with an operation confirmation sequencer control circuit (confirmation signal sending means) 4 and a confirmation instruction / determination circuit (command means) 6, and the area 3 has a normal operation control circuit (normal operation circuit) 9 and a plurality of An operation confirmation sequencer (operation confirmation means) 5 is provided, and FIG. 1 shows an example in which five operation confirmation sequencers 5 are provided.

  The operation confirmation sequencer 5 is for confirming the operation of the normal operation control circuit 9 provided in the area 3 and has a function suitable for the circuit characteristics or application / configuration of the operation confirmation target. The detailed configuration and sequence contents of the sequencer 5 differ depending on the circuit to be confirmed. For example, when the confirmation target circuit of the normal operation control circuit 9 is a counter, the operation confirmation sequencer 5 operates the counter to confirm that a desired count value is obtained at a desired timing. Note that the number of operation check sequencers 5 provided in the region 3 is provided according to the number of circuits for checking the operation, and is not limited to five as described above. The normal operation control circuit 9 may be, for example, a transmitter, a receiver, a modulator, a demodulator, an encoder, a decoder, or the like of a mobile phone.

Next, the operation will be described.
FIG. 2 is a flowchart showing the operation of the semiconductor device according to the first embodiment. The operation of the semiconductor device 1 according to the first embodiment will be described with reference to FIG. 2, after the confirmation instruction / determination circuit 6 outputs an instruction signal for confirming the operation of the normal operation control circuit 9, the normal operation control circuit 9, i.e., the semiconductor device 1. Shows the process up to normal operation. The region 2 of the semiconductor device 1 is always supplied with power, and the confirmation instruction / determination circuit 6 and the operation confirmation sequencer control circuit 4 are activated. When the power for normally operating the semiconductor device 1 is turned on, the confirmation instruction / determination circuit 6 that has already been activated detects that the power supply to the region 3 has started, and the normal operation control circuit for the region 3 An instruction signal is output to the operation confirmation sequencer control circuit 4 so as to confirm the operation 9 (step ST1). The operation check sequencer control circuit 4 receiving this instruction signal outputs the operation check signal to each operation check sequencer 5 provided in the area 3 (step ST2). The operation check sequencer 5 having received the operation check signal starts a sequence process for checking the operation of the normal operation control circuit 9 in the region 3 (step ST3).

  Each operation confirmation sequencer 5 performs a confirmation process by a predetermined sequence process on the normal operation control circuit 9, confirms the operation of the circuit, generates a signal indicating the result, and operates in the region 2. Output to the confirmation sequencer control circuit 4. The operation confirmation sequencer control circuit 4 determines whether the confirmation results input from all the operation confirmation sequencers 5 are “good” or not (step ST4). The operation check sequencer control circuit 4 determines that all the operation check target circuits provided in the area 3 operate normally when it is determined that all the operation check results indicate “good”. When confirmed, the determination result of the content is returned to the confirmation instruction / determination circuit 6 (step ST5). In step ST4, if even one of the operation confirmation target circuits cannot be confirmed to operate normally, the process returns to step ST2, and the operation confirming sequencer control circuit 4 performs the normal operation again. A confirmation instruction signal is output to the operation confirmation sequencer 5 in charge of the circuit that could not be confirmed, and the processes of steps ST2 to ST4 are repeated until the operation confirmation result is determined to be “good”.

  When the confirmation instruction / determination circuit 6 determines from the determination result input from the operation confirmation sequencer control circuit 4 that the power supply in the area 3 is on, it sends a command to the normal operation control circuit 9 to perform normal operation. . For example, the confirmation instruction / determination circuit 6 that has determined that the power supply of the region 3 has been started up is such that the operation confirmation sequencer 5 does not interfere with the operation processing of each circuit that constitutes the normal operation control circuit 9. The operation check sequencer 5 is set so that each control signal is output and predetermined parameters are set so that the operation check sequencer 5 is electrically disconnected from the circuit. In this way, control is transferred to normal operation (step ST6), and normal operation of the normal operation control circuit 9, that is, the semiconductor device 1, is started (step ST7).

  It should be noted that even if the operation confirmation sequencer control circuit 4 and the confirmation instruction / determination circuit 6 provided in the region 2 are provided outside the semiconductor device 1, the same effects can be obtained. Further, even if the operation check sequencer control circuit 4 is provided in the area 3, the same effect can be obtained. Further, here, the semiconductor device 1 configured by separating the inside into two power supply regions has been described. However, the semiconductor device is separated into three or more power supply regions so that individual power is supplied to each region. As shown in the area 2 shown in FIG. 1, the operation confirmation sequencer control circuit 4 and the confirmation instruction / determination circuit 6 are provided in an area where power is constantly supplied, and the semiconductor device is turned on. Even if the operation of each circuit provided in each region where power supply is started is confirmed, the same effect can be obtained.

  As described above, according to the first embodiment, when the confirmation instruction / determination circuit 6 confirms that the supply voltage to the normal operation control circuit 9 has risen, the operation command is transmitted to the normal operation control circuit 9. Since the output is performed, there is an effect that it is not necessary to provide a margin between the supply voltage sufficiently rising and the normal operation control circuit 9 starting the operation.

  Further, since the confirmation instruction / determination circuit 6 always outputs the operation command to the normal operation control circuit 9 after the supply voltage to the normal operation control circuit 9 rises, the normal operation control circuit 9 There is an effect that the operation can be started reliably.

  Further, since the operation confirmation sequencer control circuit 4 sends an operation confirmation signal to the normal operation control circuit 9 when the supply voltage of the normal operation control circuit 9 rises, the voltage of the normal operation control circuit 9 is After the start-up, the confirmation instruction / determination circuit 6 has an effect that the normal operation of the normal operation control circuit 9 can be started quickly.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention. The same reference numerals are used for the same or corresponding parts as shown in FIG. The semiconductor device 1a shown in FIG. 3 includes a memory control circuit (command means) 7 composed of a processor or the like and a memory 8 for storing a plurality of test data and the like in a region 2 to which power is always supplied. The region 3 to which power is supplied by turning on the power to the semiconductor device 1a is provided with a normal operation control circuit 9 that performs each process when the semiconductor device 1a performs normal operation. The normal operation control circuit 9 is composed of, for example, a digital circuit such as a counter and a selector, or an analog circuit. Here, for simplicity of explanation, the normal operation control circuit 9 is shown as one block, but it is the same as that described in the first embodiment, and is used in normal operation of the counter and the like. It may be provided with a plurality of circuits.

Next, the operation will be described.
FIG. 4 is a flowchart showing the operation of the semiconductor device according to the second embodiment. The operation of the semiconductor device 1a according to the second embodiment will be described with reference to FIG. 4 shows a process from when the memory control circuit 7 outputs an instruction signal for confirming the operation of the normal operation control circuit 9 to when the semiconductor device 1a reaches a normal operation. Test data used for operation confirmation is stored in the memory 8 in advance. The memory control circuit 7 in the region 2 to which power is always supplied is on standby in a state where test data can be read from the memory 8. When the power for performing the normal operation is turned on to the semiconductor device 1a, the power-on command unit provided in the semiconductor device 1a (not shown in FIG. 3) controls the normal operation in the region 3 where the power supply is started. A command signal is output to the circuit 9 to activate the normal operation control circuit 9. Further, the power-on command unit outputs this command signal to the memory control circuit 7 in the area 2 at the same time. The memory control circuit 7 receives this command signal and detects that power is supplied to the area 3 (step ST10). When the memory control circuit 7 detects that the power supply to the area 3 is started, the memory control circuit 7 reads predetermined test data from the memory 8 (step ST11), and operates the normal operation control circuit 9 so as to process the test data. An instruction is given to perform a predetermined operation (step ST12).

  The memory control circuit 7 receives a response from the normal operation control circuit 9, that is, the test data processing result from the normal operation control circuit 9, and determines whether the normal operation control circuit 9 is good or not based on this processing result. Is determined (step ST13). If the predetermined result expected in advance is not obtained, it is considered that the normal operation control circuit 9 is not sufficiently activated, so the process returns to step ST12 again, and the memory control circuit 7 An operation instruction is given to the normal operation control next circuit 9 so as to process the test data.

  The memory control circuit 7 causes the normal operation control circuit 9 to execute a plurality of different test data in the normal operation control circuit 9 to confirm the operation. In step ST13, when a predetermined result expected in advance is notified, it is determined whether or not the final operation confirmation is made (step ST14). The memory control circuit 7 recognizes which test data is to be processed when the test data is supplied to the normal operation control circuit 9, so whether or not a plurality of predetermined test data has been processed is determined in step ST14. judge. When there is test data that has not been processed yet, the process returns to the process of step ST11, the test data that has not been processed yet is read from the memory 8, and the process of step ST11 to step ST14 is repeated to obtain a predetermined plurality of test data. The control circuit 9 for normal operation is processed. In step ST14, when confirming that the last test data has been executed by the normal operation control circuit 9, the memory control circuit 7 outputs an operation command to the normal operation control circuit 9 so as to start normal operation. To do. Specifically, the memory control circuit 7 sets the normal operation control circuit 9 in a state in which a predetermined operation when performing the normal operation is possible (step ST15). The normal operation control circuit 9 starts normal operation (step ST16), and the semiconductor device 1a starts normal operation based on the operation by performing the above-described operation.

  Note that the memory control circuit 7 and the memory 8 provided in the region 2 of the semiconductor device 1a can obtain the same function and effect even in a configuration provided outside the semiconductor device 1a. Even when the memory control circuit 7 and the memory 8 provided in the region 2 are provided in the region 3, the time from when the semiconductor device 1a is turned on until the normal operation is started is as described above. Although it cannot be shortened as compared with the semiconductor device 1a, it is possible to confirm the pros and cons of the operation of each circuit used in the normal operation of the semiconductor device.

  Further, the operation check sequencer 5 shown in FIG. 1 is incorporated in each point of the normal operation control circuit 9 and the operation check sequencer 5 is used to check the operation of the normal operation control circuit 9 by sequence control. Then, it may be confirmed that power is supplied to the region 3. Further, here, the semiconductor device 1a is described in which the interior is separated into two power supply regions in the same manner as in the description of the first embodiment. However, the interior is separated into three or more power supply regions, and each region is individually separated. A similar effect can be obtained even in a semiconductor device that is configured to include the memory control circuit 7 and the memory 8 in a region where the power is constantly supplied and in which the power is always supplied.

  As described above, according to the second embodiment, the memory control circuit 7 causes the normal operation control circuit 9 to process the test data, and determines whether the normal operation control circuit 9 is operable from the processing result. If the operation is possible, an operation command is output to the normal operation control circuit 9, so that there is a margin between the supply voltage sufficiently rising and the normal operation control circuit 9 starting the operation. There is an effect that it is not necessary.

  Further, since the memory control circuit 7 always outputs the operation command to the normal operation control circuit 9 after the supply voltage to the normal operation control circuit 9 rises, the operation of the normal operation control circuit 9 is performed. There is an effect that can be started reliably.

  Further, since the memory control circuit 7 sends test data to the normal operation control circuit 9 when the supply voltage of the normal operation control circuit 9 rises, after the voltage of the normal operation control circuit 9 rises, The memory control circuit 7 has an effect that the normal operation of the normal operation control circuit 9 can be started quickly.

  In addition, it is possible to confirm the start-up of the power supply without providing an operation confirmation unit for confirming the operation of the normal operation control circuit 9, and there is an effect that the configuration of the semiconductor device 1a can be simplified.

1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 3 is a flowchart showing the operation of the semiconductor device according to the first embodiment. It is a block diagram which shows schematic structure of the semiconductor device by Embodiment 2 of this invention. 6 is a flowchart showing the operation of the semiconductor device according to the second embodiment.

Explanation of symbols

  1, 1a Semiconductor device, 2, 3 area, 4 operation confirmation sequencer control circuit (confirmation signal sending means), 5 operation confirmation sequencer (operation confirmation means), 6 confirmation instruction / determination circuit (command means), 7 memory control Circuit (command means), 8 memory, 9 control circuit for normal operation (normal operation circuit).

Claims (5)

Normal operation circuit that is supplied with power at the time of operation check and can perform normal operation when the power rises to a predetermined level,
Confirmation signal sending means for sending an operation confirmation signal to the normal operation circuit when the power supply of the normal operation circuit is turned on;
A semiconductor device comprising command means for instructing a normal operation to the normal operation circuit based on an operation result of the normal operation circuit based on an operation confirmation signal sent from the confirmation signal sending means.   The confirmation signal sending means sends an operation confirmation signal to a plurality of operation confirmation means connected to the normal operation circuit, and when the operation result of the normal operation circuit by the plurality of operation confirmation means is determined to be good, the operation result The semiconductor device according to claim 1, wherein: is sent to the command means.   The confirmation signal sending means sends an operation confirmation signal to the operation confirmation means again when a good operation result is not obtained from the normal operation circuit, and confirms the operation until the operation result becomes good. The semiconductor device according to claim 2, wherein: Normal operation circuit that is supplied with power at the time of operation check and can perform normal operation when the power rises to a predetermined level,
A semiconductor device comprising: command means for sending test data to the normal operation circuit when the power supply of the normal operation circuit is turned on, and instructing the normal operation circuit to perform a normal operation based on a processing result of the test data apparatus.   5. The semiconductor device according to claim 4, wherein the command means sequentially sends a plurality of test data, and commands a normal operation when the processing results of all the test data are good.

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