JP2005124089A - Video signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display an image in which a skew is not conspicuous with a small circuit configuration which does not require a time base collector or the like.
A pulse generation timing is generated corresponding to a count value of a horizontal synchronization signal separated from a video signal, and a masking pulse generation unit that outputs a masking pulse at the generated timing is synchronized with the horizontal synchronization signal. A PLL unit for generating a video signal processing clock and holding a control voltage of the voltage controlled oscillator while a masking pulse is supplied. For example, if the timing of masking pulse generation is set near the vertical blanking period of the input video signal, even if there is a sudden fluctuation in the horizontal period near the vertical blanking period of the input video signal, the fluctuation Since the oscillation frequency of the PLL unit in the vicinity of the period during which the PLL occurs is kept constant, fluctuations in the clock frequency output by the PLL unit are prevented.
[Selection] Figure 4

Description

  The present invention relates to a video signal processing apparatus suitable for application to, for example, a television receiver, and more particularly to processing for generating a clock synchronized with a horizontal synchronizing signal.

  Conventionally, when a video signal reproduced from a video tape recorder (VTR) is displayed on a television receiver, processing for preventing the occurrence of skew, which is an area where the video is distorted during special reproduction, from being included in the display area has been performed. ing. The point where the skew occurs during special playback in the VTR enters the display area when signal processing having a delay of several H (several horizontal periods) is performed in the television receiver. It is common for television receivers to have a delay of several H.

  The relationship between the delay of the number H and the occurrence of the skew entering the display area will be described below. In a television receiver, a horizontal synchronization signal separated from an input video signal is input to a PLL unit (phase locked loop unit), and a system clock synchronized with the horizontal period of the video signal is generated by the PLL unit. However, video processing in the television receiver is performed with the system clock. The horizontal synchronization signal input to the PLL unit is input to a phase comparator inside the PLL unit. The phase comparator compares the phase of the input horizontal synchronization signal with the pulse obtained by dividing the system clock output from the voltage controlled oscillator (VCO), and outputs the phase difference as a voltage. This voltage is input as a control voltage to the VCO through a low-pass filter (LPF), and the frequency of the system clock is adjusted so that there is no phase shift.

  Here, since the PLL unit has a quick response, in normal broadcasting, it follows the fluctuation of the horizontal synchronizing signal, supplies a stable clock, and can display a good image. However, in the case of a video signal reproduced from a VTR, since the horizontal synchronization signal fluctuates abruptly when the head is switched, the clock also fluctuates abruptly and image disturbance called skew occurs. When a delay of about several H, for example, about 8H, occurs in the signal processing in the television receiver, the image disturbance is not noticeable in the overscan area in normal reproduction, but the power of the television receiver is not noticeable. There is a possibility that the overscan area is narrowed and displayed due to variations due to voltage fluctuations or aging deterioration of circuit components of the deflection system. Further, the number of horizontal lines increases or decreases during special reproduction with a VTR, and skew is displayed when the number of horizontal lines decreases.

  FIG. 5 is a diagram showing the relationship between the occurrence of this skew and a delay of about several H at the receiver. It is assumed that the vertical line a1 is displayed in the display video a when the input video signal is displayed without delay at the same timing. At this time, if there is a delay DL of 8H period from the input of the video signal by signal processing, the video displayed on this receiver is the display video b as shown on the right side of FIG.

  Here, the input video signal at this time is a video signal reproduced by a VTR, and there is an abrupt change in horizontal synchronization timing due to switching of the reproduction head at timing t1 in the vicinity of the vertical blanking period Vsync of the input video signal. And At this time, the vertical blanking period Vsync shown in FIG. 5 is a vertical blanking period of the video b actually displayed. However, in the PLL unit, the clock cycle changes at the synchronization timing fluctuation time t1. The horizontal synchronization timing fluctuates during a period different from the vertical blanking period Vsync of the display video b. Therefore, the timing at which the clock fluctuation occurs occurs during the timing at which the video b is displayed, and the image disturbance b2 occurs on the vertical line b1 in the display video b.

Conventionally, in order to solve such a problem, a time base collector (TBC) is used so that the synchronization timing of the video signal is constant. Patent Document 1 discloses a configuration of a time base collector used in such a case.
JP-A-6-86228

  However, this type of conventional time base collector has a problem that the configuration is complicated and expensive. In other words, the time base corrector is a circuit that stabilizes the output timing of the video signal using a memory, and includes a PLL section for input with a fast response speed and an output with a slow response speed (stable). The PLL unit is used to perform writing and reading to the memory. By providing such a time base corrector, even if there is a sudden change in the horizontal sync signal due to VTR head switching, separate clocks are used for memory input and output, so image disturbance does not occur.

  However, the time base collector configured as described above has a problem in that two PLL units are required for the memory and the write / read clock, which increases the circuit scale and the number of components.

  SUMMARY OF THE INVENTION An object of the present invention is to make it possible to display an image with less noticeable skew with a small circuit configuration.

  The present invention provides a horizontal synchronization count unit that counts a horizontal synchronization signal separated from a video signal, generates a pulse generation timing corresponding to a count value in the horizontal synchronization count unit, and generates a masking pulse at the generated timing. And a PLL unit for generating a video signal processing clock synchronized with the horizontal synchronizing signal and holding the control voltage of the voltage controlled oscillator while the masking pulse is supplied It is a device.

  By doing so, for example, by setting the generation timing of the masking pulse in the vicinity of the vertical blanking period of the input video signal, the horizontal cycle is abrupt in the vicinity of the vertical blanking period of the input video signal. Even if there is a variation, the oscillation frequency of the PLL unit is kept constant by the masking pulse during the period in which the variation occurs, so that the variation of the clock frequency output by the PLL unit is prevented.

  According to the present invention, within a predetermined period in one field period, the fluctuation of the clock synchronized with the horizontal synchronizing signal is prevented by the masking pulse, and the skew generation period is masked. When the video signal is processed by the apparatus of the present invention and the processed video signal is displayed, image disturbance due to switching of the playback header of the VTR does not occur in the display video. In this case, since a complicated configuration means such as a time base collector is not required, the display image can be stabilized with such a simple configuration.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
In this example, the present invention is applied to a circuit for generating a system clock in a television receiver, and FIG. 1 is a block diagram showing a circuit configuration for generating the system clock. The configuration shown in FIG. 1 will be described. The video signal input terminal 1 is supplied with an externally input video signal or a video signal received by a built-in tuner. The video signal obtained at the input terminal 1 is supplied to the sync separation circuit 2 to separate a composite sync signal such as a vertical sync signal, a horizontal sync signal, and an equivalent pulse contained in the video signal, and the vertical sync signal is synchronized with the horizontal sync signal. Output signals individually.

  The horizontal synchronization signal separated by the synchronization separation circuit 2 is supplied to a phase locked loop section (hereinafter referred to as PLL section) 3 and also to a horizontal synchronization counter 4. The horizontal synchronization counter 4 is also supplied with respect to the vertical synchronization signal separated by the synchronization separation circuit 2 and is supplied while being reset each time the vertical synchronization signal is supplied (that is, reset in one field period). The pulses as the synchronization signal are counted one cycle at a time. The count value L from the counter 4 is supplied to the timing pulse generation circuit 5. The timing generation circuit 5 outputs a start pulse when the count value becomes La. a is a value for determining the start position, and can be adjusted by a start position setting signal obtained at the input terminal 5a. The range that can be adjusted by the signal obtained at the input terminal 5a may be limited within a certain range.

  The start pulse generated by the timing pulse generation circuit 5 is supplied to the masking pulse generation circuit 6. The masking pulse generation circuit 6 is also supplied with the vertical synchronization signal separated by the synchronization separation circuit 2, and becomes high level from the rising edge of the start pulse supplied from the timing pulse generation circuit 5, and low level at the rising edge of the vertical synchronization signal. Is generated and supplied to the voltage controlled oscillator 33 in the PLL unit 3. The period during which the masking pulse is at a high level is a relatively short period of about several H to several tens of H, for example, in this example.

  In the PLL unit 3, the horizontal synchronization signal separated by the synchronization separation circuit 2 is supplied to one input terminal of the phase comparator 31, and compared with the output of the frequency divider 34 in the PLL unit 3, and output as a result of comparison. The error signal is averaged (direct current) by a low pass filter (LPF) 32 and supplied to a voltage controlled oscillator (VCO) 33 as a control voltage. The voltage controlled oscillator 33 is a variable frequency oscillator that oscillates at a frequency corresponding to a supplied control voltage, and each circuit (not shown) whose oscillation output processes a video signal in the television receiver as a system clock. The signal supplied to the frequency divider 34 and frequency-divided by the frequency divider 34 is returned to the phase comparator 31. Note that the voltage controlled oscillator 33 provided in the PLL unit 3 of this example is of a type having a relatively fast response speed in which the oscillation frequency changes at high speed following changes in the input voltage.

  Here, in this example, while the high level masking pulse is supplied to the voltage controlled oscillator 33 in the PLL unit 3, the oscillation frequency of the voltage controlled oscillator 33 is fixed to the frequency immediately before the masking pulse is supplied. Thus, the oscillation frequency is stabilized.

  Next, processing for generating a masking pulse with the configuration shown in FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2A shows a vertical sync pulse and FIG. 2B shows a horizontal sync pulse. The count value in the counter 4 shown in FIG. 2C is counted up to the value L while being reset to the field period by the vertical synchronization pulse. Here, when the count value becomes L−a, the timing pulse shown in FIG. 2D is generated by the timing pulse generation circuit 5, and the masking pulse shown in FIG. 2E is generated from the timing pulse generation position to the vertical synchronization pulse generation position. Is generated by the masking pulse generation circuit 6.

  FIG. 3 is a diagram showing a control state of the clock by the masking pulse generated in this way. FIG. 3A shows a synchronization signal separated from an input video signal, and it is assumed that the head portion of this synchronization pulse has a rapid horizontal cycle variation due to head switching during reproduction in a VTR. Here, regarding the output of the synchronization signal when the processing by the masking pulse of this example is not performed, as shown in FIG. On the other hand, the masking pulse shown in FIG. 3C is generated with the configuration shown in FIG. 1, and the clock cycle fluctuation in the PLL unit 3 is regulated by the masking pulse, thereby masking as shown in FIG. 3D. While the pulse is at the high level, the period variation of the synchronization pulse is restricted, and the clock period variation occurs after the masking pulse returns to the low level.

  FIG. 4 is a diagram showing a processing example using the masking pulse of this example. FIG. 4 is a diagram of a display form similar to that of FIG. 5 shown as a conventional example. In the display image a when the input image signal is displayed without delay at the same timing, a vertical line a1 is displayed. Suppose that At this time, if the video displayed in this receiver has a delay DL of 8H period from the input of the video signal, the actual display video b is as shown on the right side of FIG.

  If the input video signal at this time is a video signal reproduced by a VTR, and there is a sudden change in horizontal synchronization timing due to switching of the reproduction head at timing t1 in the vicinity of the vertical blanking period Vsync of the input video signal. To do. The vertical blanking period Vsync shown in FIG. 4 is a vertical blanking period of the video b that is actually displayed. In the PLL section, the clock period varies until the vertical blanking period is reached by the masking pulse. Thus, there is no change in the clock cycle at the synchronization timing fluctuation time t1. Accordingly, the horizontal synchronization timing fluctuates during the vertical blanking period Vsync of the display image b, and the image disturbance b2 'is not displayed in the display image b without causing the image disturbance of the vertical line b1. Get out.

  Thus, according to the receiver having the configuration of this example, when the input video signal is displayed, the video signal reproduced by the VTR is input when the input video signal is displayed with a delay of a period of several H. Thus, even if the video signal has a disturbance in the synchronization timing when the reproducing head is switched, the disturbance in the display video does not occur due to the disturbance in the synchronization timing. Therefore, it is possible to always display images without distortion without providing complicated and expensive circuit components such as a time base collector as in a conventional receiver.

  In this example, the position where the timing pulse generator 5 generates the timing pulse can be adjusted by an external signal. For example, a delay of about 1 to 2H occurs in the circuit for separating the vertical synchronization signal. Even in this case, adjustment to absorb the fluctuation is possible.

  In the embodiment described so far, the case where the system clock is generated in the television receiver has been described. However, in the case where the system clock is generated by the same processing in various video signal processing apparatuses that process the video signal. It is also applicable to. If the video signal is processed based on the system clock generated in this way, even when the video signal processed by the processing device is supplied to another receiver and displayed, The display is good without skew.

It is a block diagram which shows the structural example by one embodiment of this invention. FIG. 6 is a timing diagram illustrating the generation timing of a masking pulse according to an embodiment of the present invention. FIG. 5 is a timing diagram showing a pulse output state by a masking pulse according to an embodiment of the present invention. It is explanatory drawing which shows the example of a display by one embodiment of this invention. It is explanatory drawing which shows the example of a conventional display.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Video signal input terminal, 2 ... Synchronous separation circuit, 3 ... Phase locked loop part (PLL part), 4 ... Horizontal period counter, 5 ... Timing pulse generation circuit, 6 ... Masking pulse generation circuit, 31 ... Phase comparison 32, low-pass filter, 33 ... voltage controlled oscillator, 34 ... frequency divider

Claims (4)

A synchronization signal separation unit for separating a horizontal synchronization signal from a video signal;
A horizontal synchronization count unit that counts the horizontal synchronization signal separated by the synchronization signal separation unit in a field period;
Generating a pulse generation timing corresponding to the count value in the horizontal synchronization count unit, and outputting a masking pulse at the generated timing; and
A video signal processing apparatus comprising: a phase locked loop unit that generates a video signal processing clock synchronized with the horizontal synchronizing signal and holds a control voltage of a voltage controlled oscillator while the masking pulse is supplied. The video signal processing apparatus according to claim 1, wherein
A video signal processing apparatus capable of setting and adjusting a count value for generating a pulse generation timing in the masking pulse generator. The video signal processing apparatus according to claim 1, wherein
A video signal processing apparatus that performs video signal display processing using a clock generated by the phase-locked loop unit. The video signal processing apparatus according to claim 3, wherein
As the display process, a video signal processing apparatus that performs a display process at a timing delayed by a predetermined horizontal period from a timing at which the synchronization signal is separated by the synchronization signal separation unit.

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