JP2005124071A - Image processing apparatus, image processing method, computer-readable storage medium storing program, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure an intermediate buffer in a rectangular shape unit that is secured in accordance with conditions such as a set image processing mode, and optimize the size of the intermediate buffer between blocks according to processing contents and capability, This is to reduce the burden of buffer management processing when processing image data of a predetermined rectangular unit.
An intermediate buffer for temporarily retaining processing data for data writing processing or data reading processing for each predetermined rectangular shape unit is secured in a main memory 100, and the amount of retained data on the intermediate buffer is monitored, The buffer arbitration units 77 and 78 arbitrate data write processing or data read processing for each predetermined rectangular unit on the intermediate buffer by the DMAC 91 based on the amount of staying data.
[Selection] Figure 1

Description

  The present invention provides an intermediate buffer that is secured in a main memory and temporarily stores processing data, and is arranged in a preceding stage of the intermediate buffer. The input image data is processed in a predetermined rectangular unit and input to the intermediate buffer. An image processing apparatus, an image processing method, and a computer comprising: a first image processing block that generates data; and a second image processing block that is arranged after the intermediate buffer and that processes data read from the intermediate buffer. The present invention relates to a storage medium storing a readable program and a program.

  FIG. 35 is a block diagram showing a configuration of a scanner image processing circuit / recorded image processing circuit in a conventional image processing apparatus.

  As shown in FIG. 35, an optical element such as a CCD (Charged Coupled Device) 2010 or a CIS (Contact Image Sensor) 2110 is used as an image reading device, and data in accordance with a predetermined output format for each line in the main scanning direction. Are A / D converted by the CCD interface (CCDi / f) circuit 2000 and the CIS interface (CISi / f) circuit 2100, respectively, and stored in the main memory 2200.

  In this case, the CCD 2010 outputs data corresponding to R, G, B in parallel, whereas the signal output from the CIS 2110 outputs R, G, B data serially according to the lighting order of the LEDs. Due to the difference in the characteristics of the output data, a dedicated interface circuit is provided, and the read image data is stored in the intermediate buffer 2200-1 in the main memory (SDRAM) 2200 through a predetermined A / D conversion process. It became the composition to be.

  The LBP recording system reads compressed data from the memory, stores the compressed data in the intermediate buffer 2200-2 in the main memory (SDRAM) 2200, performs recording image processing via the intermediate buffer 2200-2, and outputs the processed data to the LBP 2530. It was.

  In FIG. 35, dedicated line buffers 2400a to 2400d are used for image processing blocks of the reading system (shading correction (SHD) 2300, character determination processing (ZSG) 2320, filter processing (NSF) 2340 (NSF), LIP 2350, etc.)). Is provided. In such a circuit configuration, data stored in the intermediate buffer 2200-1 in the main memory (SDRAM) 2200 is read in line units in the main scanning direction and stored in dedicated line buffers (2400a to 2400d). A configuration in which individual image processing is performed has been adopted.

  Each image processing block (resolution conversion) of the recording system is provided with a dedicated line buffer 2510. In such a circuit configuration, the data 2520 stored in the intermediate buffer 2200-2 in the main memory (SDRAM) 2200 is read line by line in the main scanning direction, stored in the dedicated line buffer 2510, and stored in the resolution converter 2500. Then, after the resolution conversion is performed, the output printing is performed on the LBP 2530.

  Control of writing / reading on the intermediate buffers 2200-1 and 2200-2 is managed by software.

  In the conventional method, since the intermediate buffers 2200-1 and 2200-2 in the main memory (SDRAM) 2200 are controlled in units of main scanning lines, the number of lines in the intermediate buffers 2200-1 and 2200-2 is managed by software. However, the buffer capacity does not increase extremely by adopting a processing system having two buffer units that can be controlled by software according to the processing capability of the hardware.

  As prior art which discloses the configuration of the above-described conventional example, for example, there are those disclosed in Patent Documents 1 to 3.

  In particular, Patent Document 2 describes an arbitration circuit that controls writing in line units for a dedicated line buffer.

Further, Patent Document 3 describes a remaining amount detecting means for a line buffer used in a ring shape.
JP-A-5-327989 JP-A-5-284364 Japanese Patent Laid-Open No. 7-319799

  However, each processing unit does not have a dedicated line buffer 2400a to 2400d, and the image data read by each image reading device is stored in the intermediate buffers 2200-1 and 2200-2 and the processing in the image processing unit is individually performed. In an image processing apparatus that controls data processing by cutting out data in the main memory 2200 into a predetermined unit (for example, a rectangular shape) adapted to the image processing mode without the intervention of the line buffers 2200-1 and 2200-2, an intermediate buffer Since the unit of reading from 2200-1 and 2200-2 is a unit of multiple lines, performing buffer management on software may cause an increase in buffer memory or an increase in software processing load as well as use hardware performance. There was a problem that said no.

  In addition, there is a problem that it is necessary to increase the number of intermediate buffers depending on the processing capability of hardware. An increase in the capacity of the intermediate buffer increases the cost burden and hinders cost reduction of the entire image processing apparatus.

  Further, even in the case of configuring an arbitration circuit that monitors the intermediate buffer in units of lines in order to reduce the software load, it cannot cope with the case where the input / output data units are rectangular.

  The present invention has been made in order to solve the above-described problems. The object of the present invention is to secure an intermediate buffer that is secured in a main memory and temporarily stores processing data, and is arranged in the preceding stage of the intermediate buffer. A first image processing block for processing input image data in a unit of a predetermined rectangular shape to generate input data to the intermediate buffer, and processing the data read from the intermediate buffer, which is arranged after the intermediate buffer In the image processing apparatus including the second image processing block, the amount of staying data on the intermediate buffer is monitored, and data writing processing for each predetermined rectangular shape unit on the intermediate buffer by the DMAC based on the amount of staying data Or a rectangular unit that can be secured by adapting the conditions such as the set image processing mode by arbitrating the data reading process By securing an intermediate buffer and optimizing the size of the intermediate buffer between each block according to the processing content and capability, it reduces the burden of buffer management processing when processing image data in units of a predetermined rectangular shape and efficiently performs image processing. An inexpensive image processing apparatus, image processing method, and storage medium storing a computer-readable program and a program are provided.

  According to a first aspect of the present invention, a writing unit (image processing DMAC 91 shown in FIG. 1) that sequentially writes the image data input by the image input unit in a memory along the main scanning direction, and the writing unit. Determining means for determining whether or not the image data written in the memory has been accumulated for a predetermined sub-scanning width; and dividing the image data written in the memory by a predetermined main scanning width in the main scanning direction; Reading means (image processing DMAC 91 shown in FIG. 1) for reading out the image data in order to output the image data from the memory to the image processing means in units of a rectangular shape having the main scanning width and the predetermined sub-scanning width; and the memory Based on whether the amount of image data stored in the image can be read out in the rectangular shape, the reading means reads out the rectangular shape. Characterized in that it has an arbitration unit for stop (buffer arbitration unit 77 shown in FIG. 1).

  According to a second aspect of the present invention, there is provided a counting means for counting the amount of the image data stored in the memory, and the writing means writes the image data for one line in the main scanning direction each time the image data is written. The counting means counts up, and the reading means subtracts a predetermined number every time one line is read in the main scanning direction for each rectangular unit.

  According to a third aspect of the present invention, there is provided storage means for temporarily storing the image data input by the image input means according to the input method of the image input means, and the writing means is stored in the storage means. The stored image data is written into the memory according to the input method of the image input means, and the reading means reads out regardless of the input method of the image input means.

  According to a fourth aspect of the present invention, the arbitration unit includes a remaining amount detection unit, and when the memory is full, outputs a stop signal to the writing unit and stops the operation on the writing side. It is characterized by letting.

  According to a fifth aspect of the present invention, the arbitration unit includes a trigger generation unit, and when the predetermined number of lines of data corresponding to a predetermined processing line unit on the reading side is accumulated in the memory, the reading unit A start signal is output to start reading control.

  A sixth aspect of the present invention is characterized in that the predetermined rectangular shape unit can be set to a variable amount based on an image processing mode.

  A seventh invention according to the present invention is characterized in that the writing means can connect a plurality of types of image reading devices.

  According to an eighth aspect of the present invention, there is provided a writing step of sequentially writing the image data input by the image input means in the main scanning direction into the memory, and the image data written in the memory by the writing step. Determining whether or not a predetermined sub-scanning width has been accumulated, and dividing the image data written in the memory by a predetermined main scanning width in the main scanning direction, so that the predetermined main scanning width and the predetermined sub-scanning width are divided. A reading step of reading out the image data in order to output the image data from the memory to the image processing means in a rectangular shape unit comprising a scanning width, and the amount of the image data stored in the memory can be read out in the rectangular shape. An arbitration step (step S33 shown in FIG. 26) for arbitrating to read out the rectangular shape by the reading means based on whether or not Characterized in that it has.

  According to a ninth aspect of the present invention, a program for realizing the image processing method of the eighth aspect is stored in a computer-readable storage medium.

A tenth aspect of the present invention is a program for realizing the image processing method of the eighth aspect.

  According to the present invention, an intermediate buffer that is secured in the main memory and temporarily retains processing data, and is arranged in the preceding stage of the intermediate buffer, and processes input image data in a predetermined rectangular shape unit to the intermediate buffer. In an image processing apparatus comprising: a first image processing block that generates input data of a second image processing block; and a second image processing block that is arranged downstream of the intermediate buffer and processes data read from the intermediate buffer. The amount of staying data is monitored, and based on the amount of staying data, the data writing process or data reading process for each predetermined rectangular shape unit on the intermediate buffer by the DMAC is arbitrated, thereby setting the image processing mode etc. Secure an intermediate buffer of rectangular units to be secured according to the conditions, and save the intermediate buffer between each block. Optimized according to size as the process type and capacity, an effect capable of performing efficient image processing to reduce the buffer management processing load at the time of image data processing in a predetermined rectangular units.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus showing an embodiment of the present invention.

  In FIG. 1, reference numeral 10 denotes a scanner interface (hereinafter referred to as “scanner I / F”) unit, which is connected to a CCD 17 and a CIS 18 via an analog front end (AFE) 15 without interposing dedicated dedicated circuits. The read data can be taken into the image processing apparatus 200. Data processing of the scanner I / F unit 10 will be described in detail later.

  Reference numeral 20 denotes a scanner image processing unit. The image data developed in the main memory 100 by the processing of the scanner I / F unit 10 is set in an image processing operation mode (color copy, monochrome copy, color scan, monochrome scan, etc.). It is a processing unit that executes corresponding image processing. Details of the scanner image processing unit 20 will be described later.

  When the data transfer between the scanner I / F unit 10 and the scanner image processing unit 20 is performed via the ring buffer area on the main memory 100, the buffer arbitration unit 77 arbitrates data writing and reading as described later. .

  The printer image processing unit 30 is a processing unit for performing region editing and resolution conversion of an input image, and outputting the obtained image data to a printer. Reference numeral 40 denotes a laser beam printer (LBP) 45 to be connected. It is an LBP interface (I / F) unit for outputting a result.

  When the data transfer between the printer image processing unit 30 and the LBP interface unit 40 is performed via the ring buffer area on the main memory 100, the buffer arbitration unit 78 arbitrates data writing and reading as described later. The buffer arbitration units 77 and 78 have the same basic configuration, but the control method differs depending on the application to be used. Details will be described later.

  Reference numerals 50 and 60 denote JPEG and JBIG modules, which are processing units for executing image data compression / decompression processing conforming to a predetermined standard.

  Reference numeral 70 denotes a memory control unit, which is connected to the first BUS 83 and second BUS 84 of the image processing system and the third BUS 85 of the computer system, and performs data transfer control for writing / reading data to / from the main memory (SDRAM) 100.

  Reference numeral 90 denotes a DMA controller (DMAC), which is connected to the ROM 95 via the ROMISA 97 in cooperation with the memory control unit 70, and relates to data exchange between the external device and various interface units 170 and the main memory 100. Predetermined address information for DMA control is generated or set.

  Reference numeral 91 denotes a DMA controller (image processing DMAC), which cooperates with the memory control unit 70 to perform DMA control regarding data exchange between each image processing unit (10, 20, 30, 40) and the main memory 100. Predetermined address information is generated or set.

  For example, according to the type of image reading device, CCD 17 and CIS 18, address information for DMA transfer of image data read by the scanner I / F unit 10 to the main memory 100 is generated for each DMA channel. Alternatively, the address information for reading out the image data developed on the main memory 100 is generated according to the DMA channel and DMA-transferred to the scanner image processing unit 20. 20, 30, 40) and the main memory 100 function as a unit that manages the DMA control together with the memory control unit 70.

  The ROM 95 stores appropriate control parameters and control program data according to the image reading device (CCD 17 and CIS 18), and various control parameters can be set according to the image reading device. Since it is possible to input image data in accordance with the individual data output format, it is not necessary to provide a dedicated interface circuit.

  Reference numeral 83 denotes a first BUS, which is configured to transmit data read from the main memory 100 to each processing unit (10 to 60) of the image processing system. Reference numeral 84 denotes a second BUS, which can send data read from each processing unit (10 to 60) of the image processing system to the main memory 100. The first BUS 83 and the second BUS 84 are paired with the image processing block and the main. Transfer image data between the memories 100. Reference numeral 85 denotes a third BUS, which functions as a computer system bus to which the CPU 180, the communication and interface unit 170, the mechatronic system control unit 125, the control register in the image processing unit, and the DMAC 90 are connected.

  The mechatronics system control unit 125 includes a motor control unit 110 and an interrupt timer control unit 120 that controls timing for controlling motor drive timing and image processing system processing.

  The LCD control unit 130 is a unit that controls display for displaying various settings, processing statuses, and the like of the image processing apparatus on the LCD 135. Reference numerals 140 and 150 denote USB interface units that enable connection with peripheral devices. FIG. 1 shows a state in which the BJ-printer 175 is connected.

  Reference numeral 160 denotes a media access control (MAC) unit that controls at what timing (access) data should be sent to a connected device. A CPU 180 controls the overall operation of the image processing apparatus 200. Reference numeral 93 denotes a modem (MODEM).

<Configuration of Scanner I / F Unit 10>
The scanner I / F unit 10 can correspond to the CCD 17 and the CIS 18 as image reading devices, and inputs signals of both image reading devices. The image data input here is DMA-transferred by the memory control unit 70 and developed on the main memory 100.

  2 is a block diagram showing a schematic configuration of the scanner I / F unit 10 shown in FIG. 1, and the same components as those in FIG. 1 are denoted by the same reference numerals.

  In FIG. 2, for the CCD 17 / CIS 18, the timing control section 11a generates and outputs a reading device control signal corresponding to the reading speed. This device control signal is synchronized with a synchronization signal generated in the scanner I / F unit 10, whereby the reading timing in the main scanning direction and the reading process can be synchronized.

  The LED lighting control unit 11b is a unit that controls the lighting of the LED 19 serving as the light source of the CCD 17 / CIS 18, and is a synchronization signal (TG, SP, FIG. 5) for controlling the sequential lighting of LEDs corresponding to the R, G, and B color elements. 3, refer to FIG. 4), clock signal (CLK, refer to FIG. 4, etc.) and dimming control corresponding to the CCD 17 / CIS 18, start of lighting, and extinction control. This control timing is based on the synchronization signal received from the above-described timing control unit 11a, and the lighting of the LED 19 synchronized with the driving of the image reading device is controlled.

  FIG. 3 is a timing chart for explaining an example of an output signal from the CCD 17 shown in FIG.

  As shown in FIG. 2, the light emitted from the LED 19 illuminates the document surface, and the reflected light is guided to the CCD 17 for photoelectric conversion. For example, the original surface is sequentially scanned for each line in the main scanning direction while moving the reading position at a constant speed in the direction perpendicular to the line direction of the CCD 17 that is the main scanning direction (sub-scanning direction). Can be read.

  As shown in FIG. 3, based on the synchronization signal (TG) output from the timing controller 11a, signals corresponding to the R, G, B elements for one line of the CCD 17 are output in parallel (FIG. 3B). , (C), (d)).

  FIG. 4 is a timing chart relating to the lighting control of the LED 19 with respect to the CIS 18 shown in FIG. 2, and based on the synchronization signal (SP) and the clock (CLK) generated by the LED lighting control unit 11b, each R, G, B The timing for starting and turning off the LED is controlled.

  In FIG. 4, the period of the synchronization signal (SP) is indicated by Tstg, and the lighting of the LED is controlled by any one of these colors (R, G, B) or a combination thereof within this time. Tled indicates the lighting time of the LED in one cycle (Tstg) of the synchronization signal (SP).

  FIG. 5 shows a photoelectrical operation based on the lighting of the LEDs corresponding to R, G, and B ((a) to (d)) and the reflected light of the LED accumulated during the lighting time according to the timing chart shown in FIG. It is a timing chart which shows the relationship with the output (e) converted.

  As is clear from the output (e) of FIG. 5, the output of the signals corresponding to the R, G, and B colors is output as R data, G output, and B output, respectively, as serial data. This is different from the output signal of the CCD 17.

  FIG. 6 is a timing chart for explaining the LED lighting control operation shown in FIG. 2. In relation to the control of the CIS 18, each of the R, G, B LEDs 19 is within one cycle of the synchronization signal (SP). It is an example of a timing chart which shows the timing in the case of turning on sequentially, The input of the image reading device in this case can be taken in into the image processing apparatus 200 as monochrome image data by the synthesis | combination of R, G, B data.

  FIG. 7 is a timing chart showing an output example when the CIS 18 shown in FIG. 2 is provided with two channels in the main scanning direction.

  As shown in FIG. 7, the output of channel 1 ((c) in FIG. 7) is synchronized with the falling edge of the Nth CLK signal (see (b) in FIG. 7) in any dummy bit string ( In the case of FIG. 7, 22 bits) are output, and then a signal for the number of effective bits of 3254 bits is output ((c) of FIG. 7). On the other hand, the output of channel 2 ((d) in FIG. 7) is synchronized with the falling edge of the Nth CLK signal from the valid bit 3255th bit (the bit following the last bit 3254 of the sensor output of channel 1). 2794 bits are output as valid bits.

  The data for one line in the main scanning direction can be divided and read by the sensor outputs of the two channels. Note that the configuration of the CIS is not limited to a maximum of 2 channels. For example, even if the configuration is a 3 channel, only the number of outputs of the number of effective bits changes, and the gist of the present invention is not limited.

  Returning to the block diagram shown in FIG. 2, the output signal of the image reading device (CCD 17 / CIS 18) is input to an AFE (analog front end) 15.

  FIG. 8 is a block diagram for explaining the configuration of the AFE 15 shown in FIG. 2, and the same components as those in FIG. 2 are denoted by the same reference numerals.

  As shown in FIG. 8, the AFE 15 performs gain adjustment (15a, 15d) and A / D conversion processing (15b, 15c, 15e) on the output signals of the CCD 17 and CIS 18, and further performs inter-line correction processing. The analog signal output from each image reading device 15c is converted into a digital signal and input to the scanner I / F unit 10. The AFE 15 can convert parallel data output from the image reading device into serial data and output the serial data.

  The synchronization control unit 11c in FIG. 2 sets a predetermined threshold level for the AFE 15 according to the analog signal of each device (17, 18), and adjusts the output signal level according to the difference in the image reading device. Further, a sampling clock for analog signals and a synchronous clock for outputting a digital signal to the AFE 15 are generated and output, and read image data by a predetermined digital signal is received from the AFE 15. This data is input to the output data control unit 11d via the synchronization control unit 11c. The output data control unit 11d buffers the image data received from the AFE 15 in accordance with the output mode of the scanner I / F unit 10 (11e , 11f, 11g).

  The output mode of the scanner I / F unit 10 can be switched between a single mode, a 2-channel (ch) mode, and a 3-channel (ch) mode, depending on the image reading device to be connected.

  The single mode is a mode selected when main scanning direction data is serially input from the AFE 15, and in this case, only one buffer is available.

  The 2ch mode is a mode selected when data input from the AFE 15 is input at the same timing as information for two channels of the image reading device. In this case, two buffers (for example, 11e, 11f) is set to an available state.

  The 3ch mode is a mode that is selected when image data received from the AFE 15 is input at the same timing as R, G, and B outputs. In this case, three buffers (11e, 11f, and 11g) are provided. Set to available state.

  When color image data is read by the CIS 18 in the single mode, the data received from the AFE 15 is serially output as R, G, B data according to the lighting order of the LEDs as shown in FIG. The output data control unit 11d stores the data in one buffer (for example, the first buffer 11e) according to this arrangement. The same applies when monochrome image data is read by the CIS 18, and the monochrome image data is stored in one buffer.

  When the color image data is read by the 2-channel CIS 18, the above-described 2ch mode is set. As shown in FIGS. 7C and 7D, the data received from the AFE 15 is data for each area divided into two in the main scanning direction. In order to store the data for each area, the output data control unit 11d stores the received data in two buffers (for example, the first buffer 11e and the second buffer 11f). This process is the same even when monochrome image data is read by the CIS2 channel.

  When the color image data is read by the CCD 17, the output data control unit 11d receives the data received from the AFE 15 in three buffers (first, second, and third buffers) for each of R, G, and B data in the above-described 3ch mode. 11e, 11f, and 11g).

<Configuration of Memory Control Unit 70>
Next, a description will be given of a process in which the image data stored in the predetermined buffer (11e, 11f, 11g) is DMA-transferred to the main memory (SDRAM) 100 and stored by the process of the scanner I / F unit 10. The process of transferring the image data to the main memory 100 by DMA transfer is controlled by the I / O control unit 71 of the image processing DMAC 91.

  FIG. 9 is a block diagram for explaining a schematic configuration of the image processing DMAC (DMAC) 91 shown in FIG. 1, and the connection of the buffer arbitration unit 77 shown in FIG. 1 and the image reading devices (17, 18). This corresponds to a diagram illustrating a relationship between the main memory (SDRAM) 100 storing the read image data and a connection relationship between the printer image processing unit 30 and the buffer arbitration unit 78.

  The DMAC 91 controls transfer of data between the main memory 100 and the scanner image processing unit 20, an I / O control unit 71 that DMA-transfers image data input by the scanner I / F unit 10 to the main memory 100. An I / P control unit 73 is included. Data exchange between the I / O control unit 71 and the I / P control unit 72 is performed via an intermediate buffer on the main memory 100. When this intermediate buffer is used as a ring buffer, a buffer arbitration unit 77 for arbitrating data writing and reading is used.

<Configuration of I / O control unit 71>
Here, the I / O control unit 71 includes a data arbitration unit 71a, a first write data interface (I / F) unit 71b, and an I / O interface unit 71c.

  The I / O interface unit 71c sets predetermined address information generated by the above-described DMAC 91 to store data in the main memory 100 in the first write data I / F unit 71b. Further, the image data output from the scanner I / F unit 10 is received, and the data is stored in each buffer channel (hereinafter referred to as “channel”) (ch0 to ch2) in the I / O control unit 71.

  The first write data I / F unit 71b is connected to the first BUS 83 for writing data to the main memory 100, and the data stored in each channel (ch0 to ch2) according to the generated predetermined address information. Are transferred to the main memory 100 by DMA. The data arbitration unit 71a reads the data stored in each channel, and transfers the data of each channel in accordance with the writing process of the first write data I / F unit 71b.

  The first write data I / F unit 71b is connected to the buffer arbitration unit 77, and is controlled so that memory access does not compete with data read or write by the I / P control unit 72 described later. Even when the main memory 100 is used as a ring buffer by controlling access to the main memory 100, data is overwritten to the same memory address before the data stored in the main memory 100 is read. Troubles can be prevented and memory resources can be used effectively.

  FIG. 10 is a block diagram for explaining the schematic configuration of the buffer arbitration units 77 and 78 shown in FIG.

  As shown in FIG. 10, the buffer arbitration unit 77 detects the control register 771, the read update detection unit 773 that detects the transfer completion signal Read_end signal from the read side DMAC channel, and the transfer completion signal Write_end signal from the write side DMAC channel. And a DMAC control signal generator 775 that generates a control signal to the DMAC 91 according to the number of staying lines.

  Each of the channels ch0 to ch2 in the I / O control unit 71 has a function of generating a transfer completion signal for each dimension, and the transfer completion signal Write_end1-3 is connected to a one-dimensional (hereinafter referred to as line) transfer end signal. Has been. That is, when transfer for one line in the main scanning direction is detected, a transfer completion signal Write_end1-3 is output. The write update detection unit 772 detects the end of all the used channels by permitting the input according to the actually used channel among the transfer end signals of the three channels to be connected.

  As described above with reference to FIGS. 8, 9, and 10, data is written into the main memory 100 in accordance with the image reading device (CCD17 / CIS18) and the output mode (single mode, two-channel mode, and three-channel mode) of the image reading device. Since the image data writing method is selected, the scanner image processing unit 20 side can read the image data from the main memory regardless of the image reading device or the output mode of the image reading device, and has a simple configuration. Compatible with various reading devices and reading methods.

  FIG. 11 is a timing chart for explaining the operation of the buffer arbitration units 77 and 78 and the DMAC 91 shown in FIG. 10, and (a) and (b) of FIG. It is a timing chart in the case. In FIG. 11A, the buffer arbitration unit 78 generates a count_up signal when the end of one channel is detected and the count value of the stay counter 774 is updated, whereas in FIG. 11B, the buffer arbitration unit 77 is updated. However, the count value is not updated until the end of the two channels.

  FIG. 11A shows arbitration of writing to the ring buffer for printing. Further, the suspend signal in FIG. 11A determines that the print buffer is FULL when the RING_LINE value corresponding to the ring buffer set in the control register 771 matches the number of stays, and the printer image This is a temporary stop signal for stopping the write side DMAC from the processing unit, and the I / O control unit 71 stops the write transfer to the intermediate buffer 1 while this signal is asserted.

  FIG. 11B shows the writing of image data from the scanner interface unit 10. Each time the output of the transfer completion signal Write_end2 in FIG. 11B, that is, writing of one line of image data in the main scanning direction is completed, the staying number is added. The TRIGGER signal is a pulse signal generated when the number of stays matches the TRIGGER_LINE value corresponding to the stripe width set in the control register 771. The transfer data is set in advance, and the waiting I / P control unit 72 When this pulse signal is received, data transfer processing to the scanner image processing unit is started.

  Each of the channels ch3 to ch6 in the I / P control unit 72 has a function of generating a transfer completion signal for each dimension, and the transfer completion signals Read_end1-4 are three-dimensional (hereinafter referred to as stripe regions) transfer end signals. It is connected. The read update detection unit 773 in the buffer arbitration unit 77 detects the end of all used channels by permitting input according to the channel actually used among the transfer end signals of the connected four channels. .

  FIG. 11C is a timing chart when 1 and 2 channels of the buffer arbitration units 77 and 78 are enabled. FIG. 11C shows the buffer arbitration unit 77 in FIG. In this case, the count_down signal is generated by detecting the end of one channel, that is, the end of reading for the scanner image processing unit 20 for one stripe width, and the count value of the stay counter is updated (that is, the count value for one stripe is subtracted). ). For the buffer arbitration unit 78, the count value is updated every time one line of image data is read from the ring buffer to the printer unit, whereas FIG. 6 is a timing chart when output to the printer unit. This is an example in which there are two LBP laser beam generators (not shown) and the two laser beams are simultaneously turned on to print at high speed. In FIG. 11D, the count value of the ring buffer is not updated until the end of the two channels.

  In the suspend signal in FIG. 11D, the count value of the stay counter 774 is updated by the input of the count_down signal, and as a result, the state is shifted to the suspend release state.

  The I / O control unit 71 resumes the write transfer to the intermediate buffer 1 by releasing the suspend signal. The suspend generated by the buffer arbitration units 77 and 78 has a function of permitting / prohibiting the generation. The TRIGGER signal has three switching functions: permission, prohibition, and permission only when the first condition occurs.

  As described above, arbitration between the process of sequentially writing the image data from the scanner interface unit 10 in the main memory 100 along the main scanning direction and the process of reading out the rectangular data for processing by the scanner image processing unit 20 is simple. It can be carried out.

  In addition, the number of stays in the buffer is added for writing, and the number of stays is subtracted when reading is completed for each stripe, so that the necessary memory area can be reduced and arbitration can be easily performed.

  As shown in FIGS. 8, 9, and 10, when the image read by the scanner is stored in the main memory 100 for each color component and processed by the scan image processing unit 20, the same arbitration as described above is performed for each color. do it.

<(1) Storage of data for one channel>
FIG. 12 is a diagram for explaining a process in which the I / O control unit 71 shown in FIG. 10 writes data for one channel to the main memory (SDRAM) 100. FIG. 12A shows a color image for one channel. FIG. 12 (b) shows a process of writing monochrome image data by the CIS 18 obtained at the LED lighting timing shown in FIG. 5 (b). Show.

  As in the output example shown in FIG. 5E, R, G, and B data for one line in the main scanning direction are serially output, and one buffer (11e in FIG. 2) of the scanner I / F unit 10 is output. ), The data is transferred to one corresponding channel (ch0, see FIG. 9) in the I / O control unit 71.

  Here, in FIG. 12, FIG. 13, and FIG. 14, the configuration for storing the data of the channel (ch0) by the data arbitration unit 71a and the first write data I / F unit 71b is denoted as “first LDMAC”. The configuration for processing the data of the channel (ch1) is denoted as “second LDMAC”, and the configuration for processing the data of the channel (ch2) is denoted as “third LDMAC”.

  In the case where the process of storing color image data of one channel separately into R, G, and B data is performed, as shown in FIG. Among them, R data for one line (R1 to R2) in the main scanning direction is written in the R area 1000a of the main memory 100, and the write address is switched to the start address (G1) of the G area (1000b) which is the next writing area.

  Then, the first LDMAC writes the G data for one line (G1 to G2) in the main scanning direction among the R, G, and B data to the G area (1000b) of the main memory 100, and the next B area that is the next writing area The write address is switched to the start address (B1) of (1000c).

  The first LDMAC writes the B data for one line (B1 to B2) in the main scanning direction to the B area (1000c) of the main memory 100, and then the address is the leading address (R2) of the second line in the R area (1000a). ). Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control in which the first LDMAC writes data, the address of the memory that is the storage destination of data corresponding to the R data, G data, and B data is given as offset information (A, B), and the storage area for each color data is switched. Thus, the R, G, and B data in the line order can be stored in the main memory 100 separately from the R data, the G data, and the B data.

  The start address for starting DMA transfer (R1 in the case of FIG. 12A), offset information (A, B), and the like are due to the generation of the DMAC 90 described above.

  In this case, the buffer arbitration unit 77 uses the input to the write update detection unit 772 as valid only for the Wite_end signal of the first LDMAC (ch0). A Write_end signal is generated for each R, G, B line transfer, and the stay counter 774 counts up by 1. Therefore, the stay counter 774 counts up by 3 for the input of one color line. Therefore, the total number of lines allocated to each of R, G, and B data storage is set in the control register 771 as the RING_LINE value.

  When performing monochrome image data writing processing by the CIS 18 obtained at the LED lighting timing shown in FIG. 6, as shown in FIG. 12B, in the case of monochrome image data, for each of R, G, and B Since there is no need to separate the data, the line order monochrome image data is written for one line (M1 to M2) in the main scanning direction of the main memory 100, and the writing address is shifted in the sub-scanning direction of the area 1000d. Then, the data for the next second line (M3 to M4) is written. Thereafter, monochrome image data can be stored in the area 1000d of the main memory 100 by sequentially executing the same processing.

  In this case, the buffer arbitration unit 77 uses the input to the write update detection unit 772 as valid only for the Wite_end signal of the first LDMAC (ch0). A Write_end signal is generated for each monochrome line transfer, and the stay counter 774 counts up by one, so the stay counter 774 counts up by one for monochrome one line input. Therefore, the number of lines allocated to monochrome data storage is set in the control register 771 as the RING_LINE value.

<Data storage by 2-channel CIS>
FIG. 13 is a diagram for explaining a data storing process in the SDRAM 100 by the image processing DMAC 91 shown in FIG. 1. FIG. 13A shows two-channel color image data as R, G, as shown in FIG. This corresponds to a processing example of storing data separately into B data, and corresponds to a processing example of monochrome image data writing by CIS of two channels obtained at the lighting timing of the LED shown in FIG. The memory area in the main scanning direction is divided corresponding to two channels.

  Image data read by the two-channel CIS 18 (chip 0, chip 1) is stored in the two buffers (11e, 11f) of the scanner I / F unit 10, and is controlled by the I / O control unit 71. The data (11e, 11f) is transferred to the channels (ch0, ch1) in the control unit 71.

  The first LDMAC stores the data (chip0_data) of the channel (ch0) in the areas indicated as the first R area (1100a), the first G area (1200a), and the first B area (1300a) in FIG.

  In FIG. 13A, the first LDMAC writes R data (RA1 to RA2) out of R, G, and B data input from chip0 to the first R area (1100a) of the main memory, and the next writing area. The write address is switched to the first address (GA1) of the first G area (1200a) (offset information C).

  The first LDMAC writes G data (GA1 to GA2) among R, G, and B data to the first G area (1200a) of the main memory, and the first address (BA1) of the first B area (1300a) that is the next writing area. ) To switch the write address (offset information C).

  Then, the first LDMAC writes B data (BA1 to BA2) among the R, G, and B data to the B area (1300a) of the main memory, and after the processing is completed, the address is set in the sub-scanning direction of the R area (1100a). To the first address (RA2) of the second line (offset information D). Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  The first LDMAC has a data storage area for each of the areas indicated as the first R area (1100a), the first G area (1200a), and the first B area (1300a) in FIG. The memory address can be arbitrarily set based on the offset information (C, D), and the data stored in the channel (ch0) is stored in the main memory 100 according to the setting.

  The second LDMAC stores the data (chip1_data) of the channel (ch1) in the areas indicated as the second R area (1100b), the second G area (1200b), and the second B area (1300b) in FIG.

  In FIG. 13A, the second LDMAC writes R data (RB1 to RB2) among the R, G, and B data input from chip1 to the second R area (1100b) of the main memory, and the next writing area. The write address is switched to the start address (GB1) of the second G area (1200b) (offset information E).

  The second LDMAC writes G data (GB1 to GB2) among the R, G, and B data to the second G area (1200b) of the main memory 100, and the first address of the second B area (1300b) that is the next writing area ( The write address is switched to BB1) (offset information E).

  Then, the second LDMAC writes the B data (BB1 to BB2) among the R, G, and B data to the second B area (1300b) of the main memory 100, and after the processing is completed, the address is stored in the second R area (1100b). Switch to the first address (RA2) of the second line in the sub-scanning direction (offset information F). Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control in which the first and second LDMACs write data, the address of the memory serving as the data storage destination corresponding to the R data, G data, and B data is given as offset information (C, D, E, F), and each color data By switching the storage area for each line, the R, G, and B data in the line order can be separated from the R data, the G data, and the B data and stored in the main memory 100.

  The start address for starting DMA transfer (RA1, RB1 in the case of FIG. 12A), offset information (C, D, E, F), and the like are due to the generation of the DMAC 90 described above.

  In this case, the buffer arbitration unit 77 uses the input to the write update detection unit 772 as valid only for the Wite_end signals of the first LDMAC (ch0) and the second LDMAC (ch1). The first LDMAC and second LDMAC Write_end signals are generated for each R, G, B line transfer, and the stay counter 774 counts up by 1. Therefore, the stay counter 774 counts up by 3 for the input of one color line. Therefore, the total number of lines allocated to each of R, G, and B data storage is set in the control register 771 as the RING_LINE value.

  In the following, the writing process of monochrome image data by the 2-channel CIS obtained at the LED lighting timing shown in FIG. 6 will be described.

  As shown in FIG. 13B, in the case of monochrome image data, unlike the case of the color image data described above, it is not necessary to separate the data for each of R, G, and B. Is written for one line (MA1 to MA2, MB1 to MB2) in the main scanning direction of the main memory 100, and the write address is shifted in the subscanning direction of the same area (1400a, 1400b). Data of the line (MA3 to MA4, MB3 to MB4) is written. Thereafter, monochrome image data can be stored in the main memory area (1400a, 1400b) by sequentially performing the same processing.

  In this case, the buffer arbitration unit 77 uses the input to the write update detection unit 772 as valid only for the Wite_end signals of the first LDMAC (ch0) and the second LDMAC (ch1). The first LDMAC and second LDMAC Write_end signals are generated for each monochrome line transfer, and the stay counter 774 counts up by 1. Therefore, the stay counter 774 counts up by 1 for monochrome one line input. Therefore, the number of lines assigned to monochrome data storage is set in the control register 771 as the RING_LINE value.

<(3) Storage of 3 channel data>
FIG. 14 is a diagram for explaining an example of data writing processing by the image processing DMAC 91 shown in FIG. 1, and the image data read by the CCD 17 by the output data control unit 11d in the scanner I / F unit 10 shown in FIG. When three channels of data (R data, G data, and B data) are used, this corresponds to a processing example in which the first to third LDMACs write data to the main memory 100.

  Data stored in the three buffers (11e, 11f, and 11g shown in FIG. 2) is transferred to channels (ch0, ch1, and ch2) in the control unit 71 under the control of the I / O control unit 71. The The data transferred to ch0 is written to the main memory 100 by the first LDMAC, the data transferred to ch1 is written to the main memory 100 by the second LDMAC, and the data transferred to ch2 is Data is written to the main memory 100 by the third LDMAC.

  Each LDMAC writes data to areas corresponding to the R area (1500a), G area (1500b), and B area (1500c) of the main memory 100, thereby separating the R, G, and B data onto the main memory 100. Can be stored.

  In this case, the start address (SA1, SA2, SA3 in the case of FIG. 14) for starting the DMA transfer is due to the generation of the DMAC 90 described above.

  In this case, the buffer arbitration unit 77 uses the input to the write update detection unit 772 as valid only for the first LDMAC (ch0), second LDMAC (ch1), and third LDMAC (ch2) Wite_end signals. The Write_end signal of the first LDMAC, the second LDMAC, and the third LDMAC is generated for each R, G, B line transfer, and the stay counter 774 counts up by 1. Therefore, the stay counter 774 counts up by 1 for the input of one color line. . Accordingly, the control register 771 sets the number of lines allocated to each of R, G, and B data storage as the RING_LINE value.

  As described above, the image data read by the image reading device (CCD 17, CIS 18) is distributed to channels for controlling DMA transfer according to the output format, and address information and offset for controlling DMA with respect to the distributed data. By generating information, it is possible to cope with various image reading devices.

<Main memory area setting and DMA transfer>
In order to DMA transfer image data to the main memory 100, address information for the main memory 100 is set, and the I / O control unit 71 controls DMA transfer according to this address information.

  FIG. 15 is a diagram showing a state in which the main memory 100 shown in FIG. 1 is divided into predetermined rectangular areas (blocks). FIG. 15A shows the main memory 100 divided into predetermined rectangular areas (blocks). FIG. 15B corresponds to an example in which the main memory 100 is used as a ring buffer.

  As shown in FIG. 15, in order to perform image processing in units of rectangular areas on the image data stored in the main memory 100, rectangular areas are defined according to the image processing mode (copy mode or scanner mode). Address information is set. In FIG. 15A, SA indicates a start address of DMA, and an area in the main scanning direction (X-axis direction) is divided by a predetermined byte length (XA, XB). A region in the sub-scanning direction (Y-axis direction) is divided by a predetermined number of lines (YA, YB). When used as a ring buffer (FIG. 15B), the areas 101a and 101b shown with hatching are the same memory area.

  The DMA for the rectangular area (0, 0) starts from the start address SA, and when data for XA is transferred in the main scanning direction, it is offset data (OFF1A) as a transfer address shifted by one line in the sub-scanning direction. The indicated address is set. Similarly, when transfer in the main scanning direction and address shift by offset data (OFF1A) are controlled and DMA for the rectangular area (0, 0) is completed, the DMA shifts to DMA for the next rectangular area (1, 0).

  The DMA for the rectangular area (1, 0) jumps to the address indicated by the offset address (OFF2A). Hereinafter, similarly to the rectangular area (0, 0), transfer in the main scanning direction and offset data (OFF1A). When the address shift by is controlled and DMA for the rectangular area (1, 0) is completed, the process proceeds to the next rectangular area (2, 0). Similarly, when the DMA for the YA line is completed up to the area (n, 0), the next DMA is jumped to the address indicated by the offset data (OFF3), and the process proceeds to the process for the rectangular area (0, 1). . Similarly, the DMA for the areas (1, 1), (2, 1). For example, when the size of the rectangular area differs depending on the memory capacity (when defined by XB and YB), offset data (OFF1B, OFF2B) corresponding to the area size is further set to control the DMA.

  The rectangular area described above is a pixel and sub-pixel in the main scanning direction as an overlapping area between the rectangular areas due to the resolution in the main scanning direction according to the set image processing mode and the pixel area to be referred to. The number of lines in the scanning direction is set, and the allocation (division) of image data developed on the memory is controlled.

<Specific example>
FIG. 16 is a diagram illustrating capacity required for the main memory 100 shown in FIG. 1 for each image processing mode, and is set as follows according to each processing mode.

  16A corresponds to the case of the color copy mode. Effective pixels: 600 dpi in the main scanning direction, character determination (ZSG) processing: upper and lower 11 lines, left 12 pixels, right 13 pixels, color determination filtering (NSF) ) Processing: Upper and lower 2 lines, left 2 pixels, right 3 pixels, scaling processing: lower 1 line.

  (B) in FIG. 16 corresponds to the case of the monochrome copy mode. Effective pixels: 600 dpi in the main scanning direction, color determination filtering (NSF) processing: upper and lower 2 lines, left and right 2 pixels, scaling processing: lower 1 line It is an example.

  FIG. 16C corresponds to the case of the color scan mode mode, and is an example of effective pixels: 1200 dpi in the main scanning direction and scaling processing: the lower one line.

  Further, the setting of the glue amount affects not only memory resources but also transfer efficiency between the main memory 100 and the scanner image processing unit 20. The transfer efficiency is defined as the area ratio of the effective pixel area to the image area including the margin area, and as described above, in the copy mode, since the margin area is indispensable, the transfer efficiency is low. In the scanner mode, the transfer efficiency is high because there is no margin for excluding scaling processing.

  For example, in the case of the color copy mode shown in FIG. 16A, if the rectangular area including the margin area is 283 pixels × 49 lines, the maximum margin area (character determination processing (ZSG)) is subtracted. The effective area is 256 pixels × 24 lines, and the transfer efficiency is (256 pixels × 24 lines) / (283 pixels × 49 lines) ≈44%.

  On the other hand, in the color scan mode shown in FIG. 16C, if the scaling process is not performed, there is no margin and the transfer efficiency is 100%.

  Since the contents of the image processing differ between the scanner mode and the copy mode, the necessary memory area is appropriately set according to the processing contents. For example, as shown in FIG. 16, since character determination (ZSG) processing and color determination filtering (NSF) processing are required in the color copy mode, a margin amount for extracting an effective pixel region (in the drawing, effective pixels) However, since it is necessary to secure a resolution of about 600 dpi as the number of effective pixels in the main scanning direction, the margin area is determined by a trade-off with the memory area.

  On the other hand, in the scan mode, it is not necessary to secure the amount of paste except for the scaling process, but it is necessary to secure about 1200 dpi as the number of effective pixels in the main scanning direction. Therefore, when the memory allocation amount is approximately the same in the scan mode and the copy mode, if the number of lines in the sub-scanning direction is, for example, 24 lines, the main memory allocation amount in the color copy mode and the scan mode can be reduced. It can be about the same. Hereinafter, the flow of storage processing for each image processing mode will be described with reference to FIGS.

<Storage processing in copy mode>
FIG. 17 is a flowchart showing an example of a first data processing procedure in the image processing apparatus according to the present invention, and corresponds to, for example, a data storage processing procedure in the copy mode. S11 to S18 indicate each step.

  First, in step S11, it is determined whether or not the copy mode is color. If it is determined that the copy mode is color (YES in step S11), the process proceeds to step S12 to perform DMA transfer in the color copy mode. Set the address information as follows.

  In the case of writing including the margin of (a) in FIG. 16, an effective pixel (for example, resolution 600 dpi in the main scanning direction) is secured from the top of the buffer, and the margin (upper and lower 11 lines, left 12 pixels) is also provided in the periphery. , 13 pixels on the right) are set (see (a) of FIG. 16).

On the other hand, when writing only effective pixels (b) in FIG.
Start address (SA) = Memory top address (BUFTOP) + Number of pixels in the main scanning direction (TOTALWIDTH) x 11 (sub scanning margin (upper) in the sub scanning direction) + 12 (main scanning direction) Norihiro (left)).

In addition, (TOTALWIDTH = number of effective main scanning pixels (IMAGEWIDTH) of one page image + number of left margin pixels + number of right margin pixels)
UA = memory end address (BUFFBOTTOM) + 1 = ring buffer return address and OFF1A = TOTALWIDTH-IMAGEWIDTH.

  On the other hand, if it is determined in step (11) that the image is monochrome, the process proceeds to step S13, and the address information for DMA transfer in the monochrome copy mode is set as follows.

  When writing including a margin as shown in FIG. 16A, an effective pixel (for example, resolution 600 dpi in the main scanning direction) is secured from the head of the buffer, and a margin (upper and lower two lines) is provided in the periphery. , Left and right 2 pixels) are set (see FIG. 16B).

  When writing only effective pixels in FIG. 16B, start address (SA) = start address of memory (BUFTOP) + number of pixels in the main scanning direction of the one-page image including the margin (TOTALWIDTH) × 2 (sub- The margin in the scanning direction (top) +2 (the margin in the main scanning direction (left)), UA = memory end address (BUFFBOTTOM) +1, and OFF1A = TOTALWIDTH-IMAGEWIDTH.

  When address information for DMA transfer is set in steps S12 and S13 as described above, the process proceeds to step S14, and data transfer is started.

  Next, in step S15, the data stored in each channel in the I / O control unit 71 is sequentially read and DMA-transferred according to predetermined address information. When the data stored in the channels (ch0 to ch2) has been written (S16), the reading is finished (S17), the DMA transfer is finished (S18), and the processing is finished.

<Storage process in scanner mode>
FIG. 18 is a flowchart showing an example of a second data processing procedure in the image processing apparatus according to the present invention, and corresponds to, for example, a data storage processing procedure in the scanner mode. S21 to S26 indicate each step.

  First, in step S21, address information for DMA transfer in the scanner mode is set as follows.

  As shown in FIG. 16A, when writing including a margin, an effective pixel (for example, resolution of 1200 dpi in the main scanning direction) is secured from the top of the buffer, and further, the lower one line in the sub scanning direction is secured. A margin is set (see (c) of FIG. 16).

  As shown in FIG. 16B, when only valid pixels are written, start address (SA) = start address of memory (BUFTOP), UA = end address of memory (BUFFBOTTOM) + 1 = folding address of ring buffer And OFF1A = 0 (TOTALWIDTH = IMAGEWIDTH).

  When the address information is set in step S21, DMA transfer starts in step S22. The data stored in each channel in the I / O control unit 71 is read sequentially (S23) and DMA-transferred according to predetermined address information. When the data stored in the channels (ch0 to ch2) has been written (S24), the reading is finished (S25), the DMA transfer is finished (S26), and the process is finished.

  As described above, the image data is developed in the main memory 100 according to the set processing mode by the processing of FIGS. 17 and 18. 17 and 18 are parameters that can be arbitrarily set, and the gist of the present invention is not limited by these conditions.

<Reading data>
The image data developed in the main memory 100 is loaded into the scanner image processing unit 20 as corresponding R, G, B data or monochrome image data for each predetermined rectangular area, and image processing is performed for each rectangular area. Executed. In order to perform image processing for each rectangular area, the CPU 180 stores in the main memory 100 shading (SHD) correction data for correcting variations in sensitivity of the light receiving elements of the image reading device (CCD 17 / CIS 18), variations in the amount of light of the LEDs 19, and the like. The shading data of the rectangular area and the image data of the rectangular area are DMA-transferred to the scanner image processing unit 20 by the I / P control unit 72 described later.

  FIG. 19 is a diagram for explaining data read processing in the image processing apparatus according to the present invention. Data read processing when image data in a rectangular area is transferred to the block buffer RAM 210 (FIG. 21) of the scanner image processing unit 20. Corresponds to the example.

  In FIG. 19, with respect to the area (0, 0), the margin area AB1CD1 is set for the effective pixel area (abcd) ((a) of FIG. 19), and image data reading starts A. Corresponding data is read up to the main scanning direction B1 address as the address.

  When the reading of the data in the main scanning direction is completed, the address of the data to be read next is moved to the A2 address in the figure shifted by one line in the sub-scanning direction, and the data reaches the B3 address pixel in the main scanning direction. Read out. In the same manner, data is read out, and data in the main scanning direction from the C address corresponding to the last line in the margin area is read in the main scanning direction, and the reading of data in the area (0, 0) is completed. .

  For the area (0, 1), the margin area B2ED2F is set for the effective pixel area (bedf) ((b) of FIG. 19), and image data is read using B2 as the start address. Data to be read is read up to the E address in the main scanning direction. When the reading of the data in the main scanning direction is completed, the address of the next data to be read is moved to the B4 address in the figure shifted by one line in the sub-scanning direction, and the data is read up to the pixel at the B5 address in the main scanning direction.

  Then, the image data in the main scanning direction from the D2 address to the F address corresponding to the last line in the margin area is read, and the reading of the data in the second area is completed. Through the above processing, the data of the rectangular area including the margin area is read out. Thereafter, the same processing is performed for each rectangular area.

<Configuration of I / P control unit 72>
Reading of data stored in the main memory 100 is controlled by the I / P control unit 72 in the image processing DMA 91 in FIG. The first read data I / F unit 72a is connected to the main memory 100 via the second BUS 74 for reading data, and the first read data I / F unit 72a refers to the address information generated by the DMAC 91, Predetermined image data can be read from the main memory 100.

  The read data is set to a plurality of predetermined channels (ch3 to ch6) by the data setting unit 72b. For example, image data for shading correction is channel 3 (ch3), frame sequential R data is channel 4 (ch4), frame sequential G data is channel 5 (ch5), and frame sequential B data is channel 6 (ch6). Each data is set.

  Data set in each channel (ch3 to ch6) is sequentially DMA-transferred via the I / O interface 72c under the control of the I / P control unit 72, and the block buffer RAM 210 (scanner image processing unit 20). 21).

  The buffer arbitration unit 77 connects the read_end signals of ch3 to ch6 to the input to the read update detection unit 773. The effective setting corresponding to the channel to be used is performed in the same manner as the control in the update detection on the writing side. Channels used are all channels ch3 to ch6 during color processing. For monochrome, all channels ch3 to ch6 or ch3 and ch4 are used. The valid setting of the Read_end signal is switched according to the above setting.

  The Read_end signal is generated when the transfer of the area (stripe area) from (0, 0) to (n, 0) shown in FIG. When the Read_end signals for all the channels set as valid are input, a count_down signal is generated as shown in FIGS. 11C and 11D, and the subtraction preset in the control register 771 from the value of the stay counter 774 is performed. Subtract the value (DEC_VALUE). The value of DEC_VALUE varies depending on the operation mode. That is, when image data corresponding to stripe width × main scanning width is transferred to the scanner image processing unit 20, the stay counter is subtracted, so that the next image data can be written from the scanner interface unit 10.

  As the TRIGGER_LINE value, for example, a value corresponding to the stripe line on the reading side is set. If the TRIGGER_LINE value is misaligned in the sub-scanning direction between the R, G, and B outputs as in the color CCD, the intermediate buffer 101-1 needs to absorb this position difference, and the value is set to TRIGGER_LINE. It is necessary to add.

  As the RING_LINE value, for example, a value of stripe line +8 lines is set. This value should be changed according to the performance required for the system. Set the value of RING_LINE to be larger than TRIGGER_LINE.

  FIG. 20 is a diagram showing a setting example of DEC_VALUE, TRIGGER_LINE, and RING_LINE for each reading mode in the image processing apparatus according to the present invention.

  The setting shown in FIG. 20 is performed before the start of the reading operation. Even if the setting is not changed after the start, if only the setting of the DMAC 91 is updated, the management of the buffer and the activation control on the reading side can be continuously performed. I can do it.

  Channel 7 (ch7) is a channel for storing dot-sequential image data output from the scanner image processing unit 20 in order to store data subjected to predetermined image processing in the main memory 100. The scanner image processing unit 20 outputs address information (block end signal, line end signal) in accordance with the output of dot sequential image data, and based on this address information, the second write data I / F 72d is The image data stored in the channel 7 is stored in the main memory 100. The contents of this process will be described later in detail.

<Image processing>
FIG. 21 is a diagram for explaining an example of data processing in the image processing apparatus according to the present invention, is a block diagram for explaining a schematic configuration of the scanner image processing unit 20 shown in FIG. 1, and is loaded into the block buffer RAM 210. Processing corresponding to each image processing mode is performed on the processed data.

  FIG. 22 is a schematic diagram for explaining the size of a rectangular area required for each image processing in the image processing apparatus according to the present invention.

  The scanner image processing unit 20 executes processing by switching a rectangular pixel region to be referenced with respect to the rectangular region in accordance with the set image processing mode. The contents of the image processing will be described below with reference to FIG. 21, and the size of the rectangular area referred to during the processing will be described with reference to FIG.

  In FIG. 21, a shading correction block (SHD) 22 is a processing block for correcting variations in the light amount distribution of the light source (LED 19) in the main scanning direction, variations in light receiving elements of the image reading device, and dark output offset.

  The shading data stores correction data for one pixel in the order of bright R, bright G, bright B, dark R, dark G, and dark B on the main memory 100, and the number of pixels corresponding to the rectangular area ( X pixels are input in the main scanning direction, and Y pixels (see FIG. 22A) are input in the sub-scanning direction.

  The input frame sequential correction data is converted into dot sequential data by the input data processing unit 21 and stored in the block buffer RAM 210 of the scanner image processing unit 20. Then, when the shading data capturing of the rectangular area is completed, the process proceeds to image data transfer.

  The input data processing unit 21 is a processing unit that executes processing for reconstructing frame sequential data separated into R, G, and B into dot sequential data. One-pixel data is stored in the main memory 100 as frame-sequential data for each color of R, G, and B, and when these data are loaded into the block buffer RAM 210, the input data processing unit 21 One pixel data is taken out every time and reconstructed as R, G, B data of one pixel. Reconstruction processing is performed for each pixel, and frame sequential image data is converted to dot sequential data.

  FIG. 23 is a diagram for explaining an image processing region in the image processing apparatus according to the present invention. For example, a target region for image processing and a reference region (ABCD) for performing filter processing for executing the processing are schematically illustrated. Is shown.

  In FIG. 23, “Na” and “Nb” pixels are set as the margin amounts in the main scanning direction (X direction) for the effective pixel region (abcd), and the margin amounts in the sub scanning direction (Y direction). “Nc” and “Nd” pixels are set.

  FIG. 24 is a diagram exemplifying a margin for each image processing mode (color copy mode, monochrome copy mode, scanner mode) in the image processing apparatus according to the present invention. The reference area is larger than that at the same magnification only for pixels.

  In the color copy mode, the largest reference area is required in the image processing mode in order to determine black characters. In order to detect black characters, it is necessary to ensure the determination of halftone dots and black characters. Therefore, in order to determine the period of halftone dots, 26 pixels in the main scanning direction and 26 pixels in the sub-scanning direction (when zooming) are used. The reference area.

  In the monochrome copy mode, 5 pixels in the main scanning direction and 5 pixels in the sub-scanning direction (during zooming) are used as reference regions in order to perform edge enhancement on the character portion. In the scanner mode, necessary image processing is performed by a scanner driver or an application on the host computer. Therefore, a reference area is not required at the time of magnification, but a reference area is set for one pixel in the sub-scanning direction at the time of magnification. Needless to say, the gist of the present invention is not limited to the amount of glue shown here, and can be set arbitrarily.

  In the processing block 23 shown in FIG. 21, the averaging processing unit (SUBS) is a processing block that performs sub-sampling (simple decimation) for reducing the reading resolution in the main scanning direction or averaging processing, and an input masking processing unit. (INPMSK) is a processing block that calculates color correction of input R, G, and B data. The γ correction processing unit (LUT) is a processing block that gives predetermined gradation characteristics to input data.

  The character determination processing (ZSG) block 24 is a processing block that performs black character determination and line drawing contour pixel determination on input image data. In the black character discrimination process, since it is necessary to refer to an area wider than the halftone dot period as described above, it is desirable to refer to a margin area corresponding to 26 pixels (lines) in the main scanning direction and 26 pixels (lines) in the sub scanning direction. . Similar to the input of the shading correction block (SHD) 22, the input data of the character determination processing block (ZSG) 24 is the XA pixel in the main scanning direction (effective pixel + replacement) × the YA pixel in the sub-scanning direction (effective pixel + replacement). The data (FIG. 22A) is referred to.

  In the processing block 25, the MTF correction processing unit is a processing unit that performs filter processing in the main scanning direction for MTF difference correction and moiré reduction at the time of zooming when the image reading device is changed. On the other hand, this is a block for multiplying and adding each coefficient for a predetermined pixel in the main scanning direction.

  In FIG. 22B, the left hatched part (b1) 2 pixels and the right hatched part (b2) 3 pixels are secured for the attention area G1, and the process for the area G1 is executed.

  The (RGB → (L, Ca, Cb)) conversion processing unit (CTRN) performs R, G, and B colors for filtering (brightness enhancement, saturation enhancement, color determination) performed in the subsequent filter processing (NSF) block 26. The multivalued image data is converted.

  The background density correction processing unit (ABC) automatically recognizes the background density of the document and corrects the background density value to the white side to execute binarized data suitable for facsimile communication or the like.

  The filter processing (NSF) block 26 performs edge strength processing and saturation (Ca, Ca) of the lightness component (L) of the image as processing for performing color determination and filtering on the obtained data in the previous CTRN processing. The enhancement process of Cb) is performed. Further, the color determination of the input image is performed and the result is output. Further, the emphasis amount parameter can be changed based on the character generated in the character determination processing (ZSG) block 24, the determination signal of the line drawing outline portion, and the like. The data after the filter process (NSF) is converted from L, Ca, Cb to R, G, B data and output. This processing block functions as an edge enhancement filter of 5 pixels × 5 pixels when processing monochrome image data.

  In FIG. 22C, the above-described filtering process (NSF) is executed with respect to the attention area G2, using the upper and lower two pixels (line) and the left and right two pixel areas (hatched areas) as reference data. .

  The scaling process (LIP) block 27 is a processing block that performs linear interpolation scaling processing in the main scanning and sub-scanning directions. In FIG. 22D, the region G3 is a region obtained as a result of the linear storage scaling process, and hatching is applied from the image data (d: (XA−26 pixels) × (YA−26 pixels)). The scaled area is scaled in the main scanning direction and the sub-scanning direction according to a predetermined scaling ratio, and the area of the area G3 is determined.

  The image processing described above is performed on the image data in units of rectangular areas according to the set image processing mode (copy mode, scanner mode). By setting a rectangular area corresponding to the image processing mode on the memory and switching the unit of the rectangular area, it becomes possible to realize resolution and high-definition processing corresponding to each image processing mode.

  In addition, each rectangular area includes a margin required for image processing of each processing block. Therefore, in order to process the edge of the rectangular image data to be processed, the image data in the adjacent area is processed in rectangular units. There is no need to read out data, and a further reduction in work memory can be achieved as compared with a method in which an image is simply divided into rectangles and processed.

  FIG. 25 is a diagram for explaining the DMA transfer processing state of rectangular data in the image processing apparatus according to the present invention. For example, when processing of one rectangular data is completed, the image data of the next rectangular data is DMA transferred. 6 corresponds to a diagram for explaining a starting point in the DMA main scanning direction.

  As shown in FIG. 25, when the DMA of the first rectangular area ABCD is completed and the transfer to the pixel of point D is completed, the start point in the main scanning direction is the position returned by Na + Nb pixels in the main scanning direction (in FIG. 25). S1 point). Thereafter, when the DMA of the rectangular data for one column is sequentially completed and the DMA at the point E corresponding to the final rectangular data of the first column is transferred, the sub-scan is performed to transfer the rectangular data of the next column. The starting point for shifting in the direction is the position returned by Nc + Nd pixels (S2 in the figure).

  FIG. 26 is a flowchart showing an example of a third data processing procedure in the image processing apparatus according to the present invention. For example, the processing corresponds to the data reading in the copy mode and the image processing procedure, and is classified according to the image processing mode at that time. DMA transfer processing and image processing will be described. In addition, (S31)-(S45) show each step. The address information described in FIGS. 26 and 27 uses numerical values corresponding to those in FIG. 22 as an example, but is not limited to these numerical values, and can be set arbitrarily.

<Processing in copy mode>
First, in step S31, it is determined whether the mode is the color mode or the monochrome mode, and if it is determined that the mode is the color mode (YES), the process proceeds to step S33 to determine that the mode is the monochrome mode (NO). ), The process proceeds to step S32.

  In step S33, address information for reading in the color copy mode is set as follows.

  Start address (SA) = memory start address (BUFTOP), UA = memory end address (BUFFBOTTOM) +1, XA = rectangular effective main scanning pixel number + left margin (left margin pixel number (12 pixels), right The number of margin pixels (13 pixels)) and YA = rectangular effective sub-scanning pixel (line) + margin (the number of upper margin pixels (11 pixels (line)), the number of lower margin pixels (11 pixels (line)) ), OFF1A = TOTALWIDTH-XA, OFF2A = − (TOTALWIDTH × YA + margin (12 pixels left, 13 pixels right)), OFF3A = − (TOTALWIDTH × (group margin (upper 11 pixels, lower 11 pixels)) + (Effective main scanning pixel + margin (12 left pixels, 13 right pixels)) and XANUM = effective main scanning pixels / rectangular effective main scanning pixels are set.

  At this time, various parameters corresponding to the mode are set in the buffer arbitration unit 77 as shown in FIG. However, TOTALWIDTH = the number of effective main scanning pixels (IMAGEWIDTH) of one page image + the number of left margin pixels + the number of right margin pixels.

  On the other hand, in step S32, address information for reading in the monochrome copy mode is set as follows.

  Start address (SA) = memory start address (BUFTOP), memory end address (BUFFBOTTOM) + 1, XA = rectangle effective main scanning pixel number + margin (left margin pixel number (2 pixels), right margin Number of pixels (2 pixels)), YA = rectangular effective sub-scanning pixel (line) + margin (upper margin pixel number (2 pixels (line)), lower margin pixel number (2 pixels (line))) and , OFF1A = TOTALWIDTH-XA, OFF2A =-(TOTALWIDTH x YA + margin (left 2 pixels, right 2 pixels)), OFF3A =-(TOTALWIDTH x (glue margin (top 2 pixels, bottom 2 pixels) + effective main Scan pixel + margin (12 pixels on the left and 13 pixels on the right)) and XANUM = effective main scan pixel / rectangular effective main scan pixel, respectively, where TOTALWIDTH = number of main scan effective pixels of one page image (IMAGEWIDTH ) + Left margin pixel number + Right margin pixel number And

  Thus, when the address information is set in the first read data I / F unit 72a in steps S33 and S32, the process proceeds to step S34, and the I / P control unit 72 is ready to read data. Judge whether there is.

  For example, if the activation signal from the buffer arbitration unit 77 has not been issued, the number of lines retained in the buffer of the buffer arbitration unit 77 becomes the number of activation lines, and it waits until the TRIGGER signal is generated, so that buffer read is possible. If so, the process proceeds to step S35.

  In step S35, the first read data I / F unit 72a reads the data according to the set address information, and the data arbitration unit 72b sets the data for a predetermined channel (ch3 to ch6).

  The I / P control unit 72 then DMA-transfers the data set for each channel to the block buffer RAM 210 of the scanner image processing unit 20. Here, the DMA transferred data is loaded into the buffer of the scanner image processing unit 20, and image processing corresponding to each image processing mode is executed. Since the contents of the individual image processing have been described above, detailed description thereof is omitted here.

  The loaded shading correction data and image data are converted from frame sequential data to dot sequential data by the above-described input data processing unit 21, and the following image processing is performed.

  In step S36, it is determined whether the color copy mode or the monochrome copy mode is selected. If it is determined that the color copy mode is selected, the process proceeds to step S37 to execute the character determination process.

  On the other hand, if it is determined in step S36 that the color copy mode is not selected, for example, in the case of the monochrome copy mode, step S37 (character determination process) is skipped, the filter process of step S38 is executed, and the process is changed in step S39. Execute double processing.

  The above processing is executed for each piece of rectangular area data. In step S40, the image-processed dot-sequential image data is further DMA-transferred and stored in a predetermined memory area for storing the image-processed data. This storage process will be described in detail later.

  In step S41, it is determined whether the image processing of the rectangular area and the data storage processing have been completed. If it is determined that the processing has not been completed, the processing returns to step S36 again, and the same processing is executed. .

  On the other hand, if it is determined in step S41 that the processing of the rectangular area has been completed, the process proceeds to step S42 to determine whether or not the processing of the rectangular area constituting the entire page has been completed. If it is determined that the process has not been completed, the process returns to step S34, the subsequent image data is read from the main memory 100, and image processing (steps subsequent to step S34) is executed on that data.

  On the other hand, if it is determined in step S42 that the page processing has been completed, the process proceeds to step S43, the DMA transfer to the scanner image processing unit 20 is terminated, and the buffer of the scanner image processing unit 20 is transferred to the buffer in step S44. The data writing process is terminated, and in step S45, the image processing in the scanner image processing unit 20 is terminated, and the present process is terminated.

  With the above processing, the image processing for the data read in the copy mode is completed.

<Processing in scanner mode>
FIG. 27 is a flowchart showing an example of a fourth data processing procedure in the image processing apparatus according to the present invention. For example, the processing corresponds to the reading of data in the scanner mode and the image processing procedure according to the image processing mode at that time. DMA transfer processing and image processing will be described. In addition, (S51)-(S60) show each step.

  First, in step S51, address information for reading data from the main memory 100 is set as follows.

  Start address (SA) = memory start address (BUFTOP), UA = memory end address (BUFFBOTTOM) +1, XA = rectangular effective main scanning pixel, YA = rectangular effective sub-scanning pixel (line) + margin ( The number of lower margin pixels (one pixel (line))), OFF1A = TOTALWIDTH-XA, OFF2A =-(TOTALWIDTH × YA), OFF3A =-(TOTALWIDTH × (number of margin margin (number of lower margin pixels (1 pixel)) )) + Effective main scanning pixel) and XANUM = effective main scanning pixel / rectangular effective main scanning pixel, respectively, where TOTALWIDTH = number of main scanning effective pixels of one page image (IMAGEWIDTH) + number of left margin pixels + The number of pixels on the right.

  In this way, when the address information is set in the first read data I / F unit 72a in step S51, the process proceeds to step S52, and the I / P control unit 72 is ready to read data. For example, if it is determined that the activation signal from the buffer arbitration unit 77 has not been issued, the number of staying lines in the buffer arbitration unit 77 of the buffer becomes the number of activation lines, and a TRIGGER signal is generated. (S52—NO), and if it is determined that buffer reading is possible, the process proceeds to step S53.

  In step S53, the first read data I / F unit 72a reads the data according to the set address information, and the data arbitration unit 72b sets the data for a predetermined channel (ch3 to ch6).

  The I / P control unit 72 then DMA-transfers the data set for each channel to the buffer of the scanner image processing unit 20. Here, the DMA-transferred data is loaded into the buffer of the scanner image processing unit in step S54, and image processing corresponding to each image processing mode is executed. Since the details of the image processing have been described above, a detailed description thereof will be omitted.

  The image data loaded in this way is converted from the frame sequential data to the dot sequential data by the above-described input data processing unit 21, and the scaling process is executed in step S54.

  Next, in step S55, the image-processed dot-sequential image data is further DMA-transferred and stored in a predetermined memory area for storing the image-processed data. This storage process will be described in detail later.

  In step S56, it is determined whether the image processing of the rectangular area and the data storage processing are completed. If it is determined that the processing is not completed, the process returns to step S54 again, and the same processing is performed. Execute.

  On the other hand, if it is determined in step S56 that the processing of the rectangular area has been completed, the process proceeds to step S57 to determine whether the processing for the entire page has been completed. If it is determined, the process returns to step S52, the subsequent image data is read from the main memory 100, and image processing is executed on the data.

  On the other hand, if it is determined in step S57 that the page processing has been completed, the process proceeds to step S58 to end the DMA transfer to the scanner image processing unit 20, and in step S59 to the buffer of the scanner image processing unit 20 The data writing process is terminated, and in step S60, the image processing in the scanner image processing unit 20 is terminated, and the present process is terminated.

  With the above processing, the image processing for the image data read in the scanner mode is completed.

  Depending on the image processing mode, a rectangular area including a predetermined margin is set, and image processing is performed in units of the rectangular area, thereby performing predetermined image processing without intervening individual line buffers in each image processing unit. It becomes possible to execute.

<Storage of image processed data>
FIG. 28 is a diagram for explaining the storage processing of the image processed data in the image processing apparatus according to the present invention. For example, the rectangular data subjected to the scaling process is transferred from the scaling process block (LIP) 27 to the main memory 100. As an example, when the rectangular data of 256 pixels × 256 pixels is reduced to 70%, 256 pixels × 0.7 = 179.2 pixels, and the rectangular data of 179.2 pixels × 179.2 pixels in numerical calculation However, since pixel data reflecting a numerical value below the decimal point cannot be generated, the appearance probability of 180 pixels and 179 pixels is set to 2: 8 in the main scanning direction and the sub-scanning direction. In particular, 179.2 pixels corresponding to a reduction ratio of 70% are realized.

  In FIG. 28, the size of the rectangular area is different from the areas B11 (XA1 = 180 pixels) and B12 (XA2 = 179 pixels) in the main scanning direction, and the sizes of the subareas are B11 (YA1 = 180 pixels) and B21 (YA2 = 179 pixels). The sizes of the rectangular areas are different in the scanning direction. Appearance probabilities of rectangular areas having different sizes are controlled according to the result of the scaling process, and predetermined scaled image data can be obtained. In order to return the image-processed data to the main memory 100, a signal for controlling the DMA is notified from the scaling processing block (LIP) 27 to the I / P control unit 72 (FIG. 29).

  FIG. 29 is a diagram for explaining a main configuration of the image processing apparatus according to the present invention.

  Next, the storage process in step S40 shown in FIG. 26 and step S55 shown in FIG. 27 will be described in detail.

  FIG. 30 is a timing chart for explaining the operation from the scaling processing block (LIP) 27 to the I / P control unit 72 shown in FIG. 29 for transferring the image-processed data to the main memory 100 by DMA transfer. 10 is an example of a timing chart showing the relationship between data and signals sent from the scaling processing block (LIP) 27 to the I / P control unit 72.

  As shown in FIG. 30, the I / P control unit 72 starts DMA transfer with the rectangular main scanning length and sub-scanning length unknown. When the final data (XA1, XA2) of the main scanning width in one rectangle is transferred from the scaling processing block 27, a line end signal is output, and the main scanning length of the rectangle is changed by the line end signal. To the I / P control unit 72.

  A block end signal is output to the I / P control unit 72 at the time of final data transfer within one rectangle from the scaling processing block 27, whereby the sub-scan length can be recognized. When all the data in the sub-scanning direction YA1 is output, the DMA transfer is shifted to the columns of the areas B21 and B22 (see FIG. 28), and similarly the data XA in the main scanning direction is sent out. The DMA is controlled by a line end signal and a block end signal. Thereby, the rectangular area of the DMA can be dynamically switched according to the calculation result of the scaling processing block 27.

  The line end signal, block end signal, and dot sequential image data described above are input to the interface unit 72c of the I / P control unit 72, and the image data is stored in the channel (ch) 7. The line end signal and the block end signal are used as address information when the data stored in the channel (ch) 7 is expanded on the main memory 100, and the second write data I / F unit 72d receives these addresses. Based on the information, the data of ch7 is read and stored in the main memory 100.

  FIG. 31 is a diagram for explaining an example of image data expansion processing in the image processing apparatus according to the present invention, and corresponds to a state where data is expanded in the main memory 100 in accordance with, for example, a line end signal and a block end signal.

  In FIG. 31, SA indicates a start address of DMA transfer, and dot sequential RGB data is stored from this address in the main scanning direction. Based on the line end signal, the DMA transfer address is switched by offset information (OFF1A), and data is similarly stored in the main scanning direction from the address shifted by one pixel (line) in the sub-scanning direction.

  Then, based on the block end signal of the rectangular area (0, 0), the process proceeds to data storage for the next rectangular area (1, 0). The DMA transfer address is switched by the offset information (OFF2A). In this case, OFF2A is switched as an address shifted by one pixel in the main scanning direction with respect to the region (0, 0) and jumped to the first line in the sub-scanning direction.

  Hereinafter, similarly, the area (2, 0),... (N−1, 0), (n, 0) and data are stored, and when storage of n blocks is completed, the offset information ( The address of DMA transfer is switched by OFF3). In this case, OFF3 is switched as an address that is shifted by one pixel (line) in the sub-scanning direction with respect to the pixel in the last line of the region (0, 0) and jumped to the first pixel in the main scanning direction.

  The control of the scanner I / F unit 10, the scanner image processing unit 20, the DMAC 91, and the buffer arbitration unit 77 has been described above. Hereinafter, the printer image processing unit 30, the LBPI / F unit 40, the DMAC 91, and the buffer arbitration unit 78 will be described. Will be described. Since the detailed control of the DMAC 91 has already been described, only the outline is shown.

  A connection state of the DMAC 91, the buffer arbitration unit 78, the printer image processing unit 30, and the LBPI / F unit 40 will be described with reference to FIG.

  The DMAC 91 includes an I / P control unit 74 that inputs data to the printer image processing unit 30, an I / O control unit 75 that DMA-transfers output image data from the printer image processing unit 30 to the main memory 100, the main memory 100, and the LBPI. An I / P control unit 76 that controls data exchange with the / F unit 40 is included.

  Data exchange between the I / O control unit 75 and the I / P control unit 76 is performed via an intermediate buffer on the main memory 100. When this intermediate buffer is used as a ring buffer, a buffer arbitration unit 78 for arbitrating data writing and reading is used.

  The printer image processing unit 30 and the LBPI / F unit 40 are blocks corresponding to the resolution conversion unit 2500 of the conventional example. The printer image processing unit 30 and the LBPI / F unit 40 are divided into two blocks, the printing system. This is to cope with both the BJ printer 175 and the LBP 45.

  In an apparatus having an LBP 45 in the printing system, the output data of the printer image processing unit 30 is transmitted to the LBP 45 via the LBPI / F 40 and printed out. On the other hand, when the BJ printer 175 is a printing system, printing is performed via the USB 1.1 HOST 150. Data is sent to a BJ printer and printed.

  The buffer arbitration unit 78 includes an LBP recorder and is used only when the LBPI / F unit 40 is used.

  The LBPI / F unit 40 is composed of two blocks, ch1 and ch2. Each block is equivalent and corresponds to an LBP scanning beam. When the number of scanning beams is 1, only ch1 of the LBPI / F unit 40 is used, and when the number of scanning beams is 2, ch1 and ch2 of the LBPI / F unit 40 are used in association with each beam. The ch1 of the LBPI / F unit 40 is connected to the ch10 of the I / P control unit 76, and the ch2 of the LBPI / F unit 40 is connected to the ch11 of the I / P control unit 76.

<Configuration of I / O control unit 75>
The configuration of the I / O control unit 75 is basically the same as the configuration of the I / O control unit 71.

  The only difference is the number of buffer channels. Since the number of channels is 1, there is no unit corresponding to the data arbitration unit 71a.

  As shown in FIG. 10, the schematic configuration of the buffer arbitration units 77 and 78 and the DMAC 91 are connected. The buffer arbitration unit 78 detects the transfer completion signal Read_end signal from the control register 781 and the read-side DMAC channel. A detection unit 783, a write update detection unit 782 that detects a transfer completion signal Write_end signal from the write-side DMAC channel, a stay counter 784 that counts the stay amount of the intermediate buffer 1, and a control signal to the DMAC 91 according to the number of stay lines And an LDMAC control signal generation unit 785.

<Configuration of I / P control units 74 and 76>
The configuration of the I / O control units 74 and 76 is basically the same as that of the I / P control unit 72.

  Only the number of buffer channels is different. Since the number of channels of the I / O control unit 74 is “1”, there is no unit corresponding to the data arbitration unit 72b.

  The buffer arbitration units 77 and 78 have the same configuration except that the number of channels in the connected I / O control unit 76 is 1, and the number of channels in the I / P control unit 76 is two. There is only. The transfer end signal is connected to the buffer arbitration unit 78 in the I / O control unit, and the I / P control unit 76 is connected to the buffer arbitration unit 78 in a two-dimensional (hereinafter referred to as tile) transfer end signal. The reason why the tile transfer end signal of the I / P control unit 76 is used is to enable resolution conversion in the sub-scanning direction by reading the same line repeatedly.

  FIG. 32 is a diagram for explaining an example of mode setting in the image processing apparatus according to the present invention. For example, DEC_VALUE, TRIGGER_LINE, and RING_LINE are set for each recording mode.

  This setting and the setting of the I / P control unit 76 of the DMAC 91 are performed before the start of the recording operation, and the buffer can be continuously managed without changing the setting after the start of the recording operation.

  FIG. 33 is a diagram showing the data transfer to the LBPI / F unit 40 shown in FIG. 1 and the channel correspondence of the DMAC 91 until data is read from the intermediate buffer 100 secured on the main memory and output to the LBP 45. Corresponds to the flow.

  For example, when the LBP 45 is configured by a one-beam printer, only the ch10 of the DMAC 91 and the ch10 of the LBPI / F unit 40 are used as shown in FIG. The print image developed in the intermediate buffer is transferred line by line to the LBPI / F unit 40 and printed out by the LBP 45.

  When the LBP 45 is constituted by a two-beam printer, as shown in FIG. 33 (b), the ch10 of the DMAC 91 and the ch1 of the LBPI / F unit 40 are LBPI in order of the odd lines of the print image developed in the intermediate buffer. The data is transferred to the / F unit 40 and printed out by the LBP 45. The ch11 of the DMAC 91 and the ch2 of the LBPI / F unit 40 transfer the even lines of the print image developed in the intermediate buffer to the LBPI / F unit 40 in a line-sequential manner and print out at the LBP 45.

  DEC_VALUE differs depending on the number of LBP 45 beams. When the number of beams is 1, only the channel 10 of the I / P control unit 76 on the reading side is used. Therefore, the number of lines is subtracted from the staying number by one for each occurrence of the transfer completion signal Read_end. When the number of beams is 2, only the channel 10 of the I / P control unit 76 on the reading side is used, so that the number of lines is subtracted from the staying number by 2 for one generation of the transfer completion signal Read_end.

  As described above, the image-processed data is DMA-transferred to a predetermined area of the main memory 100 by dynamically switching the offset information (OFF1A, OFF2A, OFF3) by the line end signal and the block end signal. Can be stored.

<Other embodiments>
In the above embodiment, the present invention has been described with a composite image processing apparatus having various image input / output functions. However, the present invention is not limited to this, and a single-function scanner apparatus, printer apparatus, or other apparatus. The present invention can also be applied to an option card for expansion connection. Further, the unit configuration of the apparatus related to the present invention is not limited, and for example, the apparatus or system related to the present invention may be configured to be achieved by a plurality of apparatuses connected via a network. .

  According to each of the above embodiments, in an image processing apparatus including an image block that performs input / output in units of a rectangular shape via an intermediate buffer, the size of the intermediate buffer between blocks can be optimized according to the processing content and capability. .

  Furthermore, it is possible to reduce the buffer management load of software in the control of the intermediate buffer.

  Further, by setting a rectangular area corresponding to the image processing mode on the memory and switching the unit of the rectangular area, it is possible to realize resolution and high-definition processing corresponding to each image processing mode.

  In addition, by setting a rectangular area including a predetermined margin amount according to the image processing mode and performing image processing in units of the rectangular area, a predetermined image can be obtained without intervening individual line buffers in each image processing unit. It becomes possible to execute processing.

  The configuration of a data processing program that can be read by the printing apparatus according to the present invention will be described below with reference to the memory map shown in FIG.

  FIG. 34 is a diagram illustrating a memory map of a storage medium that stores various data processing programs readable by the printing apparatus according to the present invention.

  Although not particularly illustrated, information for managing a program group stored in the storage medium, for example, version information, creator, etc. is also stored, and information depending on the OS on the program reading side, for example, a program is identified and displayed. Icons may also be stored.

  Further, data depending on various programs is also managed in the directory. In addition, a program for installing various programs in the computer, and a program for decompressing when the program to be installed is compressed may be stored.

  The functions shown in FIGS. 17, 18, 26, and 27 in this embodiment may be performed by a host computer by a program installed from the outside. In this case, the present invention is applied even when an information group including a program is supplied to the output device from a storage medium such as a CD-ROM, a flash memory, or an FD, or from an external storage medium via a network. Is.

  As described above, a storage medium storing software program codes for realizing the functions of the above-described embodiments is supplied to the system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the storage medium in the storage medium. It goes without saying that the object of the present invention can also be achieved by reading and executing the programmed program code.

  In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

  Therefore, as long as it has the function of the program, the form of the program such as an object code, a program executed by an interpreter, or script data supplied to the OS is not limited.

  As a storage medium for supplying the program, for example, a flexible disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD, etc. Can be used.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As another program supply method, a browser of a client computer is used to connect to a homepage on the Internet, and the computer program itself of the present invention or a compressed file including an automatic installation function is stored on a recording medium such as a hard disk from the homepage. It can also be supplied by downloading. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server, an ftp server, and the like that allow a plurality of users to download a program file for realizing the functional processing of the present invention on a computer are also included in the claims of the present invention.

  In addition, the program of the present invention is encrypted, stored in a storage medium such as a CD-ROM, distributed to users, and key information for decryption is downloaded from a homepage via the Internet to users who have cleared predetermined conditions. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) or the like running on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the storage medium is written to a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

  The present invention is not limited to the above embodiments, and various modifications (including organic combinations of the embodiments) are possible based on the spirit of the present invention, and these are excluded from the scope of the present invention. is not.

  Although various examples and embodiments of the present invention have been shown and described, those skilled in the art will not limit the spirit and scope of the present invention to the specific description in the present specification.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

1 is a block diagram illustrating a schematic configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of a scanner I / F unit illustrated in FIG. 1. 3 is a timing chart for explaining an example of an output signal from the CCD shown in FIG. 2. It is a timing chart regarding the lighting control of LED with respect to CIS shown in FIG. According to the timing chart shown in FIG. 4, the LEDs corresponding to R, G, and B are turned on ((a) to (d)), and the output is photoelectrically converted by the reflected light of the LEDs accumulated during the lighting time. It is a timing chart which shows the relationship with (e). 3 is a timing chart for explaining an LED lighting control operation shown in FIG. 2. 3 is a timing chart showing an output example when the CIS shown in FIG. 2 is provided with two channels in the main scanning direction. FIG. 3 is a block diagram illustrating a configuration of the AFE illustrated in FIG. 2. FIG. 2 is a block diagram illustrating a schematic configuration of the image processing DMAC illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a schematic configuration of a buffer arbitration unit illustrated in FIG. 1 and a connection relationship between DMACs. It is a timing chart for demonstrating operation | movement of the buffer arbitration part shown in FIG. 10, and DMAC. FIG. 11 is a diagram illustrating a process in which the I / O control unit shown in FIG. 10 writes data for one channel in a main memory (SDRAM). It is a figure explaining the data storage process with respect to SDRAM by the image processing DMAC shown in FIG. It is a figure explaining the example of a data writing process by the image processing DMAC shown in FIG. It is a figure which shows the state which divided | segmented the main memory shown in FIG. 1 into the predetermined | prescribed rectangular area (block). It is a figure which illustrates the capacity | capacitance required for the main memory shown in FIG. 1 according to image processing mode. It is a flowchart which shows an example of the 1st data processing procedure in the image processing apparatus which concerns on this invention. It is a flowchart which shows an example of the 2nd data processing procedure in the image processing apparatus which concerns on this invention. It is a figure explaining the data reading process in the image processing apparatus which concerns on this invention. It is a figure which shows the example of a setting of DEC_VALUE, TRIGGER_LINE, and RING_LINE for every reading mode in the image processing apparatus which concerns on this invention. It is a figure explaining the example of a data processing in the image processing apparatus which concerns on this invention. It is a schematic diagram explaining the size of the rectangular area required for each image processing in the image processing apparatus according to the present invention. It is a figure explaining the image processing area | region in the image processing apparatus which concerns on this invention. It is a figure which illustrates the margin for each image processing mode (color copy mode, monochrome copy mode, scanner mode) in the image processing apparatus according to the present invention. It is a figure explaining the DMA transfer processing state of the rectangular data in the image processing apparatus which concerns on this invention. It is a flowchart which shows an example of the 3rd data processing procedure in the image processing apparatus which concerns on this invention. It is a flowchart which shows an example of the 4th data processing procedure in the image processing apparatus which concerns on this invention. It is a figure explaining the storage process of the image processed data in the image processing apparatus which concerns on this invention. It is a figure explaining the principal part structure in the image processing apparatus which concerns on this invention. FIG. 30 is a timing chart for explaining operations of a scaling processing block (LIP) and an I / P control unit shown in FIG. 29. FIG. It is a figure explaining the example of expansion | deployment processing of the image data in the image processing apparatus which concerns on this invention. It is a figure explaining the example of a mode setting in the image processing apparatus which concerns on this invention. It is a figure which shows the data transfer to LBPI / F shown in FIG. 1, and a DMAC channel correspondence. It is a figure explaining the memory map of the storage medium which stores the various data processing program which can be read with the printing apparatus which concerns on this invention. It is a block diagram which shows the structure of the scanner image processing circuit and the recording image processing circuit in the conventional image processing apparatus.

Explanation of symbols

15 AFE
17 CCD
18 CIS
77, 78 Buffer arbitration unit 91 Image processing DMAC
100 main memory

Claims (10)

Writing means for sequentially writing the image data input by the image input means to the memory along the main scanning direction;
Determining means for determining whether the image data written in the memory by the writing means has been accumulated for a predetermined sub-scanning width;
Dividing the image data written in the memory in a main scanning direction with a predetermined main scanning width;
Reading means for reading out the image data in order to output the image data from the memory to the image processing means in a rectangular shape unit comprising the predetermined main scanning width and the predetermined sub-scanning width;
Based on whether or not the image data amount stored in the memory is readable in the rectangular shape, arbitration means for arbitrating to read out the rectangular shape by the reading means;
An image processing apparatus comprising: Counting means for counting the amount of image data stored in the memory;
The writing unit counts up each time the image data of one line is written in the main scanning direction, and the reading unit reads out the one line in the main scanning direction for each rectangular unit. The image processing apparatus according to claim 1, wherein a predetermined number is subtracted. Storage means for temporarily storing the image data input by the image input means according to the input method of the image input means;
The writing means writes the image data stored in the storage means into the memory according to the input method of the image input means, and the reading means reads regardless of the input method of the image input means. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus.   4. The arbitration unit includes a remaining amount detection unit, and outputs a stop signal to the writing unit to stop the operation on the writing side when the memory is full. An image processing apparatus according to any one of the above.   The arbitration unit includes a trigger generation unit, and when a predetermined number of lines of data corresponding to a processing line unit on a read side is accumulated in the memory, an output signal is output to the read unit to perform read control. The image processing apparatus according to claim 1, wherein the image processing apparatus is started.   7. The image processing apparatus according to claim 1, wherein the predetermined rectangular shape unit can be set to a variable amount based on an image processing mode.   The image processing apparatus according to claim 1, wherein the writing unit is capable of connecting a plurality of types of image reading devices. A writing step of sequentially writing the image data input by the image input means in the memory along the main scanning direction;
A determination step of determining whether or not the image data written in the memory by the writing step has been accumulated for a predetermined sub-scanning width;
The image data written in the memory is divided by a predetermined main scanning width in the main scanning direction, and the image data is read from the memory in units of a rectangular shape including the predetermined main scanning width and the predetermined sub scanning width. A reading step for reading the image for output to the processing means;
An arbitration step for arbitrating to read out the rectangular shape by the reading means based on whether the image data amount stored in the memory is readable in the rectangular shape;
An image processing method comprising:   A computer-readable storage medium storing a program for realizing the image processing method according to claim 8.   A program for realizing the image data processing method according to claim 8.

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