JP2005118159A - Electronic endoscope apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a convenient electronic endoscope apparatus capable of connecting various kinds of electronic endoscopes with different frame rates to a processor and displaying images with improved moving image performance. <P>SOLUTION: The processor 11 to which various kinds of electronic scopes 10 are connected has a frame rate detection circuit 32 for detecting the frame rate of the picture signal outputted from the electronic scope 10 by comparing a scope side vertical synchronizing signal and a processor side vertical synchronizing signal. For example, if an electronic endoscope 10 in which a 850,000 pixel CCD is installed is connected, the frame rate of 1/20 is detected; if an electronic endoscope 10A in which a 1,300,000 pixel-equivalent honeycomb CCD 14 is installed, the frame rate of 1/30 is detected. Then, a non-TV resolution conversion circuit 28 reads the same image three times when the frame rate is 1/20 and twice when the frame rate is 1/30, and an image of an observed subject is displayed on a non-TV monitor at the frame rate of 1/60. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic endoscope apparatus, in particular, various electronic scopes having different numbers of pixels (particularly, the number of vertical scanning lines is larger than that of a TV (TV) output) mounted on a processor device and imaged. The present invention relates to a configuration of an electronic endoscope apparatus that can display a subject image on a non-TV monitor or a TV monitor.

  An electronic endoscope apparatus includes a solid-state imaging device such as a CCD (Charge Coupled Device) mounted on the tip of an electronic scope (electronic endoscope). In this CCD, an object to be observed is based on illumination of light from a light source device. Image. The imaging signal obtained by such a CCD is output to the processor device, and various image processing is performed by the processor device, so that the image of the object to be observed is displayed on a monitor (display) or a still image is recorded. Can be recorded on the device.

  In this type of electronic endoscope apparatus, a CCD having a larger number of pixels than the number of display pixels (resolution: in particular, the number of vertical scanning lines) of a TV monitor is mounted, and an object to be observed imaged by this high pixel number CCD. Video (moving images and still images) can be displayed not only on a TV monitor but also on a PC (personal computer) monitor.

FIG. 8 shows a process in a case where images obtained by CCDs having different numbers of pixels are displayed on a PC monitor and a TV monitor. As shown in FIG. 8 (A), when a CCD (for example, 410,000 pixels) 1a of a TV system (suitable for television display resolution) is used, the number of pixels of the image obtained by this CCD 1a is built in the frame memory. The image signal increased by the resolution conversion circuit 2a and the number of pixels increased is output to the PC monitor, and the output signal from the CCD 1a is directly output to the TV monitor without resolution conversion. Further, as shown in FIG. 8B, when a PC system (having a resolution higher than the television display resolution) CCD (for example, 850,000 pixels) 1b is used, resolution conversion is performed on the signal output from the CCD 1b. Without being output to the monitor for the PC as a video signal, and for the TV monitor, the number of pixels of the image obtained by the CCD 1b is reduced by the resolution conversion circuit 2b having a built-in frame memory, and the number of pixels is reduced. The signal is output to the TV monitor. According to this, it becomes possible to observe and use a high-resolution endoscopic image obtained by a CCD having a high pixel count.
JP 2000-287203 A Japanese Patent Laid-Open No. 2002-25396

  By the way, the light receiving sensitivity of the CCD, which is a conventional solid-state imaging device, is not so high, and it is necessary to set the photoelectric conversion time to be long to some extent. Become. For this reason, although the resolution is improved, switching of images on the screen is conspicuous, and it cannot be said that the moving image performance is good. However, in recent years, IC technology has been devised to keep the display resolution high due to the evolution of IC technology. For example, a honeycomb CCD of 650,000 pixels (equivalent to 1.3 million pixels) has been developed to increase the frame rate of moving images. Such a high frame rate moving image can be displayed on a PC monitor (frame rate 1/60).

  However, manufacturing various electronic endoscopes that form moving images with different frame rates in combination with a processor device is wasteful and expensive. Therefore, if various electronic endoscopes that form moving images with different frame rates can be connected to a single processor device, a user-friendly device can be obtained.

  On the other hand, in recent years, the speed of increasing the number of pixels of a CCD is fast. For example, a CCD having a high pixel number exceeding 850,000 pixels can be used, such as the honeycomb CCD corresponding to the above 1.3 million pixels. However, when the CCD with an increased number of pixels is mounted on an electronic endoscope, a configuration corresponding to the higher number of pixels is required even in the processor device, and thus a conventional processor device cannot be used. In other words, considering the configuration of FIG. 8, the configuration of the frame memory in the resolution conversion circuits 2a and 2b corresponds to 850,000 pixels, and an image with a larger number of pixels overflows data and performs high resolution processing. Is impossible. Of course, a processor device that performs processing corresponding to a CCD having a large number of pixels may be manufactured together. However, in this case, conventional devices (assets) cannot be used effectively.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to connect various electronic endoscopes having different frame rates to a processor device to display an image with improved moving image performance. It is in providing a good electronic endoscope apparatus.

In order to achieve the above object, according to the first aspect of the present invention, there are provided various electronic scopes equipped with solid-state imaging devices having different numbers of pixels, and these various electronic scopes are detachably connected to each other to display the video signal. A processor device that performs signal processing for output, and the processor device outputs an output of the electronic scope by comparing the scope-side vertical synchronization signal and the processor-side vertical synchronization signal for driving the solid-state imaging device. A frame rate detection circuit that detects a frame rate of a video signal, and an image output circuit that outputs an image signal at a frame rate capable of maintaining the moving image performance of various electronic scopes based on the output of the frame rate detection circuit. It is characterized by.
According to a second aspect of the present invention, there is provided a solid-state imaging device having a larger number of pixels than the maximum number of pixels to be displayed and processed by the processor device, and an output image frame rate of the image having the maximum number of pixels on the processor side. An electronic scope that is higher than the above is provided, and in this electronic scope, the number of pixels of the image signal output from the solid-state imaging device (effective recording pixel number of the solid-state imaging device) is converted into an image signal having the maximum number of pixels on the processor side. A scope-side resolution conversion circuit for down-conversion is provided.

According to a third aspect of the present invention, there is provided a TV (television) system electronic endoscope having a TV system solid-state image sensor mounted thereon and a non-TV system electronic scope having a non-TV system [for example, PC (personal computer) system] solid-state image sensor. When the TV electronic endoscope is connected to the processor device, conversion to the number of pixels for non-TV is performed, and when the non-TV electronic scope is connected, the number of pixels for TV is converted. A resolution conversion circuit for conversion is provided, and the image output circuit outputs an image signal at a frame rate of a non-TV display device. Examples of the TV solid-state image sensor include an interline CCD, and examples of the non-TV solid-state image sensor include a progressive CCD compatible with a personal computer monitor.
According to a fourth aspect of the present invention, in the frame rate detection circuit, the scope side clock signal used in the electronic scope and the processor side clock signal are compared, and the scope side vertical synchronization signal and the processor side vertical synchronization signal are compared. The number of pixels of the solid-state imaging device of the connected electronic endoscope is determined.

  According to the configuration of the first aspect, the electronic scope is obtained by comparing the scope-side vertical synchronization signal for driving the solid-state imaging device and the processor-side vertical synchronization signal [for example, the vertical synchronization signal of the non-TV PC monitor for PC]. For example, 1/20 (20 frames displayed per second), 1/30, and 1/60 are detected. Since the non-TV monitor can display at a frame rate of 1/60, when the frame rate is 1/20, it is 3 times, and when it is 1/30, it is 2 times. In the case of the same frame image, the same frame image is output once. This makes it possible to observe a video with improved moving image performance without reducing the frame rate obtained on the electronic scope side.

  According to the configuration of the second or third aspect, for example, a processor device that performs image processing corresponding to a 850,000 pixel (number of pixels on the processor side) CCD of a non-TV system (for example, suitable for display on a PC monitor) is provided with Considering the case where a new electronic scope equipped with a 650,000-pixel honeycomb CCD equivalent to 10,000 pixels is connected, the resolution conversion circuit of the new electronic scope has a pixel number (1280 × 960) corresponding to 1.3 million pixel CCD per video signal. SXGA) to a number of pixels corresponding to 850,000 pixel CCD (1024 × 768 XGA). In this case, in the video processing of the 850,000 pixel CCD, the frame rate is 1/20, whereas in the video processing with the new electronic scope, the frame rate is 1/30 because a high processing speed (clock frequency) can be used. Therefore, when a new electronic scope is connected, an image with high moving image performance can be displayed.

  According to the configuration of the fourth aspect, in addition to the comparison between the scope-side vertical synchronization signal and the processor-side vertical synchronization signal, the scope-side clock signal and the processor-side clock signal are compared, whereby the connected electronic scope is 41. It is determined whether a TV-type CCD having 10,000, 270,000 pixels or the like or a non-TV-type CCD (manufactured for the purpose of improving moving image performance) having 170,000 pixels is mounted.

  According to the electronic endoscope apparatus of the present invention, since the frame rate of the moving image formed on the electronic scope side is detected using the vertical synchronization signal, the electronic endoscope having a high frame rate is used as the processor apparatus. When connected, it is possible to display and observe a good image maintaining its moving image performance, and to obtain an easy-to-use electronic endoscope apparatus. In particular, according to the detection based on the vertical synchronization signal of the present invention, there is an advantage that the frame rate can be detected directly without using the identification information acquired from the electronic scope. In addition, according to the improvement in the configuration of the number of pixels and the driving frequency in the solid-state imaging device, it is possible to effectively use the conventional device and reduce the cost without manufacturing the electronic scope as a set with the processor device.

  1 to 6 show the configuration of an electronic endoscope apparatus according to the embodiment. As shown in FIG. 1, the electronic endoscope apparatus is an electronic scope (electronic endoscope) 10. The electronic scope 10 includes a processor device 11 and a light source device 12 that can be detachably connected. The illumination light output from the light source device 12 is supplied to the distal end portion of the electronic scope 10 through the light guide, and is irradiated from the distal end portion to the object to be observed. As the electronic scope 10, in addition to various scopes on which a CCD (solid-state imaging device) having 850,000 pixels, 410,000 pixels, 270,000 pixels, 170,000 pixels or the like is mounted, the illustrated new electronic scope 10A is provided.

  At the tip of the new electronic scope 10A, for example, a CCD 14 comprising a 650,000 pixel honeycomb CCD (the number of output pixels is 1.3 million pixels), a normal 1.3 million pixel CCD, or the like is mounted. The CCD 14 is connected with a CDS (correlated double sampling) circuit 15 for sampling a CCD output signal, an A / D converter 17 and the like, and as a scope-side resolution conversion circuit after the A / D converter 17. A DSP (digital signal processor) 18 for forming and outputting a Y (luminance) signal and a C (color) signal and an image conversion circuit 19 incorporating a line memory are provided. The DSP 18 performs various image processing and converts the number of pixels in the horizontal and vertical directions of the image, and the image conversion circuit 19 converts the image format by controlling writing and reading of the line memory. The number of pixels of the CCD 14 (for example, 1.3 million pixels) is down-converted to the maximum number of pixels on the processor side (for example, 850,000 pixels).

  The new electronic scope 10 includes a timing generator (TG) 21 that forms a clock frequency, a horizontal synchronization signal, a vertical synchronization signal, and the like for signal reading from the CCD 14 and image processing in each circuit. A microcomputer 22 that performs general control, an EEPROM 23 that stores various data and programs for pixel formation, and the like are arranged.

  1 includes a level conversion circuit 25 for converting the level of a video signal, and Y (luminance) and C (color) signals into R (red), G (green), and B (blue) signals. A color conversion circuit 26 to convert, an interlace signal output from the color conversion circuit 26 to a progressive (non-interlace) signal (a progressive signal is allowed to pass), an interlace / progressive (I / P) conversion circuit 27, and non-TV use A non-TV resolution conversion circuit 28 and a D / A converter 31 are provided to match the number of pixels of a monitor (for example, a PC monitor). A frame rate detection circuit 32 including a synchronization signal generation circuit (SSG) is provided so as to input the output of the timing generator 21 of the electronic scope 10A. The frame rate detection circuit 32 and the non-TV resolution conversion circuit 28 are composed of, for example, an FPGA (Field Programmable Gate Array).

  The non-TV resolution conversion circuit 28 has a frame memory that stores image data for one frame of the XGA (Extended Graphics Array-1024 × 768 pixels) standard corresponding to 850,000 pixels, and performs processing for XGA. However, when a new electronic scope 10A or an electronic scope 10 equipped with a 850,000 pixel CCD is connected, this resolution conversion is not performed, but a TV-type CCD such as 410,000 pixels or an electronic scope with other number of pixels is used. When 10 is connected, resolution conversion is performed to increase the number of pixels of the XGA image to 1024 × 768. Then, as will be described later, processing for matching the frame rate is executed.

  Further, the processor device 11 includes a TV resolution conversion circuit 35 for inputting the output of the non-TV resolution conversion circuit 28, a progressive / interlace (P / I) conversion circuit 36 for converting a progressive signal into an interlace signal, and this conversion. A D / A converter 37 that converts the RGB signal output from the circuit 36 into an analog signal, and an encoder that converts the RGB signal output from the progressive / interlace conversion circuit 36 into Y (luminance) and C (color) signals 38, a D / A converter 39, and a microcomputer 41 that controls the circuits in the processor unit 11 are provided.

  The TV resolution conversion circuit 35 has a frame memory for storing image data for one frame of the VGA (Video Graphics Array-640 × 480 pixels) standard, and performs an XGA image by performing resolution conversion to reduce the number of pixels. Is converted to a VGA image. That is, the image obtained by the TV-type CCD is restored by reducing the number of pixels increased by the non-TV resolution conversion circuit 28, and the image obtained by the non-TV-type CCD including the CCD 14 of the new electronic scope 10A. Also, the number of pixels is reduced.

  FIG. 2 shows a detailed configuration regarding the frame rate processing in the frame rate detection circuit 32 and the non-TV resolution conversion circuit 28. The frame rate detection circuit 32 is inputted with a scope side clock signal. A clock detection unit 44 for detecting whether the CCD mounted on the electronic scope 10 has 410,000 pixels, 270,000 pixels, 170,000 pixels, or other 850,000 pixels, 1.3 million pixels. And a vertical synchronization signal detector 45 that receives the scope-side vertical synchronization signal and detects the frame rate of the image obtained by the electronic scope 10.

  Also, an image obtained by an oscillator 46 for generating a reference clock signal having a frequency of 14.318 MHz, a frequency multiplier 47 for multiplying the reference clock frequency, a non-TV system (PC system) 850,000 pixel CCD, a TV system CCD, or the like is processed. A synchronization signal generation circuit (SSG) 48 for generating a clock frequency, a horizontal synchronization signal, a vertical synchronization signal, a display system vertical synchronization signal for display on a non-TV monitor, and the like is provided. The reference clock signal output from the oscillator 46 is used as the reference clock signal for the clock detection unit 44, and the display system vertical synchronization signal output from the synchronization signal generation circuit 48 is used as the reference for the vertical synchronization signal detection unit 45. Used as a vertical synchronization signal.

  On the other hand, the non-TV resolution conversion circuit 28 is provided with an image memory (frame memory or the like) 28a and a memory controller 28b for controlling writing and reading of data in the image memory 28a. Then, data read control for adjusting to the frame rate 1/60 of the non-TV monitor is performed.

  FIG. 3 shows a circuit configuration in the clock detection unit 44. The clock detection unit 44 has an FF for inputting the processor-side reference clock signal [FIG. 4A] from the terminal a to the terminal CLK. (Flip-flop) circuit 44a, the scope side clock signal is input to the terminal CLK from the terminal b, and the Q output of the FF circuit 44a is input to the terminal D. The scope side clock signal is input from the terminal b to the terminal CLK. An FF circuit 44c that inputs the Q output of the FF circuit 44b to the terminal D and a determination circuit 44d that inputs the Q output of the FF circuit 44b and the Q output of the FF circuit 44c are provided.

  FIG. 5 shows a circuit configuration in the vertical synchronization signal detection unit 45. The vertical synchronization signal detection unit 45 includes three latch circuits for inputting a processor-side vertical synchronization signal from a terminal f to a terminal CLK. A latch circuit 45a for inputting a scope-side vertical synchronization signal from the terminal e to the terminal D, a latch circuit 45b for inputting the Q output of the latch circuit 45a to the terminal D, and a Q output of the latch circuit 45b to the terminal D. A latch circuit 45c for input and a determination circuit 45d for inputting Q outputs of the latch circuits 45a to 45c are provided.

  The embodiment has the above-described configuration. In this example, the electronic scope 10 (10A) connected by the clock detection circuit 44 and the vertical synchronization signal detection circuit 45 in FIG. 2 is connected to the 650,000-pixel honeycomb CCD 14 and the 850,000-pixel CCD. Or a non-TV (progressive) scope with a 170,000 pixel CCD with improved video performance, or a TV (interlace) scope with a 410,000 or 270,000 pixel CCD The frame rate is detected including the determination of whether or not. The outline of each frequency of each CCD is as shown in Table 1 below.

なお、このクロック周波数はＣＣＤのピクセルをラッチする周波数である。

This clock frequency is a frequency for latching CCD pixels.

  First, in the clock detection circuit 44 of FIG. 3, when the processor side reference clock signal [about 14 MHz (Table 1)] of FIG. 4A is input to the terminal CLK of the FF 44a, the data position signal of FIG. Is supplied from the terminal Q bar (6) to the terminal D (2). The terminal Q of the FF 44a is connected to the terminal D of the FF 44b, and the scope-side clock signal is supplied to the terminal CLK of the FF 44b and the FF 44c with the terminal Q of the FF 44b connected to the terminal D of the FF 44c. Therefore, in the case of the clock signal (about 20 MHz) for the 850,000 pixel CCD in FIG. 4C, there are two rising edges at the rising edge in FIG. ) The signal is output twice (determined result is 2). In the case of the clock signal (about 24 MHz) for the 650,000-pixel honeycomb CCD in FIG. 4D, there are two rises at the rise in FIG. 4B, so the H signal is sent twice from the determination circuit 44d. Is output. In the case of the clock signal (about 14 MHz) for the 410,000, 270,000 and 170,000 pixel CCDs in FIG. 4E, there is one rise at the rise of FIG. Is output (determination result is 1).

  Next, in the vertical synchronization signal detection circuit 45 of FIG. 5, the processor side (display system) vertical synchronization signal (60 Hz) of FIG. 6A is supplied from the terminal f to the terminals CLK of the latch circuits 45a to 45c. The scope-side vertical synchronization signal is output from the terminal e to the latch circuit 45a. The terminal Q of the latch circuit 45a is connected to the terminal D of the latch circuit 45b, and the terminal Q of the latch circuit 45b is connected to the terminal D of the latch circuit 45c. Therefore, in the case of the vertical synchronization signal [20 Hz (Table 1)] for the 850,000 pixel CCD in FIG. 6B, three H (High) signals are input to the determination circuit 45d (the determination result is 3). To do). In the case of the vertical synchronization signal (30 Hz) for a CCD of 650,000 pixels, 410,000 pixels, and 270,000 pixels in FIG. 6C, two H (High) signals are input to the determination circuit 45d (determination result). In the case of the vertical synchronizing signal (20 Hz) for the 170,000 pixel CCD in FIG. 6D, one H signal is input (the determination result is 1).

  In this way, when the clock detection result is 2 and the vertical synchronization signal detection result is 3, the 850,000 pixel CCD (frame rate 1/20), the clock detection result is 2, and the vertical synchronization signal detection result 2 is 650,000 pixel honeycomb CCD (frame rate 1/30), the clock detection result is 1, and when the vertical synchronization signal detection result is 1, 170,000 pixel CCD (frame rate 1/60) ) When the clock detection result is 1 and the vertical synchronization signal detection result is 2, it is detected that the CCD is 410,000 pixels or 270,000 pixels (TV interlace, frame rate 1/30).

  When the frame rate is detected, the non-TV resolution conversion circuit 28 shown in FIG. 2 reads the same image data three times from the frame memory 28a when the frame rate is 1/20, and when the frame rate is 1/30. The same image data is read twice from the frame memory 28a. When the frame rate is 1/60, the image data is read once from the frame memory 28a, and these image signals are supplied to the non-TV monitor. As a result, it is possible to observe an image of an object to be observed with good moving image performance while maintaining the frame rate set in each electronic scope 10. For example, when the new electronic scope 10A shown in FIG. 1 or the electronic scope 10 equipped with a 170,000 pixel CCD is connected, an image with higher moving image performance is obtained than when the electronic scope 10 equipped with a 850,000 pixel CCD is connected. Is displayed.

FIG. 7 shows the conversion of the number of pixels performed by the new electronic scope 10A of FIG. 1. Since this scope 10A is equipped with a honeycomb CCD 14 equivalent to 1.3 million pixels, the effective pixels of the image obtained by this CCD 14 are shown. The number is down-converted from 1280 × 960 [SXGA-Super XGA in FIG. 7A] to the maximum number of display pixels on the processor side of 1024 × 768 [XGA in FIG. 7B]. That is, in the DSP 18, the horizontal pixels of the horizontal lines L ₁ , L ₂ ... Are thinned out to 4/5 (and weighted average calculation is performed between adjacent pixels), and the vertical pixels are also divided into 4/5 lines. Is drawn (and the adjacent upper and lower lines are added). Then, the image conversion circuit 19 at the next stage performs format conversion using a line memory. That is, since the new electronic scope 10A uses the 650,000-image honeycomb CCD 14, as can be seen from Table 1, the horizontal line of the SXGA image is written to the line memory at a high clock frequency f ₁ (fast speed). An XGA image can be obtained by reading from the memory at a clock frequency f ₂ (slower speed) lower than f ₁ . The line memory is set to the number of pixels so that fast writing of data does not overtake slow reading.

  The XGA image signal thus formed is supplied to the processor device 11. In the processor device 11, the image signal is converted to D / A without performing resolution conversion in the non-TV resolution conversion circuit 28. It is output to a non-TV monitor via the converter 31 and a moving image (an image obtained by down-converting 1.3 million pixels to 850,000 pixels) is displayed on the non-TV monitor in a progressive manner. The image signal is output to the TV monitor via the D / A converter 37 or 39 by performing the TV resolution conversion by the TV resolution conversion circuit 35. A moving image (an image obtained by downconverting 1.3 million pixels to 410,000 pixels) is displayed in an interlaced manner.

  In the above embodiment, the frame rate is detected by distinguishing the number of CCD pixels (and the TV system CCD) in both the detection of the clock signal and the detection of the vertical synchronization signal, but only the frame rate is detected. In such a case, only the detection by the vertical synchronization signal detector 45 is sufficient.

  Further, the determination of the frame rate can be performed based on the identification information acquired from the electronic scope. However, according to the detection based on the vertical synchronization signal of the present invention, the frame rate can be directly detected. There is. In other words, the electronic scope has a lot of identification information regarding not only the frame rate but also the internal configuration and various processing conditions. Every time one configuration or condition changes, the recording contents corresponding to the identification information must be changed. It becomes complicated.

It is a circuit block diagram which shows the structure of the electronic endoscope apparatus which concerns on the Example of this invention. It is a circuit block diagram which shows the structure of the frame rate detection circuit and non-TV resolution conversion circuit of an Example (FIG. 1). It is a circuit diagram which shows the structure of the clock detection part of an Example. It is a wave form diagram of each clock signal for demonstrating operation | movement in the clock detection part of an Example. It is a circuit diagram which shows the structure of the vertical synchronizing signal detection part of an Example. It is a wave form diagram of each vertical synchronizing signal for demonstrating operation | movement in the vertical synchronizing signal detection part of an Example. It is explanatory drawing which shows pixel number conversion (resolution conversion) in the new electronic scope of an Example. It is a figure which shows the structure in the case of displaying an image on both the monitor for PC and the monitor for TV in the conventional electronic endoscope apparatus.

Explanation of symbols

10 ... electronic scope, 10A ... new electronic scope,
11 ... Processor device, 14 ... CCD,
18 ... DSP (resolution conversion circuit),
19: Image conversion circuit (resolution conversion circuit),
21 ... Timing generator,
22, 41 ... microcomputer,
28: Non-TV resolution conversion circuit,
32. Frame rate detection circuit,
35 ... Resolution conversion circuit for TV,
44: Clock detection unit,
45. Vertical synchronization signal detection unit.

Claims (4)

Various electronic scopes equipped with solid-state image sensors with different numbers of pixels,
A processor device that detachably connects these various electronic scopes and performs signal processing for outputting video signals to a display unit, and
A frame rate detection circuit for detecting a frame rate of the output video signal of the electronic scope by comparing the processor side vertical synchronization signal and the processor side vertical synchronization signal to the processor device; An electronic endoscope apparatus comprising: an image output circuit that outputs an image signal at a frame rate capable of maintaining moving image performance of various electronic scopes based on an output of a frame rate detection circuit. An electronic scope having a solid-state imaging device having a number of pixels larger than the maximum number of pixels to be displayed by the processor device and having a frame rate of an output image higher than that of the image having the maximum number of pixels on the processor side is provided. ,
The scope of the present invention is characterized in that a scope-side resolution conversion circuit for down-converting the number of pixels of the image signal output from the solid-state imaging device into the image signal having the maximum number of pixels on the processor side is provided in the electronic scope. The electronic endoscope apparatus according to 1. A TV system electronic endoscope having a TV system solid-state image sensor and a non-TV system electronic scope having a non-TV system solid-state image sensor are provided.
When the TV electronic endoscope is connected to the processor device, conversion to the number of pixels for non-TV is performed, and when the non-TV electronic scope is connected, conversion to the number of pixels for TV is performed. A resolution conversion circuit that
3. The electronic endoscope apparatus according to claim 1, wherein the image output circuit outputs an image signal at a frame rate of a non-TV display device.   The frame rate detection circuit includes a connected electronic endoscope by comparing a scope-side clock signal and a processor-side clock signal used in the electronic scope, and comparing the scope-side vertical synchronization signal and the processor-side vertical synchronization signal. 4. The electronic endoscope apparatus according to claim 3, wherein the number of pixels of the solid-state imaging device is determined.

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