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JP2005117035A - Flip-chip gallium-nitride-based semiconductor light-emitting element and method of fabricating same - Google Patents

Flip-chip gallium-nitride-based semiconductor light-emitting element and method of fabricating same Download PDF

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JP2005117035A
JP2005117035A JP2004269640A JP2004269640A JP2005117035A JP 2005117035 A JP2005117035 A JP 2005117035A JP 2004269640 A JP2004269640 A JP 2004269640A JP 2004269640 A JP2004269640 A JP 2004269640A JP 2005117035 A JP2005117035 A JP 2005117035A
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layer
semiconductor light
solder
gallium nitride
electrode
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Takashi Shoji
孝志 荘司
Takekazu Sakai
丈和 堺
Mineo Okuyama
峰夫 奥山
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Resonac Holdings Corp
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Showa Denko KK
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of fabricating a flip-chip gallium-nitride-based semiconductor light-emitting element having solder-coated electrodes, capable of downsizing a chip size. <P>SOLUTION: The fabrication method comprises steps of: forming a positive electrode of metal on the surface of a p-type semiconductor layer of a gallium-nitride-based semiconductor light-emitting element made up of n-type semiconductor layers and p-type semiconductor layers stacked alternately one by one on a substrate; then conferring adherence to a prescribed region of the surface of the positive electrode by reacting the prescribed region of the surface of the positive electrode and a composition containing an adherence-conferring compound; attaching solder powder exclusively on the adherence-conferred region; then heating and melting the solder power; and forming a solder layer on the prescribed region of the surface of the positive electrode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、フリップチップ型の窒化ガリウム系半導体発光素子に係わり、特にチップサイズの小型化に対応可能な、半田コートされた電極を有するフリップチップ型窒化ガリウム系半導体発光素子とその製造方法に関する。   The present invention relates to a flip-chip type gallium nitride semiconductor light-emitting device, and more particularly to a flip-chip type gallium nitride semiconductor light-emitting device having solder-coated electrodes and a method for manufacturing the same.

近年、回路基板の電極上に半導体発光素子の電極を直接銀ペーストや半田などにより導通固定させるフリップチップ型半導体発光素子が、導通を取るためにワイヤを用いる必要がなく、比較的簡単な工程で比較的小型な半導体発光素子を搭載できるので着目されている(例えば特許文献1および2)。また、このような小型の半導体発光素子に半田電極を形成する方法も提案されている(例えば特許文献3)。   In recent years, a flip-chip type semiconductor light emitting device in which a semiconductor light emitting device electrode is directly conductively fixed on a circuit board electrode with silver paste or solder does not require the use of a wire in order to achieve conduction, and is a relatively simple process. Since a relatively small semiconductor light emitting element can be mounted, it is attracting attention (for example, Patent Documents 1 and 2). A method of forming a solder electrode on such a small semiconductor light emitting element has also been proposed (for example, Patent Document 3).

しかし、最近、半導体発光素子の小型化に対する要求はさらに強まっており、正極・負極間隔も非常に小さくなってきている。電極間隔が小さくなると半田ブリッジによる短絡も当然発生しやすく、この短絡を安定して防ぐことができる小型のフリップチップ型半導体発光素子が求められている。特に、窒化ガリウム系半導体発光素子においてこの傾向が強い。   However, recently, the demand for downsizing of the semiconductor light emitting device has been further increased, and the distance between the positive electrode and the negative electrode has become very small. When the electrode interval is reduced, a short circuit due to a solder bridge is likely to occur, and a small flip-chip type semiconductor light emitting element capable of stably preventing this short circuit is desired. This tendency is particularly strong in gallium nitride based semiconductor light emitting devices.

特開平11−220168号公報Japanese Patent Laid-Open No. 11-220168 特開平2002−151739号公報Japanese Patent Laid-Open No. 2002-151739 特開平9−27498号公報JP-A-9-27498

本発明の目的は、半田コートされた電極を有するフリップチップ型窒化ガリウム系半導体発光素子において、チップサイズの小型化を可能とする製造方法を提供することである。本発明の別の目的は、発光層からの光に対する反射特性に優れ、p型窒化ガリウム系半導体層に対して良好なオーミック接触特性を有し、かつ表面の所定の部分に半田コートすることが可能な構造の正電極を有するフリップチップ型窒化ガリウム系半導体発光素子を提供することである。また、本発明の別の目的は、一辺が280μm以下という小型のフリップチップ型窒化ガリウム系半導体発光素子を提供することである。   An object of the present invention is to provide a manufacturing method that enables a reduction in chip size in a flip chip type gallium nitride semiconductor light emitting device having solder-coated electrodes. Another object of the present invention is to provide excellent ohmic contact characteristics with respect to the p-type gallium nitride based semiconductor layer, and to coat a predetermined portion of the surface with solder. To provide a flip-chip gallium nitride based semiconductor light emitting device having a positive electrode with a possible structure. Another object of the present invention is to provide a small flip chip type gallium nitride based semiconductor light emitting device having a side of 280 μm or less.

本発明は、以下の発明を提供する。
(1)基板上にn型半導体層およびp型半導体層を順次積層した窒化ガリウム系半導体発光素子のp型半導体層表面に金属からなる正電極を形成した後、該正電極の表面の所定の部分と粘着性付与化合物を含む組成物とを反応させることにより正電極の表面の所定の部分に粘着性を付与し、粘着性付与部分にのみ半田粉末を付着させた後、加熱して半田粉末を溶融させ、正電極の表面の所定の部分に半田層を形成することを特徴とするフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
The present invention provides the following inventions.
(1) A positive electrode made of metal is formed on the surface of a p-type semiconductor layer of a gallium nitride based semiconductor light-emitting device in which an n-type semiconductor layer and a p-type semiconductor layer are sequentially stacked on a substrate, and then a predetermined surface on the surface of the positive electrode is formed. By reacting the part with a composition containing a tackifying compound, the predetermined part of the surface of the positive electrode is given tackiness, and the solder powder is attached only to the tackifying part and then heated to solder powder. And a solder layer is formed on a predetermined portion of the surface of the positive electrode. A method for manufacturing a flip-chip gallium nitride semiconductor light emitting device, comprising:

(2)正電極が、窒化ガリウム系半導体発光素子のp型半導体層に電気的に接触しかつ発光層からの光を反射する第1電極層と、半田の拡散を防止するバリア層と、粘着性付与化合物と反応する金属からなる第2電極層とからなることを特徴とする上記(1)記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。 (2) a first electrode layer in which the positive electrode is in electrical contact with the p-type semiconductor layer of the gallium nitride based semiconductor light emitting device and reflects light from the light emitting layer, a barrier layer for preventing diffusion of solder, and an adhesive The method for producing a flip-chip gallium nitride semiconductor light-emitting device according to (1) above, comprising a second electrode layer made of a metal that reacts with a property-imparting compound.

(3)第1電極層が、Au,Ag,Pt,Pd,Rh,Alの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする上記(2)記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。 (3) The flip according to (2), wherein the first electrode layer is made of a metal selected from the group consisting of Au, Ag, Pt, Pd, Rh, and Al, or an alloy containing at least one of them. A method for manufacturing a chip-type gallium nitride semiconductor light-emitting device.

(4)バリア層が、Ni,Cr,Ti,W,Moの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする上記(2)または(3)記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。 (4) The flip described in (2) or (3) above, wherein the barrier layer is made of a metal selected from the group consisting of Ni, Cr, Ti, W, and Mo or an alloy containing at least one of them. A method for manufacturing a chip-type gallium nitride semiconductor light-emitting device.

(5)第2電極層が、Cu,Ni,Sn,Feの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする上記(2)〜(4)のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。 (5) Any one of the above (2) to (4), wherein the second electrode layer is made of a metal selected from the group consisting of Cu, Ni, Sn, and Fe or an alloy containing at least one of them. The manufacturing method of the flip chip type gallium nitride semiconductor light-emitting device according to one item.

(6)窒化ガリウム系半導体発光素子の正電極が形成された側の表面の一部にn型半導体層を露出させ、該n型半導体層に金属からなる負電極を形成した後、該負電極の表面の所定の部分と粘着性付与化合物を含む組成物とを反応させることにより負電極の表面の所定の部分に粘着性を付与し、粘着性付与部分にのみ半田粉末を付着させた後、加熱して半田粉末を溶融させ、負電極の表面の所定の部分に半田層を形成することを特徴とする上記(1)〜(5)のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。 (6) After exposing the n-type semiconductor layer to a part of the surface on the side where the positive electrode of the gallium nitride based semiconductor light-emitting element is formed and forming a negative electrode made of metal on the n-type semiconductor layer, the negative electrode After giving a predetermined portion of the surface of the negative electrode by reacting a predetermined portion of the surface and a composition containing a tackifier compound, after attaching the solder powder only to the tackified portion, The flip chip type gallium nitride system according to any one of (1) to (5) above, wherein the solder powder is melted by heating to form a solder layer on a predetermined portion of the surface of the negative electrode A method for manufacturing a semiconductor light emitting device.

(7)正電極と負電極に同時に半田層を形成することを特徴とする上記(6)記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
(8)半田層の厚さが、5〜100μmであることを特徴とする上記(1)〜(7)のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
(7) The method for manufacturing a flip-chip gallium nitride semiconductor light-emitting device according to (6), wherein a solder layer is simultaneously formed on the positive electrode and the negative electrode.
(8) The method for manufacturing a flip-chip gallium nitride semiconductor light-emitting element according to any one of (1) to (7) above, wherein the solder layer has a thickness of 5 to 100 μm.

(9)半田層の厚さが、5〜25μmであることを特徴とする上記(8)記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
(10)半導体発光素子の平面形状が、一辺200〜280μの正方形であることを特徴とする上記(1)〜(9)のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
(11)正電極および負電極の半田層の間隔が、30μm〜150μmであることを特徴とする上記(1)〜(10)のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。
(12)上記(1)〜(11)のいずれか一項に記載の製造方法で製造されたフリップチップ型窒化ガリウム半導体発光素子。
(9) The method for producing a flip-chip gallium nitride semiconductor light-emitting element according to (8) above, wherein the solder layer has a thickness of 5 to 25 μm.
(10) The planar shape of the semiconductor light-emitting element is a square having a side of 200 to 280 μm, and the flip-chip gallium nitride semiconductor light-emitting element according to any one of (1) to (9) above Production method.
(11) The flip-chip type gallium nitride semiconductor light-emitting element according to any one of (1) to (10) above, wherein the interval between the solder layers of the positive electrode and the negative electrode is 30 μm to 150 μm Manufacturing method.
(12) A flip-chip gallium nitride semiconductor light-emitting element manufactured by the manufacturing method according to any one of (1) to (11) above.

(13)正電極および負電極の表面に半田層を有するフリップチップ型窒化ガリウム系半導体発光素子において、該半田層の厚さが5〜100μmであり、正電極および負電極の半田層の間隔が30〜150μmであり、素子の平面形状が一辺200〜280μmであることを特徴とするフリップチップ型窒化ガリウム系半導体発光素子。 (13) In the flip chip type gallium nitride semiconductor light emitting device having solder layers on the surfaces of the positive electrode and the negative electrode, the thickness of the solder layer is 5 to 100 μm, and the interval between the solder layers of the positive electrode and the negative electrode is A flip-chip type gallium nitride semiconductor light emitting device having a thickness of 30 to 150 μm and a planar shape of the device of 200 to 280 μm per side.

(14)正電極が、Au,Ag,Pt,Pd,Rh,Alの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなる第1電極層、Ni,Cr,Ti,W,Moの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなるバリア層およびCu,Ni,Sn,Feの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなる第2電極層からなることを特徴とする上記(13)記載のフリップチップ型窒化ガリウム半導体発光素子。 (14) A first electrode layer in which the positive electrode is made of a metal selected from the group of Au, Ag, Pt, Pd, Rh, and Al or an alloy containing at least one of these, Ni, Cr, Ti, W, Mo A barrier layer made of a metal selected from the group consisting of metals or an alloy containing at least one of these and a second electrode layer made of a metal selected from the group consisting of Cu, Ni, Sn, Fe or an alloy containing at least one of these The flip-chip gallium nitride semiconductor light-emitting device according to (13) above, characterized in that

(15)上記(13)または(14)に記載のフリップチップ型窒化ガリウム系半導体発光素子を、回路基板の導電回路の電極と該発光素子の各半田層とが接触するようにダイボンドし、加熱して半田を溶融し、回路基板に接合することを特徴とするフリップチップ型窒化ガリウム系半導体発光素子の実装方法。 (15) The flip-chip type gallium nitride semiconductor light-emitting device according to (13) or (14) is die-bonded so that the conductive circuit electrode of the circuit board and each solder layer of the light-emitting device are in contact with each other, and heating Then, the solder is melted and bonded to the circuit board, and the flip chip type gallium nitride semiconductor light emitting device mounting method is provided.

本発明によれば、一辺の長さが280μm以下という小型のフリップチップ型窒化ガリウム系半導体発光素子を短絡発生等の不良率が少なく安定して製造することができる。その結果、ウェハ1枚当たりから得られる発光素子チップの数が増加し、生産性が向上する。また、発光素子チップが小型化する結果、発光素子を組み込んだ電子機器の小型化が可能となる。   According to the present invention, a small flip-chip type gallium nitride semiconductor light emitting device having a side length of 280 μm or less can be stably manufactured with a low defect rate such as occurrence of a short circuit. As a result, the number of light emitting element chips obtained from one wafer increases and productivity is improved. Further, as a result of downsizing of the light emitting element chip, it is possible to reduce the size of an electronic apparatus incorporating the light emitting element.

また、本発明の半導体発光素子は、正電極が発光層からの光に対する反射特性に優れ、p型の窒化ガリウム系半導体層に対して良好なオーミック接触特性を有する結果、高輝度で順方向電圧の低いフリップチップ型窒化ガリウム系半導体発光素子が得られる。   In addition, the semiconductor light emitting device of the present invention has a high luminance and a forward voltage as a result of the positive electrode having excellent reflection characteristics with respect to light from the light emitting layer and having good ohmic contact characteristics with respect to the p-type gallium nitride semiconductor layer. A flip-chip type gallium nitride semiconductor light emitting device having a low level can be obtained.

以下、図面を用いながら本発明を詳細に説明するが、本発明はこれらの図面のみに限定されない。
本発明に用いる窒化ガリウム系半導体発光素子としては、通常の方法で製造された従来公知の構造のものを何ら制限なく用いることができる。図1を用いてその一例を説明する。1は基板であり、窒化ガリウム系半導体発光素子では通常サファイアである。その上に窒化アルミニウムからなるバッファ層2が設けられ、その上にn型のGaN層3が形成されている。このn型のGaN層3の上にn型GaNからなる下部クラッド層4が形成されている。そして、下部クラッド層4の上に発光層として単一量子井戸構造(SQW)の井戸層となる活性層5が形成されている。活性層5の上にはp型のAlGaNから成る上部クラッド層6が形成されている。さらに、上部クラッド層6の上にはp型GaNから成るコンタクト層7が形成されている。
Hereinafter, the present invention will be described in detail with reference to the drawings. However, the present invention is not limited only to these drawings.
As the gallium nitride based semiconductor light emitting device used in the present invention, a conventionally known structure manufactured by a usual method can be used without any limitation. An example will be described with reference to FIG. Reference numeral 1 denotes a substrate, which is usually sapphire in a gallium nitride based semiconductor light emitting device. A buffer layer 2 made of aluminum nitride is provided thereon, and an n-type GaN layer 3 is formed thereon. A lower cladding layer 4 made of n-type GaN is formed on the n-type GaN layer 3. An active layer 5 serving as a well layer of a single quantum well structure (SQW) is formed on the lower cladding layer 4 as a light emitting layer. An upper cladding layer 6 made of p-type AlGaN is formed on the active layer 5. Further, a contact layer 7 made of p-type GaN is formed on the upper clad layer 6.

正電極はコンタクト層7の上に形成する。正電極は蒸着法またはスパッタ法等従来公知の方法によって形成できる。好ましくは、半導体側に金(Au)、銀(Ag)、白金(Pt)、ロジウム(Rh)、パラジウム(Pd)、アルミニウム(Al)またはそれらを含む合金からなる第1電極層を有し、その上にニッケル(Ni)、銅(Cu)、錫(Sn)、鉄(Fe)またはそれらの合金からなる第2電極層を有する。第1電極層はp型半導体層と電気的に接触し、また発光素子の発光部からの光を効率良く反射する反射層として機能し、従って、サファイア基板側から効率よく光を取り出すことができる。第2電極層は半田との濡れ性が良好で半田食われの小さな材料であり、半田との結合を良好に保つ機能を有する。また第2電極層は粘着性付与化合物を含む組成物と反応することにより、その表面に粘着性が付与される。第1電極層の厚さは、50〜1000nmが好ましい。第2電極層の厚さは、0.1〜2μmが好ましく、0.5μm以上あることがさらに好ましい。   The positive electrode is formed on the contact layer 7. The positive electrode can be formed by a conventionally known method such as vapor deposition or sputtering. Preferably, the semiconductor side has a first electrode layer made of gold (Au), silver (Ag), platinum (Pt), rhodium (Rh), palladium (Pd), aluminum (Al) or an alloy containing them, A second electrode layer made of nickel (Ni), copper (Cu), tin (Sn), iron (Fe) or an alloy thereof is formed thereon. The first electrode layer is in electrical contact with the p-type semiconductor layer, and functions as a reflective layer that efficiently reflects light from the light emitting portion of the light emitting element, and thus can efficiently extract light from the sapphire substrate side. . The second electrode layer is a material that has good wettability with solder and little solder erosion, and has a function of maintaining good bonding with the solder. In addition, the second electrode layer reacts with the composition containing the tackifier compound, thereby imparting tackiness to the surface thereof. The thickness of the first electrode layer is preferably 50 to 1000 nm. The thickness of the second electrode layer is preferably 0.1 to 2 μm, and more preferably 0.5 μm or more.

第1電極層と半導体層との間に、接触抵抗を下げるためのAu−Ni酸化物またはAu−Co酸化物等からなる透光性の薄膜電極を挿入しても良い。この場合、第1電極層は薄膜電極を介してp型半導体層と電気的に接触する。   A light-transmitting thin film electrode made of Au—Ni oxide or Au—Co oxide for reducing contact resistance may be inserted between the first electrode layer and the semiconductor layer. In this case, the first electrode layer is in electrical contact with the p-type semiconductor layer through the thin film electrode.

第1電極層と第2電極層との間に、半田の拡散を防止するための半田バリアメタルとしてチタン(Ti)、クロム(Cr)、タングステン(W)、モリブデン(Mo)、ニッケル(Ni)またはそれらの合金からなるバリア層を挿入することが好ましい。但し、上記第2電極層がNiである場合は、バリア層はNi以外の金属とすることが望ましい。半田の拡散防止のためには、バリア層の厚さは100〜1000nm程度とするのが望ましい。   Titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), nickel (Ni) as a solder barrier metal for preventing the diffusion of solder between the first electrode layer and the second electrode layer Or it is preferable to insert the barrier layer which consists of those alloys. However, when the second electrode layer is Ni, the barrier layer is preferably a metal other than Ni. In order to prevent solder diffusion, the thickness of the barrier layer is preferably about 100 to 1000 nm.

負電極は、窒化ガリウム系半導体発光素子の表面の所定の位置のコンタクト層7、上部クラッド層6、活性層5および下部クラッド層4を除去し、露出したn型のGaN層3の上に従来公知の蒸着法またはスパッタ法等により形成する。負電極の材料としては、従来公知の如何なる材料も用いることができるが、半導体と接触良好な第1電極層をバナジウム(V)とアルミニウム(Al)、タングステン(W)とアルミニウム(Al)、またはチタン(Ti)と金(Au)の合金ないし積層構造から作製し、その上に半田層を形成するための第2電極層として、ニッケル(Ni)、銅(Cu)、錫(Sn)、鉄(Fe)またはそれらの合金からなる層を設けた構造が好ましい。第1電極層の厚さは50〜1000nmが好ましい。第2電極層の厚さは一般に正電極と同様である。負電極の第1電極層と第2電極層との間にも、正電極の場合と同様に半田の拡散を防止するためのバリア層を挿入することが好ましい。   The negative electrode is formed by removing the contact layer 7, the upper cladding layer 6, the active layer 5 and the lower cladding layer 4 at predetermined positions on the surface of the gallium nitride based semiconductor light emitting device, and on the exposed n-type GaN layer 3. It is formed by a known vapor deposition method or sputtering method. As the material of the negative electrode, any conventionally known material can be used, but the first electrode layer in good contact with the semiconductor is made of vanadium (V) and aluminum (Al), tungsten (W) and aluminum (Al), or As a second electrode layer for producing a solder layer on the alloy or laminated structure of titanium (Ti) and gold (Au), nickel (Ni), copper (Cu), tin (Sn), iron The structure provided with the layer which consists of (Fe) or those alloys is preferable. The thickness of the first electrode layer is preferably 50 to 1000 nm. The thickness of the second electrode layer is generally the same as that of the positive electrode. It is preferable to insert a barrier layer between the first electrode layer and the second electrode layer of the negative electrode, as in the case of the positive electrode, for preventing the diffusion of solder.

正電極および負電極の第2電極層は、それぞれ第1電極層またはバリア層上で任意の平面配置を取ることが出来る。例えば、正電極のバリア層の表面に複数個の第2電極層を離して設け、その上に半田層を形成することが可能である。発光素子が小型になればなるほど、正電極および負電極の各半田層の間隔は小さくなり、両電極間の短絡(半田ブリッジ)が発生し易くなる。従って、正負両半田層の間隔がなるべく大きくなり、かつ半導体層中での電流密度が均一となるように、小さな平面の中で正負の両半田層即ち第2電極層を配置することが重要である。   The second electrode layers of the positive electrode and the negative electrode can each have an arbitrary planar arrangement on the first electrode layer or the barrier layer. For example, it is possible to dispose a plurality of second electrode layers on the surface of the barrier layer of the positive electrode and form a solder layer thereon. The smaller the light emitting element, the smaller the spacing between the solder layers of the positive electrode and the negative electrode, and the more likely that a short circuit (solder bridge) occurs between the two electrodes. Therefore, it is important to arrange both the positive and negative solder layers, that is, the second electrode layer in a small plane so that the distance between the positive and negative solder layers is as large as possible and the current density in the semiconductor layer is uniform. is there.

図2〜5は本発明の発光素子における電極の配置の一例である。正電極は、発光層からの光を効率よく基板側に反射するために、負電極を形成した部分を除いたコンタクト層表面のほぼ全面に形成する。負電極は、回路基板への実装を可能とするために、直径50〜150μm程度の大きさで形成する。図2は正負の半田層を対角線状に配置した例であり、正電極の半田層は底辺および高さが50〜150μmの直角二等辺三角形である。図3は負電極とその半田層を上辺の中央部に、正電極の半田層を正電極の下辺全長に亙って20〜100μmの高さで設けてある。図4および図5は複数の正電極の半田層を設けた例で、直径50〜100μmの半田層が2つ図に示したような配置で設けてある。   2 to 5 are examples of electrode arrangement in the light-emitting element of the present invention. The positive electrode is formed on almost the entire surface of the contact layer excluding the portion where the negative electrode is formed in order to efficiently reflect the light from the light emitting layer to the substrate side. The negative electrode is formed with a diameter of about 50 to 150 μm in order to enable mounting on a circuit board. FIG. 2 shows an example in which positive and negative solder layers are arranged diagonally. The solder layer of the positive electrode is a right isosceles triangle having a base and a height of 50 to 150 μm. In FIG. 3, the negative electrode and its solder layer are provided at the center of the upper side, and the positive electrode solder layer is provided at a height of 20 to 100 μm along the entire lower side of the positive electrode. 4 and 5 show an example in which a plurality of positive electrode solder layers are provided, and two solder layers having a diameter of 50 to 100 μm are provided as shown in the drawing.

正負の半田層をこのような配置にすることにより、発光素子を一辺が200〜280μmの正方形という大きさにしても、正負の半田層の間隔を150μm程度まで確保することが可能である。半田ブリッジの発生を防止するためには、正負の半田層の間隔は、少なくとも30μm以上、望ましくは50μm以上必要である。   By arranging the positive and negative solder layers in such a manner, it is possible to secure the interval between the positive and negative solder layers up to about 150 μm even if the light emitting element is a square having a side of 200 to 280 μm. In order to prevent the occurrence of solder bridges, the interval between the positive and negative solder layers needs to be at least 30 μm or more, preferably 50 μm or more.

半田層の厚さを薄くすることも半田ブリッジの発生防止には重要である。半田層の範囲を5〜100μmの範囲に、特に25μm以下にすると、高精細な電極パターンに半田層を形成した場合も、正負の電極間の短絡(半田ブリッジ)の発生を防止できて好ましい。望ましくは20μm以下である。その結果、正電極および負電極の半田層の間隔を150μm以下とすることができる。あまり薄すぎると装着する回路基板電極との接触不良が起きるので、少なくとも5μm以上、好ましくは10μm以上必要である。   Reducing the thickness of the solder layer is also important for preventing the occurrence of solder bridges. When the solder layer is in the range of 5 to 100 μm, particularly 25 μm or less, even when the solder layer is formed on a high-definition electrode pattern, the occurrence of a short circuit (solder bridge) between the positive and negative electrodes is preferable. Desirably, it is 20 μm or less. As a result, the interval between the positive electrode and negative electrode solder layers can be made 150 μm or less. If it is too thin, contact failure with the circuit board electrode to be mounted will occur, so at least 5 μm or more, preferably 10 μm or more is required.

正電極および負電極の半田層の間隔を150μm以下とすることができる結果、一辺を280μm以下とする正方形の半導体発光素子を製造することが出来る。但し、半田ブリッジを避けるため、発光素子の一辺の長さは200μm以上であるのが望ましい。   As a result of the interval between the positive and negative electrode solder layers being 150 μm or less, a square semiconductor light emitting device having one side of 280 μm or less can be manufactured. However, in order to avoid a solder bridge, the length of one side of the light emitting element is preferably 200 μm or more.

半導体素子の表面を保護する保護膜は有っても無くても良い。保護膜を設ける場合は半田層以外を全て覆ってもよいし、半導体のp−n接合部のみ覆ってもよい。   There may or may not be a protective film for protecting the surface of the semiconductor element. In the case of providing a protective film, all except the solder layer may be covered, or only the pn junction part of the semiconductor may be covered.

半田層の形成方法には、メッキ法、蒸着法、ディップ法と各種あるが、本発明では、前記特許文献3に開示されている、電極の所定部分に粘着性を付与し、その部分のみに半田粉末を付着させ、加熱溶融する方法を用いる。   There are various methods for forming the solder layer, such as a plating method, a vapor deposition method, and a dipping method. In the present invention, a predetermined part of the electrode disclosed in Patent Document 3 is given adhesiveness, and only that part is provided. A method in which solder powder is attached and heated and melted is used.

金属電極表面の特定部分に粘着性を付与するためには、表面の金属と作用して粘着性を発現する化合物で電極表面を処理する。その化合物としては、例えば、第2電極層を構成する金属であるCu、Ni、Sn、Feと反応して粘着性を発現するベンゾトリアゾール系誘導体、ナフトトリアゾール系誘導体、イミダゾール系誘導体、ベンゾイミダゾール系誘導体、メルカプトベンゾチアゾール系誘導体、ベンゾチアゾールチオ脂肪酸系誘導体などを含む水溶液を用いる。前記水溶液は酸性、好ましくはpH3〜5程度の微酸性に調整し、濃度は0.05〜20質量%が好ましい。さらに銅イオンを100〜1000ppm程度共存させると、粘着性膜の生成速度、生成量などの生成効率が高まるので好ましい。   In order to impart adhesiveness to a specific portion of the metal electrode surface, the electrode surface is treated with a compound that acts on the surface metal and develops adhesiveness. Examples of the compound include benzotriazole derivatives, naphthotriazole derivatives, imidazole derivatives, and benzimidazole derivatives that react with Cu, Ni, Sn, and Fe, which are metals constituting the second electrode layer, to exhibit adhesiveness. An aqueous solution containing a derivative, a mercaptobenzothiazole derivative, a benzothiazole thiofatty acid derivative, or the like is used. The aqueous solution is adjusted to be acidic, preferably slightly acidic with a pH of about 3 to 5, and the concentration is preferably 0.05 to 20% by mass. Furthermore, it is preferable to coexist about 100 to 1000 ppm of copper ions because the production efficiency such as the production rate and production amount of the adhesive film is increased.

金属電極の処理方法は前記のように調整した水溶液を、浸漬法、塗布法、スプレー法などの手段を用いて金属露出部に接触させる。金属電極上でも半田の不要な部分はレジスト膜等で覆って、金属面に粘着性が付与されないようにしておくのが好ましい。処理温度は室温〜60℃位の範囲が良い。接触時間は5秒〜5分間位の範囲で適宜選択する。次に適宜溶媒による洗浄、乾燥を経れば金属露出部にのみ粘着性が付与される。粘着性を付与された金属電極表面に半田粉末を振りかけ付着させ、余分な半田を圧力空気で吹き飛ばしたり湿式洗浄などにより取り除けば、金属電極表面の必要な部分だけに半田粉末が残る。   In the method for treating the metal electrode, the aqueous solution prepared as described above is brought into contact with the exposed metal portion by means of a dipping method, a coating method, a spray method or the like. Even on the metal electrode, it is preferable to cover an unnecessary portion of the solder with a resist film or the like so that the metal surface is not provided with adhesiveness. The treatment temperature is preferably in the range of room temperature to about 60 ° C. The contact time is appropriately selected within a range of about 5 seconds to 5 minutes. Next, if washing and drying with a solvent are performed as appropriate, tackiness is imparted only to the exposed metal portion. If solder powder is sprinkled and adhered to the surface of the metal electrode to which the adhesive has been imparted, and excess solder is blown off with pressurized air or removed by wet cleaning or the like, the solder powder remains only on the necessary portion of the metal electrode surface.

半田粉末は、一般的に使用されている共晶半田、銀入り半田、ビスマス入り半田等で構わない。例えば、Sn−Ag−Cu系、Sn−Bi系、Sn−Pb系およびIn−Pb系等の半田を用いることができる。半田粉末の粒度は目標とする半田層厚に応じて5μm〜数十μmの間で適宜選択すれば良い。   The solder powder may be a commonly used eutectic solder, silver-containing solder, bismuth-containing solder, or the like. For example, Sn-Ag-Cu-based, Sn-Bi-based, Sn-Pb-based, and In-Pb-based solders can be used. The particle size of the solder powder may be appropriately selected between 5 μm and several tens of μm according to the target solder layer thickness.

その後、半田を電極表面に加熱定着させて、微量な半田粉末を取り除き、市販のフラックスを塗布後加熱して半田を溶解させれば金属電極の所定の部分のみに半田層がある正電極および負電極が形成される。   After that, solder is fixed on the electrode surface to remove a small amount of solder powder, and after applying a commercially available flux and heating to dissolve the solder, positive and negative electrodes with a solder layer only on a predetermined part of the metal electrode. An electrode is formed.

次に、通常のダイシングソーやスクライブ法などによりウェーハを切断し個別の素子に分離する。半導体発光素子は分離後回路基板やリードフレームにダイボンドし、加熱して半田層を溶解し接合させて実装する。   Next, the wafer is cut and separated into individual elements by a normal dicing saw or a scribe method. The semiconductor light emitting device is die-bonded to a circuit board or a lead frame after being separated, and heated to melt and bond the solder layer for mounting.

以下、本発明の内容を実施例により具体的に説明するが、本発明はこの実施例のみに限定されるわけではない。   Hereinafter, the content of the present invention will be described in detail with reference to examples, but the present invention is not limited to these examples.

図1に示したフリップチップ型窒化ガリウム半導体発光素子を作成した。用いた窒化ガリウム半導体の構成を下記に示す。   The flip chip type gallium nitride semiconductor light emitting device shown in FIG. 1 was produced. The structure of the gallium nitride semiconductor used is shown below.

基板1にはサファイアを用い、その上には窒化アルミニウムガリウム(GaAlN)から成る膜厚約200Åのバッファ層2を設け、その上にn型のGaN層としてシリコン(Si)ドープのGaNから成る膜厚約4.0μmの高キャリア濃度n+層3を形成した。この高キャリア濃度n+層3の上にSiドープのn型GaNから成る膜厚約0.5μmのn型のGaN下部クラッド層4を形成した。そして、下部クラッド層4の上に単一量子井戸構造(SQW)の井戸層に相当する膜厚約50ÅのGaInNからなる活性層5を発光層として形成した。活性層5の上にはp型Al0.15Ga0.85Nから成る膜厚約600Åのp型AlGaN上部クラッド層6を形成した。さらに、上部クラッド層6の上にはp型GaNから成る膜厚約1500Åのコンタクト層7を形成した。 The substrate 1 is made of sapphire, on which a buffer layer 2 made of aluminum gallium nitride (GaAlN) is formed with a thickness of about 200 mm, and a silicon (Si) -doped GaN film is formed thereon as an n-type GaN layer. A high carrier concentration n + layer 3 having a thickness of about 4.0 μm was formed. On this high carrier concentration n + layer 3, an n-type GaN lower cladding layer 4 made of Si-doped n-type GaN and having a thickness of about 0.5 μm was formed. Then, an active layer 5 made of GaInN having a thickness of about 50 mm corresponding to a well layer of a single quantum well structure (SQW) was formed on the lower cladding layer 4 as a light emitting layer. A p-type AlGaN upper cladding layer 6 made of p-type Al 0.15 Ga 0.85 N and having a thickness of about 600 mm was formed on the active layer 5. Further, a contact layer 7 made of p-type GaN and having a thickness of about 1500 mm was formed on the upper clad layer 6.

この窒化ガリウム半導体の製造方法について説明する。上記窒化ガリウム半導体は、有機金属化学気相堆積法(MOCVD法)による気相成長により製造した。用いたガスは、アンモニア(NH3)、キャリアガス(H2,N2)、トリメチルガリウム(Ga(CH33)(以下「TMG」と記す)、トリメチルアルミニウム(Al(CH33)(以下「TMA」と記す)、トリメチルインジウム(In(CH33)(以下「TMI」と記す)、シラン(SiH4)とシクロペンタジエニルマグネシウム(Mg(C552)(以下「CP2Mg」と記す)である。まず、有機洗浄及び熱処理により洗浄したa面を主面としたサファイア基板1をサセプタに装着し、MOCVD装置の反応室に載置した。次に、常圧でH2を反応室に流しながら温度1150℃で基板1をベーキングした。次に、基板1の温度を400℃まで低下させて、H2、NH3、TMG及びTMAを供給してAlGaNのバッファ層2を約200Åの膜厚に形成した。 A method for manufacturing this gallium nitride semiconductor will be described. The gallium nitride semiconductor was manufactured by vapor phase growth by metal organic chemical vapor deposition (MOCVD method). The gases used were ammonia (NH 3 ), carrier gas (H 2 , N 2 ), trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), trimethylaluminum (Al (CH 3 ) 3 ). (Hereinafter referred to as “TMA”), trimethylindium (In (CH 3 ) 3 ) (hereinafter referred to as “TMI”), silane (SiH 4 ) and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ) ( (Hereinafter referred to as “CP2Mg”). First, the sapphire substrate 1 having the main surface of the surface a cleaned by organic cleaning and heat treatment was mounted on a susceptor and placed in a reaction chamber of an MOCVD apparatus. Next, the substrate 1 was baked at a temperature of 1150 ° C. while flowing H 2 into the reaction chamber at normal pressure. Next, the temperature of the substrate 1 was lowered to 400 ° C., and H 2 , NH 3 , TMG and TMA were supplied to form the AlGaN buffer layer 2 with a thickness of about 200 mm.

次に、基板1の温度を1150℃にまで上げ、H2、NH3、TMG及びシランを供給し、膜厚約4.0μm、電子濃度2×1018/cm3のシリコン(Si)ドープのGaNから成る高キャリア濃度n+層3を形成した。次に、基板1の温度を1100℃に保持し、H2、NH3、TMG及びシランを供給して、膜厚約0.5μm、電子濃度1×1018/cm3のシリコン(Si)ドープのGaNから成る下部クラッド層4を形成した。上記の下部クラッド層4を形成した後、結晶温度を850℃に降温し、H2、NH3、TMG及びTMIを供給して、膜厚約50ÅのGa0.8In0.2Nから成る活性層5を形成した。 Next, the temperature of the substrate 1 is raised to 1150 ° C., H 2 , NH 3 , TMG and silane are supplied, and the silicon (Si) -doped film having a film thickness of about 4.0 μm and an electron concentration of 2 × 10 18 / cm 3 is supplied. A high carrier concentration n + layer 3 made of GaN was formed. Next, the temperature of the substrate 1 is kept at 1100 ° C., H 2 , NH 3 , TMG and silane are supplied, and the silicon (Si) doping is performed with a film thickness of about 0.5 μm and an electron concentration of 1 × 10 18 / cm 3. A lower clad layer 4 made of GaN was formed. After forming the lower cladding layer 4, the crystal temperature is lowered to 850 ° C., H 2 , NH 3 , TMG and TMI are supplied to form an active layer 5 made of Ga 0.8 In 0.2 N having a thickness of about 50 mm. Formed.

次に、基板1の温度を1000℃に昇温し、H2、NH3、TMG、TMA及びCP2Mgを供給して、膜厚約50nm、マグネシウム(Mg)をドープしたp型Al0.15Ga0.85Nから成る上部クラッド層6を形成した。次に、基板1の温度を1000℃に保持し、H2、NH3、TMG及びCP2Mgを供給して、膜厚約100nm、Mgをドープしたp型GaNから成るコンタクト層7を形成した。 Next, the temperature of the substrate 1 is raised to 1000 ° C., and H 2 , NH 3 , TMG, TMA, and CP 2 Mg are supplied, and a p-type Al 0.15 Ga 0.85 N doped with magnesium (Mg) with a film thickness of about 50 nm. An upper clad layer 6 made of Next, the temperature of the substrate 1 was maintained at 1000 ° C., and H 2 , NH 3 , TMG and CP2Mg were supplied to form a contact layer 7 made of p-type GaN doped with Mg and having a thickness of about 100 nm.

次に用いた電極の構成を示す。
コンタクト層7の上には白金(Pt)層からなる正電極の第1電極層11を、またn+層3上には負電極の第1電極層21を形成した。正電極の第1電極層は、コンタクト層7に接合する膜厚約1000Åの白金層である。負電極の第1電極層21は、膜厚約200Åのチタン(Ti)層と膜厚約1000Åの金(Au)層との二層構造で、高キャリア濃度n+層3の一部露出された部分の上に順次積層している。
Next, the structure of the electrode used is shown.
A positive electrode first electrode layer 11 made of a platinum (Pt) layer was formed on the contact layer 7, and a negative electrode first electrode layer 21 was formed on the n + layer 3. The first electrode layer of the positive electrode is a platinum layer having a thickness of about 1000 mm and bonded to the contact layer 7. The first electrode layer 21 of the negative electrode has a two-layer structure of a titanium (Ti) layer having a thickness of about 200 mm and a gold (Au) layer having a thickness of about 1000 mm, and a part of the high carrier concentration n + layer 3 is exposed. It is laminated sequentially on the part.

正電極および負電極の第1電極層表面全面には、半田の拡散を防止するための厚さ300nmのCrからなるバリア層がある。   A barrier layer made of Cr having a thickness of 300 nm is provided on the entire surface of the first electrode layer of the positive electrode and the negative electrode to prevent the diffusion of solder.

さらに正電極および負電極のバリア層上の所定の位置には、半田を付着させるための銅(Cu)からなる第2電極層がある。図6は電極の配置を示した図である。発光素子の大きさは一辺が280μmの正方形である。負電極の大きさは半径100μmの1/4円である。正電極の第2電極層および半田層は直径40μmの円形で4つあり、図に示した如くそれぞれ対角線上に等間隔で存在している。負電極の半田層と正電極の中央の半田層と間隔は80μmである。第2電極層の厚さは正電極および負電極共に0.6μmである。   Further, there is a second electrode layer made of copper (Cu) for attaching solder at predetermined positions on the barrier layers of the positive electrode and the negative electrode. FIG. 6 shows the arrangement of the electrodes. The size of the light emitting element is a square having a side of 280 μm. The size of the negative electrode is a quarter circle with a radius of 100 μm. The second electrode layer and the solder layer of the positive electrode are four circular with a diameter of 40 μm, and are present on the diagonal line at equal intervals as shown in the figure. The distance between the solder layer of the negative electrode and the solder layer at the center of the positive electrode is 80 μm. The thickness of the second electrode layer is 0.6 μm for both the positive electrode and the negative electrode.

上記構成の電極は次のようにして形成した。
コンタクト層7の上にエッチングマスクを形成し、所定領域のマスクを除去して、マスクで覆われていない部分のコンタクト層7、上部クラッド層6、活性層5、下部クラッド層4、n+層3の一部を塩素を含むガスによる反応性イオンエッチングによりエッチングして、n+層3の表面を露出させた。
The electrode having the above configuration was formed as follows.
An etching mask is formed on the contact layer 7, the mask in a predetermined region is removed, and the contact layer 7, the upper cladding layer 6, the active layer 5, the lower cladding layer 4, and the n + layer are not covered with the mask. A part of 3 was etched by reactive ion etching with a gas containing chlorine to expose the surface of the n + layer 3.

フォトレジストを塗布し、フォトリソグラフィによりn+層3の露出面上の所定領域に窓を形成して、蒸着装置を真空に排気した後、膜厚約200Åのチタン(Ti)層と膜厚約1000Åの金(Au)層を順次蒸着した。次に、フォトレジストを除去する。これによりn+層3の露出面上に負電極の第1電極層21を形成した。 A photoresist is applied, a window is formed in a predetermined region on the exposed surface of the n + layer 3 by photolithography, and the deposition apparatus is evacuated to vacuum, and then a titanium (Ti) layer having a thickness of about 200 mm and a thickness of about A 1000 金 gold (Au) layer was sequentially deposited. Next, the photoresist is removed. As a result, a negative electrode first electrode layer 21 was formed on the exposed surface of the n + layer 3.

次に、表面上にフォトレジストを一様に塗布して、フォトリソグラフィにより、コンタクト層7上の正電極の第1電極層形成部分のフォトレジストを除去して、窓部を形成する。そして、スパッタリング装置にて、フォトレジスト及び露出させたコンタクト層7上に、膜厚約1000Åの白金(Pt)層を成膜し、フォトレジストを除去する。これによりコンタクト層表面の正電極形成部に正電極の第1電極層が形成される。   Next, a photoresist is uniformly applied on the surface, and the photoresist in the first electrode layer forming portion of the positive electrode on the contact layer 7 is removed by photolithography to form a window portion. Then, a platinum (Pt) layer having a thickness of about 1000 mm is formed on the photoresist and the exposed contact layer 7 by a sputtering apparatus, and the photoresist is removed. Thereby, the first electrode layer of the positive electrode is formed on the positive electrode forming portion on the contact layer surface.

次に、表面上にフォトレジストを一様に塗布して、フォトリソグラフィにより、正電極および負電極の第1電極層上のフォトレジストを除去して、窓部を形成する。そして蒸着により、膜厚約300nmのクロム層をフォトレジスト及び露出させた正電極および負電極の第1電極層上に成膜する。次にフォトレジストを除去する。これにより正電極および負電極の第1電極層露出面上に半田バリアとして機能するCrからなるバリア層が形成される。   Next, a photoresist is uniformly applied on the surface, and the photoresist on the first electrode layer of the positive electrode and the negative electrode is removed by photolithography to form a window portion. Then, a chromium layer having a thickness of about 300 nm is formed on the photoresist and the exposed first electrode layer of the positive electrode and the negative electrode by vapor deposition. Next, the photoresist is removed. Thereby, a barrier layer made of Cr functioning as a solder barrier is formed on the exposed surface of the first electrode layer of the positive electrode and the negative electrode.

さらに再度表面上にフォトレジストを一様に塗布して、フォトリソグラフィにより、正電極および負電極のバリア層上のフォトレジストを半田コートする部分の形状に除去して、窓部を形成する。そして膜厚約0.6μmの銅(Cu)層を、フォトレジスト及び露出させたバリア層上に蒸着により成膜し、フォトレジストを除去する。これによりバリア層表面の半田コートする部分にCuからなる第2電極層が形成される。   Further, a photoresist is uniformly applied again on the surface, and the photoresist on the positive electrode and negative electrode barrier layers is removed by soldering into the shape of a solder-coated portion to form a window portion. Then, a copper (Cu) layer having a thickness of about 0.6 μm is formed on the photoresist and the exposed barrier layer by vapor deposition, and the photoresist is removed. As a result, a second electrode layer made of Cu is formed on the solder-coated portion of the barrier layer surface.

その後、エレクトロンビーム蒸着により、最上層に一様にSiO2より成る保護膜30を形成し、フォトレジストの塗布、フォトリソグラフィー工程を経てウエットエッチングにより、正負の第2電極層以外の露出部分に、SiO2膜より成る保護膜30を形成する。 Thereafter, a protective film 30 made of SiO 2 is uniformly formed on the uppermost layer by electron beam vapor deposition, and is exposed to an exposed portion other than the positive and negative second electrode layers by wet coating through a photoresist coating and photolithography process. A protective film 30 made of a SiO 2 film is formed.

次に、ウェーハを酢酸によりpHを約4に調整した2−ドデシルイミダゾ−ル(1wt%)水溶液に45℃で5分間浸漬させ、その後、水洗、乾燥を行い、正負の第2電極層の表面に粘着性を付与した。平均粒径20μmの共晶半田粉末を振りかけ、余分な半田を圧力空気で吹き飛ばした。その後、140℃で20分間半田を電極表面に加熱定着させた。微量な半田粉末をブラシで取り除き、市販の水溶性フラックスを塗布後、230℃で1分間リフロー炉に入れ半田粉末を溶融した。第2電極層の表面に厚さ約15μmの微細な半田層が形成された。   Next, the wafer is immersed in a 2-dodecylimidazole (1 wt%) aqueous solution adjusted to a pH of about 4 with acetic acid at 45 ° C. for 5 minutes, then washed with water and dried, and the surface of the positive and negative second electrode layers Was given tackiness. Eutectic solder powder with an average particle size of 20 μm was sprinkled and excess solder was blown off with pressurized air. Thereafter, the solder was fixed on the electrode surface by heating at 140 ° C. for 20 minutes. A small amount of solder powder was removed with a brush, and after applying commercially available water-soluble flux, the solder powder was melted in a reflow oven at 230 ° C. for 1 minute. A fine solder layer having a thickness of about 15 μm was formed on the surface of the second electrode layer.

ウェーハを粘着シートに貼り付け、ダイシングソーにより280μmピッチで切断しフリップチップ型窒化ガリウム系半導体発光素子とした。分離後、この発光素子を回路基板(プリント基板)の導電回路の電極と発光素子の各半田層とが接触するようにダイボンドし、リフロ−炉で230℃で1分間加熱し半田を溶融し回路基板に接合して実装した。   The wafer was attached to an adhesive sheet and cut with a dicing saw at a pitch of 280 μm to obtain a flip chip type gallium nitride semiconductor light emitting device. After the separation, the light emitting element is die-bonded so that the conductive circuit electrode of the circuit board (printed circuit board) and each solder layer of the light emitting element are in contact with each other, and heated in a reflow furnace at 230 ° C. for 1 minute to melt the solder and circuit. Bonded to the substrate and mounted.

この試料200個について通電試験を実施した。本方法で得られたフリップチップ型窒化ガリウム系半導体発光素子では短絡または断線の不良率は0%であった。
また、この発光素子の20mA通電時の輝度は平均で5.2mW、順方向電圧は3.4Vであり、高輝度で順方向電圧の低い発光素子が得られた。
An energization test was performed on 200 samples. In the flip-chip type gallium nitride semiconductor light-emitting device obtained by this method, the defect rate of short circuit or disconnection was 0%.
In addition, the luminance of this light-emitting element at 20 mA energization was 5.2 mW on average and the forward voltage was 3.4 V, and a light-emitting element with high luminance and low forward voltage was obtained.

本発明によって提供される小型のフリップチップ型窒化ガリウム系半導体発光素子は、青色発光素子として各種インジケータ等の電子機器に有用である。   The small flip-chip gallium nitride semiconductor light-emitting device provided by the present invention is useful as a blue light-emitting device for electronic devices such as various indicators.

本発明のフリップチップ型窒化ガリウム系半導体発光素子の一例の断面図である。It is sectional drawing of an example of the flip chip type gallium nitride semiconductor light-emitting device of this invention. 本発明の発光素子における電極配置の一例を示す図である。It is a figure which shows an example of electrode arrangement | positioning in the light emitting element of this invention. 本発明の発光素子における電極配置の別の例を示す図である。It is a figure which shows another example of the electrode arrangement | positioning in the light emitting element of this invention. 本発明の発光素子における電極配置の別の例を示す図である。It is a figure which shows another example of the electrode arrangement | positioning in the light emitting element of this invention. 本発明の発光素子における電極配置の別の例を示す図である。It is a figure which shows another example of the electrode arrangement | positioning in the light emitting element of this invention. 実施例で製造したフリップチップ型窒化ガリウム系半導体発光素子の電極配置を示す図である。It is a figure which shows electrode arrangement | positioning of the flip chip type gallium nitride semiconductor light-emitting device manufactured in the Example.

符号の説明Explanation of symbols

1 サファイア基板
2 AlNバッファ層
3 n型のGaN層
4 n型のGaN下部クラッド層
5 活性層
6 p型のAlGaN上部クラッド層
7 p型のGaNコンタクト層
10 正電極
11 第1電極層
12 バリア層
13 第2電極層
14 半田層
20 負電極
21 第1電極層
22 バリア層
23 第2電極層
24 半田層
30 保護膜
DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 AlN buffer layer 3 n-type GaN layer 4 n-type GaN lower cladding layer 5 active layer 6 p-type AlGaN upper cladding layer 7 p-type GaN contact layer 10 positive electrode 11 first electrode layer 12 barrier layer 13 Second electrode layer 14 Solder layer 20 Negative electrode 21 First electrode layer 22 Barrier layer 23 Second electrode layer 24 Solder layer 30 Protective film

Claims (15)

基板上にn型半導体層およびp型半導体層を順次積層した窒化ガリウム系半導体発光素子のp型半導体層表面に金属からなる正電極を形成した後、該正電極の表面の所定の部分と粘着性付与化合物を含む組成物とを反応させることにより正電極の表面の所定の部分に粘着性を付与し、粘着性付与部分にのみ半田粉末を付着させた後、加熱して半田粉末を溶融させ、正電極の表面の所定の部分に半田層を形成することを特徴とするフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   A positive electrode made of metal is formed on the surface of a p-type semiconductor layer of a gallium nitride based semiconductor light-emitting device in which an n-type semiconductor layer and a p-type semiconductor layer are sequentially stacked on a substrate, and then adhered to a predetermined portion of the surface of the positive electrode. By reacting with a composition containing a tackifier compound, the predetermined portion of the surface of the positive electrode is imparted with tackiness, and after the solder powder is attached only to the tackifier portion, heating is performed to melt the solder powder. A method of manufacturing a flip chip type gallium nitride semiconductor light emitting device, comprising forming a solder layer on a predetermined portion of the surface of the positive electrode. 正電極が、窒化ガリウム系半導体発光素子のp型半導体層に電気的に接触しかつ発光層からの光を反射する第1電極層と、半田の拡散を防止するバリア層と、粘着性付与化合物と反応する金属からなる第2電極層とからなることを特徴とする請求項1記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   A first electrode layer in which the positive electrode is in electrical contact with the p-type semiconductor layer of the gallium nitride based semiconductor light emitting device and reflects light from the light emitting layer; a barrier layer for preventing diffusion of solder; and a tackifying compound 2. The method of manufacturing a flip chip type gallium nitride based semiconductor light emitting device according to claim 1, wherein the second electrode layer is made of a metal that reacts with the second electrode layer. 第1電極層が、Au,Ag,Pt,Pd,Rh,Alの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする請求項2記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   3. The flip-chip gallium nitride according to claim 2, wherein the first electrode layer is made of a metal selected from the group consisting of Au, Ag, Pt, Pd, Rh, and Al or an alloy containing at least one of these metals. For manufacturing a semiconductor light emitting device. バリア層が、Ni,Cr,Ti,W,Moの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする請求項2または3記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   4. The flip-chip gallium nitride semiconductor according to claim 2, wherein the barrier layer is made of a metal selected from the group consisting of Ni, Cr, Ti, W, and Mo or an alloy containing at least one of them. Manufacturing method of light emitting element. 第2電極層が、Cu,Ni,Sn,Feの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなることを特徴とする請求項2〜4のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   5. The flip according to claim 2, wherein the second electrode layer is made of a metal selected from the group consisting of Cu, Ni, Sn, and Fe or an alloy containing at least one of them. A method for manufacturing a chip-type gallium nitride semiconductor light-emitting device. 窒化ガリウム系半導体発光素子の正電極が形成された側の表面の一部にn型半導体層を露出させ、該n型半導体層に金属からなる負電極を形成した後、該負電極の表面の所定の部分と粘着性付与化合物を含む組成物とを反応させることにより負電極の表面の所定の部分に粘着性を付与し、粘着性付与部分にのみ半田粉末を付着させた後、加熱して半田粉末を溶融させ、負電極の表面の所定の部分に半田層を形成することを特徴とする請求項1〜5のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   After exposing the n-type semiconductor layer to a part of the surface on the side where the positive electrode of the gallium nitride based semiconductor light-emitting element is formed, forming a negative electrode made of metal on the n-type semiconductor layer, A predetermined part and a composition containing a tackifier compound are reacted to impart adhesiveness to a predetermined part of the surface of the negative electrode, and after applying solder powder only to the tackified part, heat 6. The method of manufacturing a flip-chip gallium nitride semiconductor light emitting device according to claim 1, wherein the solder powder is melted to form a solder layer on a predetermined portion of the surface of the negative electrode. . 正電極と負電極に同時に半田層を形成することを特徴とする請求項6記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   7. The method of manufacturing a flip chip type gallium nitride based semiconductor light emitting device according to claim 6, wherein solder layers are simultaneously formed on the positive electrode and the negative electrode. 半田層の厚さが、5〜100μmであることを特徴とする請求項1〜7のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   The method for manufacturing a flip-chip gallium nitride semiconductor light-emitting element according to claim 1, wherein the solder layer has a thickness of 5 to 100 μm. 半田層の厚さが、5〜25μmであることを特徴とする請求項8記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   9. The method of manufacturing a flip chip type gallium nitride based semiconductor light emitting device according to claim 8, wherein the solder layer has a thickness of 5 to 25 [mu] m. 半導体発光素子の平面形状が、一辺200〜280μの正方形であることを特徴とする請求項1〜9のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   10. The method for manufacturing a flip-chip gallium nitride semiconductor light-emitting element according to claim 1, wherein the planar shape of the semiconductor light-emitting element is a square having a side of 200 to 280 μm. 正電極および負電極の半田層の間隔が、30μm〜150μmであることを特徴とする請求項1〜10のいずれか一項に記載のフリップチップ型窒化ガリウム系半導体発光素子の製造方法。   The method for manufacturing a flip-chip gallium nitride based semiconductor light-emitting device according to any one of claims 1 to 10, wherein the interval between the solder layers of the positive electrode and the negative electrode is 30 to 150 µm. 請求項1〜11のいずれか一項に記載の製造方法で製造されたフリップチップ型窒化ガリウム半導体発光素子。   A flip chip type gallium nitride semiconductor light emitting device manufactured by the manufacturing method according to claim 1. 正電極および負電極の表面に半田層を有するフリップチップ型窒化ガリウム系半導体発光素子において、該半田層の厚さが5〜100μmであり、正電極および負電極の半田層の間隔が30〜150μmであり、素子の平面形状が一辺200〜280μmであることを特徴とするフリップチップ型窒化ガリウム系半導体発光素子。   In a flip-chip gallium nitride semiconductor light emitting device having a solder layer on the surface of the positive electrode and the negative electrode, the thickness of the solder layer is 5 to 100 μm, and the distance between the positive and negative electrode solder layers is 30 to 150 μm. A flip chip type gallium nitride based semiconductor light emitting device, wherein the planar shape of the device is 200 to 280 μm per side. 正電極が、Au,Ag,Pt,Pd,Rh,Alの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなる第1電極層、Ni,Cr,Ti,W,Moの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなるバリア層およびCu,Ni,Sn,Feの群から選ばれた金属またはこれらの少なくとも1種類を含む合金からなる第2電極層からなることを特徴とする請求項13記載のフリップチップ型窒化ガリウム半導体発光素子。   The positive electrode is a first electrode layer made of a metal selected from the group of Au, Ag, Pt, Pd, Rh, and Al or an alloy containing at least one of these, and a group of Ni, Cr, Ti, W, and Mo A barrier layer made of a selected metal or an alloy containing at least one of them and a second electrode layer made of a metal selected from the group of Cu, Ni, Sn, Fe or an alloy containing at least one of these The flip-chip type gallium nitride semiconductor light-emitting device according to claim 13. 請求項13または14に記載のフリップチップ型窒化ガリウム系半導体発光素子を、回路基板の導電回路の電極と該発光素子の各半田層とが接触するようにダイボンドし、加熱して半田を溶融し、回路基板に接合することを特徴とするフリップチップ型窒化ガリウム系半導体発光素子の実装方法。   15. The flip chip type gallium nitride based semiconductor light emitting device according to claim 13 or 14 is die-bonded so that an electrode of a conductive circuit on a circuit board and each solder layer of the light emitting device are in contact with each other, and heated to melt the solder. A method of mounting a flip-chip gallium nitride based semiconductor light-emitting device, characterized by bonding to a circuit board.
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