JP2005115981A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a simple address conversion circuit capable of replacing a redundancy memory cell and a defective memory cell.
An address conversion circuit 12 includes a NAND circuit 12a, a plurality of EX-NOR circuits 12b, and a plurality of selection circuits 12c. The NAND circuit 12a and the plurality of EX-NOR circuits 12b receive the defect information from the outside. The NAND circuit 12a identifies the first or last column address or row address, and the plurality of EX-NOR circuits 12b identify the column address or row address including the address of the defective memory cell, The plurality of selection circuits 12c output address conversion information to the random access memory 11 based on the identified information.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device having means for relieving a defective memory cell.

  In a semiconductor memory, it is difficult to form all memory cells without defects. For this reason, a defective memory cell repair method called a redundancy method is used in which a defective memory cell is replaced with a separately prepared redundancy memory cell.

  As a typical conventional redundancy method, there is a fuse blow method. This cuts the fuses of some memory cells including defective memory cells, and further changes the circuit connection to the redundant memory cells prepared for the repair of defective memory cells. This is a method for replacing a cell and a redundancy memory cell. However, as a problem, the fuse cutting method has a high manufacturing cost due to an increase in the number of processes, and the yield may decrease due to the cutting and connecting processes.

  For this reason, as a method other than the fuse blow method, a method of physically converting the address arrangement between the redundancy memory cell and the defective memory cell is used. According to this method, a defective memory cell can be relieved without adding a process to a completed semiconductor device such as a fuse cut.

(For example, refer to Patent Document 1).
JP-A-8-273389 (page 7, FIG. 1)

  The method of physically converting the address arrangement described above can overcome the drawbacks of the fuse blow method. On the other hand, in order to physically convert the address arrangement, a programmable address conversion circuit is required as means for realizing it. However, the introduction of the address conversion circuit has problems such as a complicated circuit as a semiconductor device and an increase in the area of the entire device.

  SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor having an address conversion circuit with a small area and a simple configuration capable of converting between an address of a defective memory cell and an address of a redundancy memory cell. To provide an apparatus.

  In order to solve the above-described problem, a first aspect of the present invention includes a main memory cell group arranged in an array in the column direction and the row direction, and a redundancy memory cell group arranged in the column direction or the row direction. And a signal designating the first or last column address or row address of the main memory cell group to a signal designating the column address or row address of the redundancy memory cell group, and the first Alternatively, if the final column address or row address does not include the address of the defective memory cell, a signal specifying the column address or row address including the defective memory cell is used as the first or last address column or row address. Having an address conversion circuit for converting the signal into a designated signal And butterflies.

The second aspect of the present invention includes a memory having a main memory cell group arranged in an array in the column direction and the row direction, and a redundancy memory cell group arranged in the column direction or the row direction. The signal designating the first or last column address or row address of the main memory cell group is converted into the signal designating the column address or row address of the redundancy memory cell group, and the first or last column address or When the row address does not include the address of the defective memory cell, the signal specifying the column address or row address including the defective memory cell is converted into the signal specifying the first or last address column or row address. And an address conversion circuit.

  According to a third aspect of the present invention, there is provided a main memory cell group arranged in an array in the column direction and the row direction, and a redundancy memory arranged in parallel with the main memory cell in the column direction and the row direction. A signal for designating a memory having a cell group and a first or last column address of the main memory cell group arranged in the column direction of the main memory cell group, and a column address of the redundancy memory cell group are designated. When the first or final column address does not include the address of the defective memory cell, the signal specifying the defective column address is converted into the signal specifying the first or final column address. A first address conversion circuit that performs a first address conversion of the main memory cell group arranged in a row direction of the main memory cell group. Or a signal designating the last row address is converted into a signal designating the row address of the redundancy memory cell group, and if the first or last row address does not include the address of the defective memory cell, And a second address conversion circuit for converting a signal designating a row address having a first address into a signal designating the last or last row address.

  According to a fourth aspect of the present invention, the main memory includes a memory including a main memory cell group arranged in an array in the column direction and the row direction, and a redundancy memory cell group arranged in the column direction. A signal designating the first or last column address of the main memory cell group arranged in the column direction of the cell group is converted into a signal designating the column address of the redundancy memory cell group, and the first or last column address is converted. A first address conversion circuit for converting a signal designating a defective column address into a signal designating the first or last column address when the address does not include an address of a defective memory cell; and the row direction Including the redundancy memory cell group arranged in the row direction of the main memory cell group. When a signal designating the first or last row address of the group is converted into a signal designating the row address of the redundancy memory cell group, and the first or last row address does not include the address of the defective memory cell And a second address conversion circuit for converting a signal designating a defective row address into a signal designating the first or last row address.

  According to the present invention, it is possible to provide a semiconductor device having an address conversion circuit capable of a small area with a simple configuration capable of converting an address of a defective memory cell and an address of a redundancy memory cell.

  Embodiments of the present invention will be described below with reference to the drawings.

  In the first embodiment of the present invention, a random access memory built-in self test circuit (RAMBIST) is added to the address conversion circuit and the random access memory as a BIST circuit for detecting a defective memory cell, and the memory test has a defect. This is a semiconductor device that consistently repairs memory cells.

  FIG. 1 is a circuit block diagram of a semiconductor device according to the first embodiment. The semiconductor device 10 starts operating by turning on the power-on reset circuit 14.

  The RAMBIST 15 includes a control circuit 15a, a test circuit 15b, a comparison circuit 15c, and a storage circuit 15d. The control circuit 15a controls the random access memory 11 test by the RAMBIST 15 and the address conversion of the random access memory 11 by the address conversion circuit 12 based on the internal program register.

  The test circuit 15b executes a test of the random access memory 11 according to an instruction from the control circuit 15a. The comparison circuit 15c compares the test data obtained from the random access memory 11 with the expected value data sent from the test circuit 15b, and writes the result as fail path data to the storage circuit 15d.

  Next, an operation procedure of the semiconductor device 10 is shown in FIG. First, when the semiconductor device 10 is powered on (step S1), the RAMBIST 15 is automatically initialized by the power-on reset circuit 14 (step S2). Alternatively, initialization may be performed by an external switch after power is turned on. Subsequently, the control circuit 15a in the RAMBIST 15 generates a sequence for instructing a series of operation procedures based on the internal program register (step S3).

  In response to a sequence instruction from the control circuit 15a, the test circuit 15b in the RAMBIST 15 executes a test of the random access memory 11 (step S4). The test data and expected value data from the test circuit 15b are sent to the comparison circuit 15c. The comparison circuit 15c compares the test data with the expected value data, and if the two data match, it passes, and if they do not match, it fails (step S5). The pass / fail data is sent to the storage circuit 15d and stored (step S6).

  The control circuit 15a reads the address where the failure is found from the pass / fail data stored in the storage circuit 15d. Next, the result is sent to the address conversion circuit 12 as fail address information (step S7). The address conversion circuit 12 receives the information and performs an address conversion operation (step S8). Based on the calculation of the address conversion, in the random access memory 11, for example, the address replacement between the column including the defective bit and the column of the spare memory cell is performed (step S9). As described above, from test to address conversion is automatically performed, and the address having the fail bit can be used as a random access memory in a state where the address is relieved (step S10).

  In addition, the above-described steps can be automatically performed to the end by turning on the power-on reset circuit 14.

  Next, address conversion between the failed memory cell and the redundancy cell by the address conversion circuit 12 will be described. FIG. 3 shows a circuit block diagram of the random access memory 11 and the address conversion circuit 12 in the semiconductor device 10 shown in FIG.

  In this embodiment, the random access memory 11 includes a main memory cell group 11a composed of 8 columns (numbers 0 to 7) and a redundancy memory cell group 11b composed of 1 column (number 8) as memory cells, and the accessed address. A column decoder 11c and a row decoder 11d are included. Hereinafter, address conversion in the column direction will be described as an example.

  The address conversion circuit 12 that controls address conversion between the main memory cell group 11a and the redundancy memory cell group 11b of the random access memory 11 receives input signals from the storage circuit 15d and the control circuit 15a of the RAMBIST described in FIG. That is, a flag signal indicating the presence or absence of a fail bit in the main memory cell group 11a (for example, “1” when there is a fail bit, “0” when there is no fail bit) is input from the control circuit 15a to the flag terminal 13b. The The column address signal to be selected is input from the control circuit 15a to the three address input terminals 13a (C0, C1, C2). A signal indicating a defective column address including a fail bit is input to the three fail input terminals 13c (F0, F1, F2).

  Further, in order to designate addresses in the column direction in the random access memory 11, four address output terminals 13d (C0 ′, C1 ′, C2 ′), three for eight columns and one for the columns of the redundancy memory cell group 11b. , C3 ′).

  In addition, when there is a fail bit, the address conversion circuit 12 inputs a flag signal and an address signal so that a specific address can be specified, and the accessed column address is compared with a defective column address. EX-NOR circuit 12b (E1, E2, E3) and a selection circuit that selects a signal from the EX-NOR circuit 12b and a fixed signal (“1” or “0”) by a signal from the NAND circuit 12a 12c (S1, S2, S3, S4).

  As described above, in the 8-column random access memory 11 of this embodiment, as the address conversion circuit 12, four selection circuits 12c, three EX-NOR circuits 12b, one NAND circuit 12a, As terminals, an input 7 terminal and an output 4 terminal are combined, and a simple circuit configuration is obtained.

  FIG. 4 shows the input / output levels of the NAND circuit 12a, EX-NOR circuit 12b, and selection circuit 12c constituting the address conversion circuit in this embodiment. Address conversion is performed according to this table. The NAND circuit 12a has four inputs, and the input terminals A to D are all “1”, that is, there is a defect, “1” is input to the flag terminal, and all three address inputs are “1”. In this case, the output is “0”. All other cases are "1".

  The EX-NOR circuit 13b is not particularly described and will be omitted.

  The selection circuit 13c outputs according to the level of the input B when “0” is input to the selection terminal SEL, and outputs according to the level of the input A when “1” is input to the SEL. The input B of the selection circuit 13c connected to C0 ', C1', and C2 'is fixed to "0", the input A of the selection circuit connected to C3' is fixed to "0", and the input B is fixed to "1".

  Next, an example of address conversion in this embodiment is shown in FIG.

  FIG. 5A shows a table when there is no column defect (no fail bit), that is, when address translation is not actually performed. In the three address input terminals 13a before the address conversion, upper address pins are determined in the order of C0 ', C1', and C2 '. In the four output terminals 13d of the address conversion circuit, the output terminal C3 'becomes the most significant address pin and continues in the order of C0', C1 ', and C2'. Therefore, the address input terminals C0, C1, and C2 are associated with the column numbers 0 to 8 shown in FIG. 3 as shown in FIG.

  Since there is no column defect, the output X of the NAND circuit 12a is “1” regardless of the input levels of A to D. Therefore, the selection circuit 12c selects and outputs the input A. On the other hand, the input levels to the fail input terminals F0, F1, and F2 are set to be the same as the corresponding address inputs so that the levels of the address input terminals C0, C1, and C2 are output as they are from the EX-NOR circuit 12b. As a result, the address output terminals C0 ', C1', C2 'and the column numbers 0 to 7 can maintain correspondence at the time of address input as shown in FIG.

  Subsequently, as an example in the case where a fail bit exists, for example, a case where the second column is a defective column is shown in FIG. In this case, “0” is input to F0, “1” is input to F1, and “0” is input to F2, respectively, to the fail input terminal 13c.

  Normally, when an address for accessing the second column is input (“0” to C0, “1” to C1, and “0” to C2), the result is as follows. Through the output of the EX-NOR circuit 12b, “1” is input to all the input terminals A of the selection circuit 12c. Since the NAND circuit 12a outputs “1”, C0 ′, C1 ′, and C2 ′ all output “1” at the address output terminals. Since such address conversion occurs, the second column which is a defective column is not accessed, and the seventh column which is the highest column address of the main memory cell group 11a is selected.

  Next, when an address for accessing the seventh column is input (“1” to C0, “1” to C1, and “1” to C2), the result is as follows. In this case, “1” is input to all the input terminals (A to D) of the NAND circuit 12a. Therefore, “0” is output from the output terminal of each EX-NOR circuit 12b, and the selection circuit 12c outputs the level of the input terminal B. As shown in FIG. 3, since a fixed signal is input to the input terminal B of the selection circuit 12c, the fixed signal (“1” to C3 ′, “0” to C0 ′, C1 from the address output terminal) "0" and C2 "0") are output. Further, this address accesses the eighth column, that is, the redundancy cell 11b.

  Thus, by the address conversion in which the defective column, the last column, and the redundancy column are interchanged, conversion of the defective column and the redundancy column is performed as the entire random access memory, and normal operation is possible. Note that address conversion is performed for other columns as shown in FIG.

  As described above, according to the present embodiment, address conversion between a redundancy cell and a defective memory cell in a random access memory can be performed by using an address conversion circuit having a simple configuration.

  Also, according to the present embodiment, by including RAMBIST in the semiconductor device, it is possible to perform consistently and automatically from random access memory to address conversion, and the number of processes related to testing can be greatly reduced.

(Modification)
FIG. 6 shows a circuit block diagram of an address conversion circuit corresponding to a 32-column random access memory, which constitutes a modification of the first embodiment of the present invention. Since this modification has the same basic contents as the circuit block of the first embodiment shown in FIG. 3, the random access memory is not shown.

  The address conversion circuit 12 has terminals having the following functions. A flag signal indicating the presence or absence of a fail bit in the memory cell is input to the flag terminal 13b. The column address signal to be selected is input to the five address input terminals 13a (C0, C1, C2, C3, C4). A signal indicating a defective column address including a fail bit is input to the five fail input terminals 13c (F0, F1, F, F3, and F4).

  In addition, in order to designate addresses in the column direction in a random access memory (not shown), a total of six address output terminals 13d (C0 ′, C1 ′, C2 ′), five for 32 columns and one for the column of the redundancy memory cell 11b. , C3 ′, C4 ′, C5 ′).

  In addition, when there is a fail bit, the address conversion circuit 12 inputs a flag signal and an address signal so that a specific address can be specified, and the accessed column address is compared with a defective column address. The EX-NOR circuit 12b and the selection circuit 12a that selects a signal from the EX-NOR circuit 12b and a fixed signal ("0" or "1") by a signal from the NAND circuit 12a.

  As described above, in the 32-column random access memory according to the present embodiment, as the address conversion circuit, there are six selection circuits, five EX-NOR circuits, one NAND circuit, and a terminal as an input 11. The terminal and the output 6 terminal are combined, and the circuit configuration is simple.

  Further, when the number of columns is increased, it is a matter of course that the same circuits and terminals should be increased correspondingly, and the configuration can easily cope with an increase in memory capacity.

  FIG. 7 shows a circuit block diagram of a random access memory and an address conversion circuit in Embodiment 2 of the present invention. The present embodiment is characterized in that a redundancy cell group 22 b consisting of one column is arranged in the address conversion circuit 22. That is, as the memory cell group of the random access memory 21, only the main memory cell group 11a having 8 columns is mounted.

  Since other configurations are the same as those of the random access memory and the address conversion circuit of FIG. 3 shown in the first embodiment, detailed description thereof is omitted.

  According to the present embodiment, since the redundancy cell is included in the address conversion circuit, it is easy to add the address conversion circuit to the memory cell design of the random access memory including only the main memory cell. This makes it possible to design a semiconductor device with high flexibility.

  In the embodiments so far, the address conversion of the memory cells in the column direction by the column decoder has been shown. Furthermore, the same address conversion is possible in the row decoder, and an example thereof will be shown.

  Since the entire configuration of the semiconductor device is basically the same as that shown in FIGS. A circuit similar to the address conversion circuit connected to the column decoder in FIG. 3 is further connected to the row decoder.

  FIG. 8 is an address map of main memory cells and redundancy cells in a random access memory.

  In FIG. 8A, a main memory cell 11a is constituted by 8 columns and 8 rows, and each is given an address number. Further, there is one redundancy cell 11c in the column direction and one redundancy cell 11d in the row direction. In addition, there are two defective bits (NG) in the main memory cell 11a.

  With respect to the defective bit (NG), the address conversion is performed by the address conversion method described in detail with reference to FIG. Similar to the address conversion example shown in FIG. 5, the address is converted, the column address number 2 is not accessed, and the column-direction redundancy cell 11c, which is the column address number 8, is accessed. FIG. 8B shows an address map after column address conversion. All the columns are address-converted, and the second column address including the defective bit (NG) remains without being accessed.

  Next, the same processing is performed for the second row address including the defective bit (NG). FIG. 8C shows an address map after row address conversion. All the rows are address-converted, and the second row address including the defective bit (NG) remains without being accessed.

  As described above, according to this embodiment, by providing a redundancy cell group in both the column and row directions, it is possible to convert the addresses of a plurality of memory cells including defective bits into the addresses of the redundancy cell group. Become.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

  For example, when the address of the defective column is designated, the first address may be selected in addition to the case where the uppermost column address of the selected main memory cell group 11a, that is, the final address is selected.

  Further, when the column address or row address of the defective memory cell is the last or first address, the address of the redundancy cell group is the conversion target.

  For example, a plurality of address conversion circuits or a plurality of first address conversion circuits and second address conversion circuits may be provided. At this time, if the redundancy memory cell group is arranged in the memory, the number of the corresponding memory cell groups is prepared in correspondence with it. Further, the redundancy memory cell group can be arranged in the memory and given an address. The fixed signal in the selection circuit may be changed according to the address.

  The size of the main memory cell group corresponding to one redundancy cell group is not particularly limited, and can be used for a large-scale memory.

  It is also possible to use an external test device without incorporating the BIST circuit for testing the memory in the semiconductor device. In this case, a memory circuit for storing test data may be incorporated in the semiconductor device.

  In addition, the semiconductor device can be applied not only to the random access memory but also to other memories, and of course, can be applied to a system LSI including a memory in which a logic circuit is embedded.

1 is a circuit block diagram showing a first embodiment of a semiconductor device according to the present invention. The flowchart which shows the operation | movement sequence in Example 1 of the semiconductor device by this invention. 1 is a circuit block diagram of a random access memory and an address conversion circuit in Embodiment 1 of a semiconductor device according to the present invention. The figure which shows the input / output level of each circuit which comprises the address conversion circuit in Example 1 of the semiconductor device by this invention. The figure which shows the address translation by the address translation circuit in Example 1 of the semiconductor device by this invention. The circuit block diagram of the address conversion circuit which shows the modification in Example 1 of the semiconductor device by this invention. FIG. 6 is a circuit block diagram of a random access memory and an address conversion circuit in a second embodiment of the semiconductor device according to the present invention. 10 is an address map showing address conversion in the third embodiment of the semiconductor device according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11, 21 Random access memory 12, 22 Address conversion circuit 14 Power-on reset circuit 15 RAMBIST
15a control circuit 15b test circuit 15c comparison circuit 15d storage circuit 11a main memory cell group 11b, 22b redundancy cell group 11c column decoder 11d row decoder 12a NAND circuit 12b EX-NOR circuit 12c selection circuit 13a address input terminal 13b flag terminal 13c fail input Terminal 13d Address output terminal 11c Redundancy cell in column direction 11d Redundancy cell in row direction

Claims (14)

A memory including a main memory cell group arranged in an array in the column direction and the row direction, and a redundancy memory cell group arranged in the column direction or the row direction;
A signal designating the first or last column address or row address of the main memory cell group is converted into a signal designating the column address or row address of the redundancy memory cell group, and the first or last column address or row address is converted. If the address does not include the address of a defective memory cell, an address that converts a signal specifying a column address or row address including the defective memory cell into a signal specifying the first or last address column or row address A semiconductor device comprising: a conversion circuit.   The main memory cell group is divided into a plurality of memory cell groups, and each of the memory cell groups is arranged so that one redundancy memory cell group and one address conversion circuit correspond to each other in the column direction or the row direction. The semiconductor device according to claim 1, wherein: A memory having a group of main memory cells arranged in an array in the column direction and the row direction;
A redundancy memory cell group arranged in the column direction or the row direction, and a signal designating a first or last column address or row address of the main memory cell group is sent as a column address or row address of the redundancy memory cell group And when the first or last column address or row address does not include the address of the defective memory cell, the signal specifying the column address or row address including the defective memory cell is A semiconductor device comprising: an address conversion circuit for converting the first or last address column or signal into a signal designating a row address.   4. The semiconductor device according to claim 3, wherein the main memory cell group is divided into a plurality of memory cell groups, and each of the memory cell groups is arranged so that one address conversion circuit corresponds to the memory cell group. . The address conversion circuit includes:
A NAND circuit to which a detection flag signal based on detection of the memory cell having the defect and a plurality of external address signals for designating the address of the main memory cell are input;
A plurality of exclusive NOR circuits to which each of the plurality of address signals and each of address signals of column addresses or row addresses including the defective memory cells are input;
Each output signal of the plurality of exclusive NOR circuits is input, and the output signal of the NAND circuit selectively selects one of the output signal of the exclusive NOR circuit and a different first fixed signal from the exclusive NOR circuit. A plurality of first selection circuits for outputting to the main memory cell group;
The first fixed signal and a second fixed signal corresponding to the output signal of the exclusive NOR circuit are input, and one of the first and second fixed signals is selected by the output signal of the NAND circuit, 5. The semiconductor device according to claim 1, further comprising: a second selection circuit that outputs to the first redundancy memory cell group.   A BIST circuit for testing the memory, storing test data based on the test, and inputting information on a column address or a row address including the defective memory cell to the address conversion circuit based on the test data; The semiconductor device according to any one of claims 1 to 5, wherein:   And a means for automatically testing the memory by the BIST circuit, storing the test data, inputting the information on the defect to the address translation circuit, and address translation by the address translation circuit. The semiconductor device according to claim 6. A memory comprising: a main memory cell group arranged in an array in the column direction and the row direction; and a redundancy memory cell group arranged in parallel with the main memory cell in the column direction and the row direction;
A signal designating the first or last column address of the main memory cell group arranged in the column direction of the main memory cell group is converted into a signal designating the column address of the redundancy memory cell group, and the first or A first address conversion circuit for converting a signal designating a defective column address into a signal designating the first or last column address when a final column address does not include an address of a defective memory cell;
A signal designating the first or last row address of the main memory cell group arranged in the row direction of the main memory cell group is converted into a signal designating the row address of the redundancy memory cell group, and the first or A second address conversion circuit for converting a signal designating a defective row address into a signal designating the first or last row address when the final row address does not include an address of a defective memory cell; A semiconductor device comprising:   The main memory cell group is divided into a plurality of memory cell groups, one redundancy memory cell group is arranged in the column direction and the row direction of each memory cell group, and each memory cell 9. The semiconductor device according to claim 8, wherein one of the first address conversion circuits and one of the second address conversion circuits are arranged so as to correspond to a group. A memory having a group of main memory cells arranged in an array in the column direction and the row direction;
A redundancy memory cell group arranged in the column direction, and a signal designating a first or last column address of the main memory cell group arranged in the column direction of the main memory cell group. When the first or last column address does not include the address of the defective memory cell, the signal specifying the defective column address is changed to the first or last column address. A first address conversion circuit for converting to a designated signal;
The redundancy memory cell group includes a redundancy memory cell group arranged in the row direction, and a signal designating a first or last row address of the main memory cell group arranged in the row direction of the main memory cell group is transmitted to the redundancy memory cell group. When the first or final row address does not include the address of a defective memory cell, the signal specifying the defective row address is converted to the first or final row address. And a second address conversion circuit for converting the signal into a designated signal.   The main memory cell group is divided into a plurality of memory cell groups, and each of the memory cell groups is arranged so that one of the first address conversion circuits and one of the second address conversion circuits correspond to each other. The semiconductor device according to claim 10. The first address conversion circuit and the second address conversion circuit are respectively
A NAND circuit to which a detection flag signal based on detection of the memory cell having the defect and a plurality of external address signals for designating the address of the main memory cell are input;
A plurality of exclusive NOR circuits to which each of the plurality of address signals and each of address signals of column addresses or row addresses including the defective memory cells are input;
Each output signal of the plurality of exclusive NOR circuits is input, and the output signal of the NAND circuit selectively selects one of the output signal of the exclusive NOR circuit and a different first fixed signal from the exclusive NOR circuit. A plurality of first selection circuits for outputting to the main memory cell group;
The first fixed signal and a second fixed signal corresponding to the output signal of the exclusive NOR circuit are input, and one of the first and second fixed signals is selected by the output signal of the NAND circuit, 12. The semiconductor device according to claim 8, further comprising: a second selection circuit that outputs to the first redundancy memory cell group.   Test the memory, store test data from the test, and based on the test data, the first address conversion circuit and the second address conversion circuit include a column address or a row address including the memory having the defect. The semiconductor device according to claim 8, further comprising a BIST circuit for inputting information.   From the test of the memory by the BIST circuit, the storage of the test data, the input of the information regarding the defect to the address conversion circuit, and the address conversion by the first address conversion circuit and the second address conversion circuit are all performed. 14. The semiconductor device according to claim 13, further comprising means for automatically performing the processing.

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