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JP2005115171A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2005115171A
JP2005115171A JP2003351229A JP2003351229A JP2005115171A JP 2005115171 A JP2005115171 A JP 2005115171A JP 2003351229 A JP2003351229 A JP 2003351229A JP 2003351229 A JP2003351229 A JP 2003351229A JP 2005115171 A JP2005115171 A JP 2005115171A
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resist
surfactant
polymer
pattern
semiconductor device
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Manabu Watanabe
孊 枡蟺
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Semiconductor Leading Edge Technologies Inc
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Semiconductor Leading Edge Technologies Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To uniformly align a polymer by using interfacial alignment of a surfactant by incorporating a surfactant into a resist and to reduce line edge roughness of a pattern obtained after development in a single layer resist process for forming lines by exposure to electron beams or light. <P>SOLUTION: A resist 11 is applied on an undercoat layer 10 and patterned by a conventional exposure method 16 (with electron beams or light). The resist 11 used is prepared by adding a surfactant 13 to a polymer. The surfactant 13 comprises a hydrophobic group 15 and a hydrophilic group 14. By applying the resist containing the surfactant on the undercoat layer 10, the hydrophilic group 14 is aligned inward the resist on the interface of the resist 11 and air. As the pattern 11a obtained by exposure and development has a uniform microscopic structure of the polymer depending on the alignment of the surfactant, the line edge roughness can be reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、改善したレゞスト材料を甚いた半導䜓装眮の補造方法に関し、特に化孊増幅型レゞストを甚いた半導䜓装眮の補造方法である。   The present invention relates to a method for manufacturing a semiconductor device using an improved resist material, and more particularly to a method for manufacturing a semiconductor device using a chemically amplified resist.

近幎半導䜓デバむスは益々高集積化し、それに぀れパタヌンの埮现化が急速に進行しおいる。それに䌎い芁求される制埡範囲も、狭くなる傟向にあり、制埡の぀ずしお、レゞストパタヌン端郚の乱れ、いわゆるラむン゚ッゞラフネスも埮现化を芁求されるようになり、制埡が困難を極める状況になっおいる。このはレゞストパタヌニング埌の゚ッチング工皋での線幅ばら぀きに圱響を䞎えるため、補造管理の手法であるσにお数レベルの倀を芁求されるようになっおきおいる。   In recent years, semiconductor devices have been increasingly integrated, and the pattern miniaturization has been rapidly progressing. Along with this, the required CD control range tends to become narrower, and as one of the CD controls, disturbance of the resist pattern end, so-called line edge roughness (LER), is required to be miniaturized, and the control is performed. The situation is extremely difficult. Since this LER affects the line width variation in the etching process after resist patterning, a value of several nm level is required for 3σ which is a manufacturing management method.

珟圚レゞストに䜿甚されおいるポリマヌは、分子量が皋床のポリマヌであり、そのポリマヌ぀の倧きさは数に盞圓する。曎にこのポリマヌは、数個のポリマヌ分子が凝集しお、クラスタヌ化するため、このレゞストを甚いおパタヌニングしたパタヌンにおいおは、が倧きくなる芁因を持っおいる。このように、珟状のレゞストでは、はポリマヌ皮に䟝存しおしたうため、ポリマヌを最適化しおも、必ずしもを改善するこずができなかった。   The polymer currently used for the resist is a polymer having a molecular weight of about 100, and the size of one polymer corresponds to several nm. Furthermore, since this polymer is agglomerated and clustered by several polymer molecules, the pattern patterned using this resist has a factor of increasing LER. Thus, in the current resist, since LER depends on the polymer type, LER cannot always be improved even if the polymer is optimized.

埓来のレゞストを甚いたパタヌン圢成方法を、プロセスを瀺す抂略断面図である図を甚いお説明する。たず。図に瀺すように、䞋地にレゞストを塗垃する。次いで、図に瀺すように、このレゞストに察しお、図瀺しないマスクを甚いお露光する。この露光によっお非感光領域ず、感光領域が圢成される。次いで、図に瀺すように、これを珟像するず、パタヌンが圢成される。埗られるパタヌンは、図に瀺すように、パタヌン偎壁及び䞊面に凹凞が生じおしたう。図は図のパタヌン郚分を拡倧した暡匏図である。   A pattern forming method using a conventional resist will be described with reference to FIG. 3 which is a schematic sectional view showing the process. First. As shown in FIG. 3A, a resist 31 is applied to the base 30. Next, as shown in FIG. 3B, the resist 31 is exposed using a mask (not shown). By this exposure, a non-photosensitive area 31a and a photosensitive area 31b are formed. Next, as shown in FIG. 3C, when this is developed, a pattern 31a is formed. As shown in FIG. 4, the obtained pattern 31a has irregularities on the pattern side wall and the upper surface. FIG. 4 is an enlarged schematic view of the pattern portion 38 of FIG.

パタヌンを構成するレゞストは、レゞストポリマヌのミクロ結晶ないしはポリマヌの分子が集合したクラスタヌ以䞋「ポリマヌミクロ構造䜓」ずいうが集合しお圢成されおおり、このポリマヌミクロ構造䜓は、レゞスト䞭においおランダムに䜍眮しおいる。
図においお、これはレゞスト内を倧きく占めおいるレゞストを構成する材料であるポリマヌのポリマヌミクロ構造䜓が、レゞストの䞭でランダムに離散的に分散しおおり、このようにポリマヌミクロ構造䜓がレゞストパタヌン䞭で分散しおいるず、パタヌニングされたレゞスト界面郚は、ポリマヌミクロ構造䜓に察応しお凹凞が圢成されおしたう。
The resist constituting the pattern is formed by agglomerating clusters of resist polymer microcrystals or polymer molecules (hereinafter referred to as “polymer microstructures”). The polymer microstructures are randomly formed in the resist. Is located.
In FIG. 4, the polymer microstructure 32 of the polymer, which is a material constituting the resist that occupies a large part of the resist, is randomly and discretely dispersed in the resist 4, and thus the polymer microstructure When the body is dispersed in the resist pattern, the patterned resist interface portion is uneven, corresponding to the polymer microstructure.

このラむン゚ッゞラフネスを防止するために、最初に高枩でを斜すこずが知られおいる特蚱文献参照。しかしながら、この方法によれば、耐熱性に劣るレゞストを甚いた堎合、レゞストに熱履歎が残留し、その特性に悪圱響を及がすおそれがあった。

特開−号公報
In order to prevent this line edge roughness, it is known that PEB is first performed at a high temperature (see Patent Document 1). However, according to this method, when a resist having poor heat resistance is used, a thermal history remains in the resist, which may adversely affect its characteristics.

JP 2003-68602 A

本発明は、埓来のレゞストを甚いたリ゜グラフィにおいお、レゞストパタヌンの端郚に凹凞が発生するのを改善するものであり、レゞストのミクロ構造を改善するこずにより、パタヌニング埌のレゞスト界面の凹凞ラむン゚ッゞラフネスを枛少させるこずを目的ずするものである。
The present invention improves the occurrence of unevenness at the edge of a resist pattern in lithography using a conventional resist. By improving the resist microstructure, the unevenness (line) of the resist interface after patterning is improved. The object is to reduce edge roughness (LER).

本発明はレゞストに界面掻性剀を配合するこずにより、レゞスト䞭のポリマヌミクロ構造䜓を配向させるこずができるこずに着目しおなされたものである。   The present invention has been made paying attention to the fact that a polymer microstructure in a resist can be oriented by adding a surfactant to the resist.

本発明は、界面掻性剀を含有するレゞスト材料を、䞋地局衚面に塗垃・也燥しおレゞスト局を圢成する工皋ず、
前蚘レゞスト局に、光、線、もしくは電子線を照射しお前蚘レゞスト局を露光する工皋ず、
前蚘露光したレゞスト局を熱凊理する工皋ず、
前蚘熱凊理したレゞスト局をアルカリ珟像しお、端郚に凹凞のないパタヌンを圢成する工皋を少なくずも備えたこずを特城ずする半導䜓装眮の補造方法である。
The present invention comprises a step of applying a resist material containing a surfactant to the surface of the underlayer and drying to form a resist layer;
Irradiating the resist layer with light, X-rays or electron beam to expose the resist layer;
Heat treating the exposed resist layer;
A method of manufacturing a semiconductor device, comprising: at least a step of alkali-developing the heat-treated resist layer to form a pattern without unevenness at an end portion.

前蚘本発明においお、前蚘レゞスト材料が、化孊増幅型レゞスト材料であるこずが奜たしい。たた、前蚘界面掻性剀ずしおは、前蚘露光光によっお分解するこずのない界面掻性剀であり、たた、前蚘熱凊理によっお揮発するものでないこずが奜たしい。
In the present invention, the resist material is preferably a chemically amplified resist material. The surfactant is preferably a surfactant that is not decomposed by the exposure light and does not volatilize by the heat treatment.

以䞊のように埓来のレゞストに、界面掻性剀を加える事により、レゞストパタヌンのラむン゚ッゞラフネスを効果的に䜎枛できる。たた本発明は特に特別なプロセスを経由しないため、スルヌプットを萜ずすこずなく良奜なパタヌンを埗る事を可胜ずする。
As described above, the line edge roughness of the resist pattern can be effectively reduced by adding a surfactant to the conventional resist. In addition, since the present invention does not go through a special process, it is possible to obtain a good pattern without reducing the throughput.

本発明で甚いられるレゞスト材料は、酞によっお可溶化たたは架橋化するポリマヌず、光酞発生剀ず、界面掻性剀ず、有機溶剀を少なくずも含むものである。   The resist material used in the present invention contains at least a polymer that is solubilized or cross-linked by an acid, a photoacid generator, a surfactant, and an organic solvent.

本実斜の圢態においおは、レゞストずしおは、埮现パタヌンのリ゜グラフを高解像床で可胜にする化孊増幅型レゞストが奜たしい。   In the present embodiment, the resist is preferably a chemically amplified resist that enables lithographic fine patterns with high resolution.

本実斜の圢態の化孊増幅型レゞストは、レゞストの本䜓ずなるポリマヌ、光酞発生剀、界面掻性剀及びそれらを溶解させる有機溶媒からなっおいる。   The chemically amplified resist according to the present embodiment is composed of a polymer as a resist body, a photoacid generator (PAG), a surfactant, and an organic solvent for dissolving them.

このレゞストを構成するポリマヌずしおは、酞の䜜甚によっお可溶化たたは架橋化するポリマヌが甚いられ、具䜓的には、ポリヒドロキシスチレン、たたはずメタクリレヌト共重合ポリマヌずの混合材料、アクリル系ポリマヌ、およびフッ玠含有ポリマヌなど、公知のポリマヌ材料を甚いるこずができる。
これらのポリマヌは偎鎖に、ハむドロオキシ基−、カルボキシル基−−などの極性基芪氎性基を有しおおり、たた、䞻鎖は炭玠ず氎玠で構成されおいる非極性基疎氎性基のアルキル鎖からなっおいる。
As the polymer constituting the resist, a polymer that is solubilized or cross-linked by the action of an acid is used. Specifically, polyhydroxystyrene (PHS), or a mixed material of PHS and a methacrylate copolymer (ESCAP). Known polymer materials such as acrylic polymers and fluorine-containing polymers can be used.
These polymers have polar groups (hydrophilic groups) such as hydroxy groups (—OH) and carboxyl groups (—COO − ) in the side chains, and the main chain is composed of carbon and hydrogen. It consists of a non-polar group (hydrophobic group) alkyl chain.

たた、光酞発生剀ずしおは、ビススルホニりゞアゟメタン類、ニトロベンゞル誘導䜓、ポリヒドロキシ化合物ず脂肪族たたは芳銙族スルホン酞゚ステル類、オニりム塩、スルホニルカルボニルアルカン類、スルホニルカルボニルゞアゟメタン類、ハロゲン含有トリアゞン化合物類、オキシムスルホネヌト系化合物類、フェニルスルホニルオキシフタルむミド類など公知の化合物を甚いるこずができる。   Photoacid generators include bissulfoniudiazomethanes, nitrobenzyl derivatives, polyhydroxy compounds and aliphatic or aromatic sulfonic acid esters, onium salts, sulfonylcarbonylalkanes, sulfonylcarbonyldiazomethanes, halogen-containing triazine compounds. , Oxime sulfonate compounds, and phenylsulfonyloxyphthalimides can be used.

本実斜の圢態で甚いる界面掻性剀は、その分子䞭に極性の高い基芪氎性基ず極性の䜎い基疎氎性基を有するものである。   The surfactant used in the present embodiment has a highly polar group (hydrophilic group) and a less polar group (hydrophobic group) in the molecule.

この界面掻性剀ずしおは、陰むオン界面掻性剀、陜むオン界面掻性剀、非むオン界面掻性剀、および䞡性むオン界面掻性剀のいずれも甚いるこずができる。
陰むオン界面掻性剀ずしおは、脂肪酞ナトリりム塩、アルファスルホ脂肪酞゚ステル、アルキルベンれンスルホン酞塩、アルキル硫酞塩、アルキル゚ヌテル硫酞゚ステル塩、アルキル硫酞トリ゚タノヌルアミンなどが挙げられる。陜むオン界面掻性剀ずしおは、アルキルトリメチルアンモニりム塩、ゞアルキルゞメチルアンモニりムクロリド、アルキルピリゞニりムクロリドなどが挙げられる。非むオン界面掻性剀ずしおは、脂肪酞ゞ゚タノヌルアミン、ポリオキシ゚チレンアルキル゚ヌテル、ポリオキシ゚チレンアルキルフェニル゚ヌテルなどが挙げられる。たた、䞡性むオン界面掻性剀ずしおは、アルキルカルボキシベタむンなどが挙げられる。
As the surfactant, any of an anionic surfactant, a cationic surfactant, a nonionic surfactant, and a zwitterionic surfactant can be used.
Examples of the anionic surfactant include fatty acid sodium salts, alpha sulfo fatty acid esters, alkyl benzene sulfonates, alkyl sulfates, alkyl ether sulfate esters, and alkyl sulfate triethanolamine. Examples of the cationic surfactant include alkyltrimethylammonium salt, dialkyldimethylammonium chloride, alkylpyridinium chloride and the like. Nonionic surfactants include fatty acid diethanolamine, polyoxyethylene alkyl ether, polyoxyethylene alkylphenyl ether, and the like. Examples of the zwitterionic surfactant include alkyl carboxybetaines.

本実斜の圢態においお甚いられる界面掻性剀ずしおは、レゞストの露光工皋においお、露光光によっお分解されるものでないこずが必芁であり、たた、熱凊理工皋で、揮散するこずのないものであるこずが必芁である。このような芁件を備えた界面掻性剀ずしおは、分子量が、以䞊の界面掻性剀を挙げるこずができる。
たた、これらの界面掻性剀ずしおは、半導䜓装眮を汚染するこずの無いよう、金属䞍玔物元玠を含たない材料が奜たしい。
The surfactant used in the present embodiment must not be decomposed by exposure light in the resist exposure process, and must not be volatilized in the heat treatment process. It is. Examples of the surfactant having such requirements include surfactants having a molecular weight of 230 or more.
These surfactants are preferably materials that do not contain a metal impurity element so as not to contaminate the semiconductor device.

レゞストに配合する界面掻性剀の量ずしおは、〜重量皋床添加するこずが奜たしい。この配合量が、䞊蚘範囲を䞋回った堎合には、界面掻性剀添加の効果を発揮せず、䞀方、䞊蚘範囲を䞊回った堎合には、パタヌンの機械的匷床が䜎䞋しお奜たしくない。   The amount of the surfactant to be blended in the resist is preferably about 1 to 10% by weight. When the amount is less than the above range, the effect of adding the surfactant is not exhibited. On the other hand, when the amount exceeds the above range, the mechanical strength of the pattern is lowered, which is not preferable.

以䞋、䞊蚘レゞスト材料を甚いた堎合のパタヌン圢成の原理に぀いお説明する。混合材料である化孊増幅型レゞストには、䞀般にポリマヌ、酞発生剀、及びそれらを溶解させる有機溶媒から圢成され、さらにク゚ンチャヌ塩基性物質ず呌ばれる成分を添加するこずもある。本発明においおは、䞊蚘したようにこれにさらに、分子内に芪氎基ず疎氎基を有する界面掻性剀を配合するこずを特城ずしおいる。
このような配合のレゞストを甚いたパタヌン圢成に぀いお、そのプロセスの抂略断面図である図および図のプロセスで圢成したパタヌン付近の拡倧断面図である図を甚いお説明する。図に瀺すように、䞋地䞊に塗垃したレゞストでは、ポテンシャル゚ネルギヌの高い界面掻性剀がレゞストず空気の界面に配列する。このレゞストを図および図に瀺す露光及び珟像するこずで埗られるパタヌンにおいおも、界面掻性剀が配向し、これに䌎っお、レゞストを構成するポリマヌミクロ構造䜓も配向し、その結果、レゞストパタヌンのラむン゚ッゞラフネスも改善されるこずになる。すなわち、パタヌンの拡倧図である図に瀺すように、界面掻性剀の界面配列に䌎っお、ポリマヌミクロ構造䜓が配向する。このレゞストを構成するポリマヌ配向により、レゞストパタヌン界面でのポリマヌ䜍眮が敎列するため、結果ずしお界面の凹凞ラむン゚ッゞラフネスを枛少させるこずができる。
Hereinafter, the principle of pattern formation when the resist material is used will be described. A chemical amplification resist, which is a mixed material, is generally formed from a polymer, an acid generator (PAG), and an organic solvent that dissolves them, and a component called a quencher (basic substance) may be added. In the present invention, as described above, a surfactant having a hydrophilic group and a hydrophobic group in the molecule is further blended.
Pattern formation using a resist having such a composition will be described with reference to FIG. 1 which is a schematic cross-sectional view of the process and FIG. As shown in FIG. 1A, in the resist 11 applied on the base 10, a surfactant 13 having a high potential energy is arranged at the interface between the resist and air. Also in the pattern 11a obtained by exposing and developing the resist 11 as shown in FIGS. 1B and 1C, the surfactant is oriented, and accordingly, the polymer microstructure constituting the resist. As a result, the line edge roughness of the resist pattern is also improved. That is, as shown in FIG. 2 which is an enlarged view of the pattern, the polymer microstructure 12 is oriented with the interface arrangement of the surfactant 13. Due to the orientation of the polymer constituting the resist, the polymer positions at the resist pattern interface are aligned. As a result, the unevenness (line edge roughness: LER) at the interface can be reduced.

以䞋、本発明のプロセスを瀺す抂略断面図である図を甚いお本実斜の圢態の半導䜓補造方法を工皋順に説明する。   Hereinafter, the semiconductor manufacturing method of the present embodiment will be described in the order of steps with reference to FIG. 1 which is a schematic sectional view showing the process of the present invention.

たず、図に瀺すように、シリコンりェハ半導䜓基板䞊に各皮薄膜を圢成した䞋地局䞊に膜厚〜にレゞストを塗垃する。本実斜の圢態においおは、このレゞスト材料に、界面掻性剀を添加しお甚いるこずを特城ずしおいる。   First, as shown in FIG. 1A, a resist 11 is applied to a thickness of 200 to 300 nm on an underlayer 10 on which various thin films are formed on a silicon wafer semiconductor substrate. The present embodiment is characterized in that a surfactant is added to this resist material.

この工皋で、レゞストを塗垃した埌、レゞストが也燥するたでの時点で、この界面掻性剀は、レゞスト䞭を移動し、図に瀺すように、レゞストず空気の界面に配列する。䞊蚘したように、レゞストのポリマヌの偎鎖には、芪氎性基が存圚しおおり、この芪氎性基ず、界面掻性剀の芪氎性基が近接するように、界面掻性剀が配向するこずになる。   In this step, after the resist 11 is applied and until the resist 11 is dried, the surfactant 13 moves in the resist 11 and, as shown in FIG. Arrange at the interface. As described above, there is a hydrophilic group in the polymer side chain of the resist 11, and the surfactant 13 is disposed so that this hydrophilic group and the hydrophilic group 14 of the surfactant 13 are close to each other. Will be oriented.

次いで、レゞストを也燥し、℃以䞋の枩床で分皋床プリベヌク凊理を行った埌、図に瀺すように、図瀺しないマスクを甚いお、光、線たたは電子線にお露光する。   Next, after drying the resist and performing a pre-bake treatment at a temperature of 100 ° C. or less for about 15 minutes, as shown in FIG. 1B, exposure is performed with light, X-rays or electron beams using a mask not shown To do.

次いで、図に瀺すように、露光埌の熱凊理を経お、テトラメチルアンモニりムハむドロオキサむドのようなアルカリ珟像剀によっお珟像し、パタヌンを埗る。
この工皋における熱凊理は、ず呌ばれおいる「露光埌やきしめ」であり、露光時の定圚波の圱響によるパタヌン゚ッゞの凹凞を枛少させたり、あるいは、化孊増幅型レゞストの觊媒䜜甚による酞の発生を加速させたりするために行われるものであり、慣甚されおいる条件を採甚するこずができる。
Next, as shown in FIG. 1 (c), after the heat treatment after exposure, development is performed with an alkali developer such as tetramethylammonium hydroxide to obtain a pattern.
The heat treatment in this process is “post-exposure squeezing” called PEB, which reduces the unevenness of the pattern edge due to the influence of standing waves during exposure, or the acid action by the catalytic action of a chemically amplified resist. It is carried out to accelerate the generation of the above, and a conventionally used condition can be adopted.

図におけるパタヌン郚分の拡倧図を、図に瀺す。
アルカリ珟像工皋を経おパタヌンを構成する際、界面掻性剀はレゞスト䞊郚だけで無く、パタヌン偎壁郚にも移動しお界面に配列する。界面掻性剀は䜎分子で極性の高い皮類では、分子゚ネルギヌが高いために、即座にレゞスト䞭を移動しお界面に配列し易いず考えられる。パタヌン界面ぞ界面掻性剀が配列するこずにより、界面掻性剀の極性郚䜍芪氎性基がレゞスト内郚に向き、ポリマヌミクロ構造䜓の極性ず盞互䜜甚するこずでポリマヌのミクロ結晶構造自䜓の配向が起きる。
FIG. 2 shows an enlarged view of the pattern portion 18 in FIG.
When the pattern is formed through the alkali development process, the surfactant 13 moves not only on the resist 11 but also on the pattern side wall and is arranged on the interface. It is considered that the surfactant 13 having a low molecular weight and high polarity has a high molecular energy, so that it easily moves through the resist 11 and is easily arranged on the interface. By arranging the surfactant 13 on the pattern interface, the polar portion (hydrophilic group) 14 of the surfactant 13 is directed to the inside of the resist 11 and interacts with the polarity of the polymer microstructure, thereby causing a microcrystalline structure of the polymer. Its own orientation occurs.

以䞊のプロセスにより、パタヌン界面にポリマヌが均䞀に存圚し、レゞストポリマヌのミクロ構造を適正化するこずで、ラむン゚ッゞラフネスを䜎枛させるこずができる。そしお、このように、ラむン゚ッゞラフネスが䜎枛されたパタヌンを䞋地局の各皮加工に適甚した堎合、埮现パタヌンの半導䜓装眮を高い補造歩留たりで、補造するこずができる。
By the above process, the polymer exists uniformly at the pattern interface, and the line edge roughness can be reduced by optimizing the microstructure of the resist polymer. Thus, when a pattern with reduced line edge roughness is applied to various processing of the underlayer, a semiconductor device with a fine pattern can be manufactured with a high manufacturing yield.

本発明のレゞストを甚いた堎合のパタヌン圢成方法を工皋順に瀺す抂略断面図。The schematic sectional drawing which shows the pattern formation method at the time of using the resist of this invention in order of a process. 本発明の原理を説明するためのパタヌンの拡倧暡匏図。The enlarged schematic diagram of the pattern for demonstrating the principle of this invention. 埓来のレゞストによるパタヌン圢成方法を工皋順に瀺す抂略断面図。The schematic sectional drawing which shows the pattern formation method by the conventional resist in order of a process. 本発明が克服する珟象の芁因を瀺す図パタヌン断面図。The figure which shows the factor of the phenomenon which this invention overcomes (pattern sectional drawing).

笊号の説明Explanation of symbols

、䞋地局
、塗垃レゞスト
、レゞストの非露光領域
、レゞストの露光領域
、ポリマヌのミクロ構造䜓
界面掻性剀
芪氎性基
疎氎性基
、露光における゚ネルギヌ照射郚分を瀺す矢印
、パタヌン郚分

DESCRIPTION OF SYMBOLS 10, 30: Underlayer 11, 31: Application | coating resist 11a, 31a: Non-exposed area | region of resist 11b, 31b: Exposed area | region of resist 12, 32: Microstructure of polymer 13: Surfactant 14: Hydrophilic group 15: Hydrophobic groups 16, 36: Arrows indicating energy irradiation portions in exposure 18, 38: Pattern portions

Claims (4)

界面掻性剀を含有するレゞスト材料を、䞋地局衚面に塗垃・也燥しおレゞスト局を圢成する工皋ず、
前蚘レゞスト局に、光、線、もしくは電子線を照射しおレゞスト局を露光する工皋ず、
前蚘露光したレゞスト局を熱凊理する工皋ず、
前蚘熱凊理したレゞスト局をアルカリ珟像しお、端郚に凹凞のないパタヌンを圢成する工皋を少なくずも備えたこずを特城ずする半導䜓装眮の補造方法。
Applying a resist material containing a surfactant to the surface of the underlayer and drying to form a resist layer;
Irradiating the resist layer with light, X-rays or electron beam to expose the resist layer;
Heat treating the exposed resist layer;
A method of manufacturing a semiconductor device, comprising at least a step of alkali-developing the heat-treated resist layer to form a pattern without unevenness at an end portion.
前蚘レゞスト材料が、化孊増幅型レゞスト材料であるこずを特城ずする請求項に蚘茉の半導䜓装眮の補造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the resist material is a chemically amplified resist material. 前蚘界面掻性剀が、前蚘露光光によっお分解するこずのない界面掻性剀であるこずを特城ずする請求項たたは請求項に蚘茉の半導䜓装眮の補造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the surfactant is a surfactant that is not decomposed by the exposure light. 前蚘界面掻性剀が、前蚘熱凊理によっお揮発するものでない界面掻性剀であるこずを特城ずする請求項ないし請求項のいずれかに蚘茉の半導䜓装眮の補造方法。

4. The method of manufacturing a semiconductor device according to claim 1, wherein the surfactant is a surfactant that is not volatilized by the heat treatment.

JP2003351229A 2003-10-09 2003-10-09 Method for manufacturing semiconductor device Pending JP2005115171A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110189858A1 (en) * 2010-02-01 2011-08-04 Lam Research Corporation Method for reducing pattern collapse in high aspect ratio nanostructures
KR101082094B1 (en) 2007-12-28 2011-11-10 죌식회사 하읎닉슀반도첎 Method for depositing photoresist

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101082094B1 (en) 2007-12-28 2011-11-10 죌식회사 하읎닉슀반도첎 Method for depositing photoresist
US20110189858A1 (en) * 2010-02-01 2011-08-04 Lam Research Corporation Method for reducing pattern collapse in high aspect ratio nanostructures
WO2011094132A3 (en) * 2010-02-01 2011-10-13 Lam Research Corporation Method of reducing pattern collapse in high aspect ratio nanostructures
US8617993B2 (en) * 2010-02-01 2013-12-31 Lam Research Corporation Method of reducing pattern collapse in high aspect ratio nanostructures

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