JP2005101620A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be designed and changed in a short period of time.
In a plurality of wiring layers stacked on an element layer forming an element, a region where at least one wiring layer of the plurality of wiring layers intersects with an upper wiring layer of the wiring layer is provided. And a cross-shaped redundant wiring WR1 formed by the wiring WL of the at least one wiring layer and the wiring WU of the upper wiring layer. In other words, when it becomes necessary to provide a wiring WL that is orthogonal to the wiring WU due to a change in design, the redundant wiring WR1 and the redundant via hole that enable direct wiring by connecting the upper wiring WR2 to the redundant via hole VR. It has a VR structure.
[Selection] FIG.

Description

  The present invention relates to a semiconductor device having a structure in which a connection structure can be easily changed in accordance with a change in a layout design specification of the semiconductor device.

  In recent years, with the progress of higher functionality, higher performance, and miniaturization of electronic devices, there has been an increasing need for semiconductor devices (Application Specific Integrated Circuits: ASICs) for specific users that can be developed in a relatively short time. Yes. Therefore, in order to further shorten the development period of the ASIC, a gate array method and an embedded gate array method incorporating a part of the gate array method have been proposed.

  In the gate array method, gates arranged in an array prepared in advance as a master slice are wired according to the specifications of each user, thereby forming a logic circuit for each user. Since only the wiring design corresponds to the specifications of each user, the development cost can be reduced and the development period can be shortened.

  The embedded gate array method partially adopts the gate array method. Based on whether or not the specification is fixed, the functional circuit (also simply referred to as “element” or “cell”) is determined by a fixed circuit section (determined element or determined cell) and an undefined circuit section (undefined element or undefined). Cell). A standard cell system is used for the deterministic circuit section, and a gate array system is used for the undefined circuit section. After the specification of the undetermined circuit unit is determined, the arrayed gates formed in the undetermined circuit unit are wired according to the determined specification. According to this method, for example, a definite circuit section such as a memory section is completed up to layout design in advance, so the development period required for layout design is only the design period for the undefined circuit section, so the development period can be further shortened. Is possible. Furthermore, since standard cells can be used for the deterministic circuit portion, the degree of integration can be increased (the chip area can be reduced) compared to the gate array method. An embedded gate array type LSI is disclosed in Patent Document 1, for example.

  Here, definitions of terms used in this specification will be described with reference to FIG. What defines the geometric structure of an LSI is called a layout 900. The LSI layout 900 includes an element layout (cell layout) 920 that defines a functional circuit (or cell) and a wiring layout 940 that defines “wiring”. The element layout 920 has a plurality of element plane layouts 922, 923, 924, 925 and 926. The element plane layouts 922, 923, 924, 925, and 926 define an N-well, an active region, a polysilicon layer, a P + ion implantation region, and an N + ion implantation region, respectively. A plurality of wiring plane layouts 942, 943, 944, and 945 included in the wiring layout 940 respectively define contact hole, first wiring, through hole, and second wiring patterns. “Interconnection” includes not only interconnection in a plane but also interlayer connection through a through hole (via hole). In order to manufacture a semiconductor device using a normal photolithography process, a mask corresponding to each planar layout is manufactured.

  Even in the above-mentioned gate array type and embedded gate array type LSIs, as the number of gates and the number of wiring layers increase, the layout design takes time and the cost and time for mask production increase. There is a problem of doing. In particular, a mask for forming a fine pattern (for example, the design rule is 0.25 μm or less) is significantly more expensive than a conventional mask (for example, the design rule is 0.35 μm or more), and the number of layers is increasing. Therefore, the number of masks necessary for manufacturing one semiconductor device is also greatly increased (for example, six-layer wiring or more). As a result, an increase in cost and time required for manufacturing a mask is becoming a major factor that causes an increase in development cost of a semiconductor device and a prolonged development period.

  A conventional LSI layout design method will be described with reference to FIG.

  FIG. 21 shows a flowchart of a conventional layout design method in the case where a circuit change (change in connection structure) is necessary for a once designed LSI.

  In step S1700, layout design is performed based on the netlist N1 indicating the connection information of the initial specification. At this stage, an initial layout corresponding to the initial specification is generated. If no design change is required, an initial layout is output, and a mask (strictly, a set of masks) is produced based on the initial layout. The set of masks includes masks corresponding one-to-one to each planar layout of the initial layout.

  In step S1710, in response to the circuit change, a netlist N2 indicating the changed connection information is generated.

  In step S1720, layout design is performed again based on the netlist N2. Here, a modified layout corresponding to the changed specification is generated. The modified layout is generated completely independently of the initial layout. For example, in the case of the gate array system, all wirings are rewired.

In step S1730, the corrected layout corresponding to the netlist N2 is output. A mask is produced based on the output layout after correction.
US Pat. No. 4,786,631

  The prior art described above has the following problems. The problem will be described by taking as an example the case where the conventional layout method shown in FIG. 21 is applied to a gate array type LSI.

  When the layout of a gate array type LSI is changed based on the netlist N2 after the design change, only the wiring layout needs to be rewired (redesigned), but the rewiring is executed for all the wirings. Therefore, the number of steps for layout design and the number of masks, that is, the correction period and the correction cost cannot be reduced. If masks are produced based on the initial layout, all masks are discarded and a new mask is produced from the beginning. Furthermore, if a wafer (master slice) is put in a line for actually manufacturing an LSI, all work in progress must be discarded.

  For example, even for a minor change such as a change in an input / output signal or a pull-up change in a power supply system, all the masks for the wiring layer must be recreated according to the layout method described above. In addition, as the number of circuits integrated on a single chip increases, the possibility of changing specifications is increasing. Therefore, the increase in mask manufacturing costs and the increase in mask manufacturing time due to design changes are becoming serious problems. is there.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a semiconductor device that can be designed in a shorter period of time.

  The semiconductor device of the present invention has an element layer that forms a plurality of elements, and a plurality of wiring layers that are stacked on the element layer and form wirings that electrically connect the plurality of elements to each other, At least one wiring layer of the plurality of wiring layers has a redundant wiring provided in a region intersecting with a wiring formed in an upper layer of the at least one wiring layer, and the redundant wirings are at least mutually It has two conductor parts extending in the intersecting direction, whereby the above object is achieved.

  Another semiconductor device of the present invention includes an element layer that forms a plurality of elements, and a plurality of wiring layers that are stacked on the element layer and form wirings that electrically connect the plurality of elements to each other. In addition, a plurality of redundant wirings regularly arranged between the wirings formed in at least one of the plurality of wiring layers are provided, thereby achieving the above object.

  According to the semiconductor device of the present invention, when the circuit is changed due to the specification change, the layout can be easily changed, so that the development period of the semiconductor device can be shortened. For example, it is possible to quickly respond to a specification change after the layout design is once completed. In addition, it is possible to deal with layout changes accompanying changes in specifications with a minimum number of wiring plane layout changes. Accordingly, it is possible to reduce the time and cost for manufacturing the mask. Furthermore, since it is possible to limit the wiring plane layout for changing the layout to the uppermost wiring plane layout as much as possible (corresponding to the mask used in the later process of the semiconductor process), depending on the progress of the manufacturing process, It is possible to reduce manufacturing time and manufacturing cost without wasting the product.

  Further, the semiconductor device having redundant wiring according to the present invention has a structure that facilitates the layout change described above and easily optimizes the wiring characteristics (delay characteristics, etc.).

  According to the present invention, a semiconductor device that can be designed in a shorter period of time than before is provided.

  A flow chart of a layout method related to the present invention is shown in FIG.

  First, in step S100, a first netlist N1 is prepared. The first netlist may be generated corresponding to an initial specification of an LSI for a specific user, or may be generated corresponding to a general-purpose basic specification. Next, in step S200, a first layout is generated based on the first netlist N1. The first layout includes an element layout and a wiring layout. The element layout and the wiring layout have a plurality of element plane layouts and wiring plane layouts, respectively. Here, the wiring layout includes first to nth (n ≧ 2) wiring plane layouts sequentially stacked on the element layout. That is, the first wiring layout is the lowermost layer (immediately above the element layout), and the nth wiring planar layout is the uppermost layer. Up to step S200 can be performed by a conventional method. Further, the first layout may be created in advance and stored in a library.

  The element layout may partially include a gate array type element (functional circuit), but it is preferable to use a standard cell. By using standard cells, it is possible to achieve higher density and lower price as well as higher performance and higher functionality of LSI. When the layout design method related to the present invention is used, it becomes possible to cope with various specifications (specification changes) than the conventional ones only by changing the wiring layout of the multilayer wiring. There is no need to use a master slice, and an element layout using standard cells can be created. Further, an LSI to which the layout design method related to the present invention can be applied may be a system LSI including a plurality of macro cells (also referred to as IP) as well as a conventional ASIC. The system LSI corresponds to a macro cell replaced with the above standard cell.

  In step S300, a second netlist is prepared. The second netlist may correspond to a change in the specification of the LSI for the specific user, or may be a specification determination for the basic specification to correspond to the specification from the specific user.

  In the steps after step S400, the second layout corresponding to the second netlist N2 is generated by changing only the wiring layout.

  First, in step S400, n−1 or less wiring plane layouts are selected from the first to nth wiring plane layouts of the first layout. Subsequently, the physical configuration (pattern) of the selected n−1 or less wiring plane layouts is changed in step S500. In step S600, a second layout based on the second netlist is generated from the changed wiring plane layout and the remaining plane layout of the first layout (that is, the element plane layout and the non-selected wiring plane layout). . The specific method of process S400-process S600 is mentioned later. In order to realize various layouts by changing the wiring layout, it is preferable to include a redundant wiring pattern in advance in the wiring layout, as will be described later with respect to specific configuration examples and embodiments.

  According to the layout method related to the present invention, instead of changing the physical configuration of all the wiring plane layouts as in the prior art, it is only necessary to change the physical configuration of at most n-1 wiring plane layouts. The LSI can be designed for layout according to the specifications from the user. Accordingly, it is possible to reduce the time and cost for manufacturing the mask. The smaller the number of wiring plane layouts that can be changed, the greater the effect of reducing the time and cost for mask manufacturing.

  The position of the wiring plane layout to be changed is preferably the upper layer. If the mask is an upper layer, it is possible to proceed to the process that requires the mask in the LSI manufacturing process without waiting for the manufacturing of the correction mask, and thus the manufacturing time can be shortened. There may also be a situation where work in progress flowing through the production line can be avoided. These effects can also be obtained when a process of drawing with an electron beam is used without using a mask.

  Steps S400 to S600 in FIG. 1 can be performed, for example, according to the flowchart shown in FIG.

  In step S410, one wiring plane layout (kth wiring plane layout) is selected from the first to nth wiring plane layouts of the first layout. First, the uppermost wiring plane layout is selected with k = n. In step S510, the physical configuration (pattern) of the selected kth wiring plane layout is changed, and in step S610, the second kth wiring plane layout and the remaining plane layout are used for the second based on the second netlist. Generate a layout. Next, in step S612, it is determined whether or not the second layout has been successfully generated. If successful, the layout design is terminated. That is, the second layout is generated by correcting only the uppermost n-th wiring plane layout of the first layout.

  If it is determined in step S612 that the second layout could not be generated, and if k = 1 is not determined in step S614, k / k-1 is selected and changed as the lower wiring plane layout. Attempts to generate the second layout (repeating steps S410 to S610). The layout design is completed when the second layout is successfully generated. In addition, the process of process S510 and process S610 can be implemented using a well-known rip-up / reroute (RIPUP / REROUT) method.

  Here, the lip-up / reroute method will be described with reference to FIGS. 22 (a), 22 (b) and 22 (c). 22A shows the wiring plane layout before the change (part of the first layout), FIG. 22B shows the wiring plane layout after the rip-up, and FIG. 22C shows the reroute (rewiring). A later wiring plane layout (a part of the second layout) is shown.

  As shown by a broken line in FIG. 22A, two RT1s are connected to each other before the change. Assume that the connection relationship (logical relationship) is changed so that one terminal (upper side of the drawing) of RT1 becomes the RT2 terminal and is connected to the other RT2 terminal by the specification change. In this case, as shown in FIG. 22B, the wiring indicated by the broken line is ripped up (stripped). Thereafter, as indicated by the broken line in FIG. 22C, the RT2 terminals are connected to each other by the wiring indicated by the broken line. In addition, the maze wiring method can be used for the connection between two terminals, for example. For an explanation of the rip-up / reroute method and the connection method, see Jiri Soukup, “Circuit Layout”, Proc. of IEEE, Vol. 69, no. 10, pp. 1281-1304, 1981. Is incorporated herein by reference.

  That is, according to the flow shown in FIG. 2, a second layout generated by changing only the uppermost wiring plane layout is obtained. If the second layout cannot be generated by changing one wiring plane layout, this flow ends. In that case, the flow of FIG. 3 to be described later may be executed, or the second layout may be generated by changing all the wiring plane layouts.

  Steps S400 to S600 in FIG. 1 can also be performed according to the flowchart shown in FIG.

  When the method shown in FIG. 3 is used, all the first layouts obtained by changing any n−1 or less wiring plane layouts out of the n wiring plane layouts can be obtained.

  First, in step S420, n−1 or less (n ≧ 2) arbitrary wiring plane layouts are selected. The number of all combinations for selecting an arbitrary number of n−1 or less from n is the number obtained by adding all nCm from m = 1 to m = n−1. First, one combination is selected from all these combinations. Actually, it is preferable to select in order from the smallest value of m (the number of masks is small) and the number of the selected plane layout is large (as much as possible). The flow for selecting the first wiring plane layout in order from the nth wiring plane layout with m = 1 can be realized as the same flow as in FIG. A flow for selecting a plurality of wiring plane layouts can be easily realized.

  Steps S520 and S620 can be performed using, for example, a rip-up / reroute method, similarly to the steps S510 and S610 of FIG. In step S622, it is determined whether the second layout has been successfully generated. If it is determined in step S622 that the generation of the second layout has failed, and if it is determined in step S624 that it is not the last combination, steps S420 to S620 are repeatedly executed for other combinations. The

  If it is determined in step S622 that the second layout has been successfully generated, information in which the changed wiring plane layout number and the changed plane wiring layout are set as one set is generated in step S630. . When the layout design method related to the present invention is executed using a computer, this information is stored at least temporarily in the storage device. Thereafter, when it is determined in step S632 that it is not the last combination, steps S420 to S620 are repeatedly executed for other combinations.

  When all of the combinations of n−1 or less wiring plane layouts are performed, Steps S420 to S630 are performed, and the second layout is obtained by changing the n−1 or less wiring plane layouts. For the combinations, a set of {changed wiring plane layout number, changed wiring plane layout} is generated. In other words, a set of all solutions that can generate the second layout is obtained under the condition that the number of masks less than n is changed.

  Next, for example, the most preferable solution is selected from all the solutions prepared in step S640 according to conditions such as the number and number of planar layouts allowed to be changed, and the layout design flow is terminated. For example, an optimal mask (wiring plane layout) is selected with respect to conditions such as the minimum number of masks and the masks positioned as high as possible. For example, when a mask (a set of masks) based on the first layout is actually manufactured, the number of masks is more important than the position of the mask (whether it is an upper layer or a lower layer) in order to reduce the correction mask cost. It is. On the other hand, when the LSI is actually manufactured in the manufacturing line, it is preferable to provide the position of the mask so that only the mask used in the manufacturing process that has not yet started is changed.

  As described above, when the layout method related to the present invention is used, it is necessary to change all the wiring plane layouts in the past. Can respond. Therefore, the cost and time required for manufacturing the mask can be reduced.

  It should be noted that in step S612 and step S622 in the flowcharts shown in FIG. 2 and FIG. 3, only the success or failure of the generation of the second layout is determined. Thus, success / failure may be determined.

(First configuration example)
A mask design method according to a first configuration example relating to the present invention will be described with reference to FIGS. In the first configuration example, an example in which a layout design method related to the present invention is used for mask correction will be described.

  In this configuration example, based on the initial layout designed based on the initial netlist N1 and the changed netlist N2 after the circuit change, only a higher wiring layer (also referred to as a metal layer) is corrected. The purpose is to change the initial layout to a corrected layout after correction based on the changed netlist N2.

  FIG. 4 is a flowchart of the mask design method according to this configuration example. First, in step S1100, layout design is performed based on the initial netlist N1 to form an initial layout.

  Next, in step S1200, a post-change netlist N2 describing a circuit change based on the generated specification change is input. Through the above steps S1100 and S1200, it is possible to obtain an initial layout based on the initial netlist N1 and a post-change netlist N2 which is connection information on which the layout is changed.

  Next, in step S1300, a correction mask to be corrected is estimated. In step S1300, after sequentially estimating the wiring layer necessary for correcting from the initial layout based on the initial netlist N1 to the layout based on the changed netlist N2, the wiring layer after the wiring layer is estimated from the uppermost wiring layer of the initial layout. To modify the layer, the mask to be modified, i.e. the modified mask, is determined. And the correction mask information R about the correction mask is created.

  Next, in step S1400, based on the created correction mask information R, a process (rip-up) for peeling off the wiring layer to be corrected is performed.

  Next, after rewiring is performed in accordance with the changed netlist N2 in step S1500, the modified layout result generated in steps S1100 to 1500 is output in step S1600.

  Here, the feature of the mask design method according to this configuration example is that the correction mask corresponding to the wiring layer to be corrected among all the wiring layers is estimated and determined in order from the upper wiring layer, and the generated correction mask information R Based on this, rewiring is performed, and the corrected layout result is output. As a result, only a minimum number of masks need be changed in design and mask manufacturing.

  As described above, according to this configuration example, when there is a circuit change, it is not necessary to perform design change and mask manufacturing for all the wirings, and from the upper wiring layer based on the corrected mask information R created by estimation. Only for the minimum number of masks, design changes and mask manufacturing are performed. Accordingly, it is possible to reduce the cost required for the design change and manufacture of the mask, that is, the correction cost, and it is possible to shorten the period necessary for the mask change, and thus the LSI development period can be shortened.

  Further, the correction is made from the uppermost wiring layer formed in a process close to the final stage of the manufacturing process. As a result, even when the manufacturing of the LSI has progressed to some extent, it is possible to cope with a circuit change. Therefore, the turnaround time required for LSI correction can be shortened.

  Furthermore, the mask design method of this configuration example can be applied to methods other than the method of designing an LSI by combining basic circuits composed of transistors. Therefore, the circuit area can be optimized and the area of the LSI can be reduced, so that the cost of the LSI can be reduced.

  The design change and layout transition according to the flow of FIG. 4 will be specifically described with reference to FIGS. 4 and 5. FIG. 5A to FIG. 5C are pattern diagrams showing layouts before, during, and after modification of layouts that are subject to design changes. Here, the transition of the layout will be described in the case where the metal layers are three of the wiring layers, that is, the layout design is performed as the metal layers M3, M2, and M1 in order from the top layer. In this case, the wiring layer is composed of a total of five layers including three metal layers and two interlayer connection layers for connecting the metal layers. In FIG. 5, wirings M2a, M2b,... Belong to the metal layer M2, and wirings M3a, M3c,. Further, the via holes V3a, V3b,... Are via holes belonging to the interlayer connection layer V3 for connecting wirings belonging to the metal layer M3 and the metal layer M2, respectively.

First, in step S1100 of FIG. 4, an initial layout is designed based on the initial netlist N1. Here, for example, the initial netlist N1 is as follows for the terminals A to D.
net1 connect (A, B)
net2 connect (C, D)
It has become. The initial netlist N1 indicates that the terminal A and the terminal B are connected and the terminal C and the terminal D are connected. Initial wiring is performed based on the initial netlist N1 to obtain the initial layout 10 shown in FIG. That is, as shown in FIG. 5A, the terminals A and B are connected via the wiring M2a, the via hole V3a, the wiring M3a, the via hole V3b, and the wiring M2b. Similarly, the terminals C and D are connected via the wiring M2c, the via hole V3c, the wiring M3c, the via hole V3d, and the wiring M2d.

Next, in step S1200, a post-change netlist N2 is obtained. Here, for example, the post-change netlist N2 is about the terminals A to D.
net1 connect (A, C)
net2 connect (B, D)
It has become. The post-change netlist N2 indicates that the terminal A and the terminal C are connected and the terminal B and the terminal D are connected.

  Next, in step S1300, based on the post-change netlist N2, a mask to be corrected is estimated to generate corrected mask information R. Here, it is assumed that the metal layer M3 is obtained as the correction mask information R.

  Next, in step S1400, lip-up of the correction mask is performed based on the correction mask information R. That is, the metal layer M3 is riped up based on the correction mask information R, and wiring layer data including data of the remaining wiring layers is generated. In this step, since the correction mask information R is not included, the interlayer connection layer V3 is not peeled off. As a result, as shown in FIG. 5B, the wirings M3a and M3c belonging to the metal layer M3 are removed from the initial layout 10 to obtain the layout 11.

  Next, in step S1500, based on the wiring layer data, rewiring is performed in accordance with the changed netlist N2, and the modified layout 20 shown in FIG. 5C is obtained. That is, the terminals A and C are connected via the wiring M2a, the via hole V3a, the wiring M3a ', the via hole V3c, and the wiring M2c. Similarly, the terminals B and D are connected via a wiring M2b, a via hole V3b, a wiring M3b ', a via hole V3d, and a wiring M2d.

  Here, according to the conventional design method including the gate array method and the embedded gate array method, when the circuit is changed as described above, the three metal layers M1 to M3 and the two interlayer connection layers are used. It was necessary to change the design of the total of five masks corresponding to the above and to manufacture them. In contrast, according to the present configuration example, only one mask corresponding to the metal layer M3 needs to be changed in design and manufactured. As a result, it can be seen that the period required for mask change and the correction cost can be greatly reduced.

  Hereinafter, the step of creating the correction mask information R by estimating the correction mask, that is, step S1300 of FIG. 4 will be described with reference to FIGS. FIG. 6 is a flowchart of step S1300 of FIG.

  First, in step S1310, as the correction mask information R, the metal layer M3 which is the uppermost layer among the wiring layers is set, and R = {M3}.

  Next, in step S1320, as in step S1400 of FIG. 4, wiring belonging to the metal layer M3 specified by the correction mask information R from the initial layout 10 shown in FIG. The wiring layer data including the data of the remaining metal layers M2 and M1 and the interlayer connection layer V3 is generated by peeling. As a result, the layout 11 shown in FIG. 5B is obtained.

  Next, in step S1330, similar to step S1500 in FIG. 4, virtual rewiring is performed according to the changed netlist N2 based on the wiring layer data. As a result, when the wiring connection is successful, the modified layout 20 shown in FIG. 5C is obtained.

  Next, in step S1340, it is determined whether or not the wiring connection is successful by virtual rewiring. If the wiring connection is successful, that is, if the wiring correction process is completed by rewiring, the process proceeds to step S1350, and the correction mask information R = {M3} set in step S1310 is output as it is. . Then, the process of estimating the correction mask and creating the correction mask information R, that is, the process S1300 of FIG. On the other hand, if the wiring cannot be corrected by virtual rewiring, the process proceeds to step S1360.

  Next, in step S1360, it is determined whether the corrected mask information R indicates all wiring layers. Here, when the correction mask information R indicates all wiring layers, the circuit cannot be changed even if all the wiring layers are corrected, and correction including transistor arrangement is necessary. Therefore, the process proceeds to step S1370, and after setting the correction mask information R as R = {φ} in step S1370, the correction mask information R (= {φ}) is output in step S1350, and the step of FIG. S1300 is ended. On the other hand, if the correction mask information R does not indicate all wiring layers, the process proceeds to step S1380.

  Next, in step S1380, the uppermost wiring layer among the wiring layers belonging to the lower wiring layer not included in the correction mask information R is added to the correction mask information R, and the process returns to step S1320. Then, the process is repeated from step S1320, that is, from the step of virtually rip-up the added wiring layer.

  The processing according to the flow of FIG. 6 and the transition of the layout will be specifically described with reference to FIG. FIG. 7A to FIG. 7C are pattern diagrams showing layouts before, during, and after modification of layouts that are subject to design change. FIG. 7A shows the same initial layout as FIG.

  In step S1320 of FIG. 6, the metal layer M3 is virtually riped up from the initial layout 10 shown in FIG. 7A to obtain the same layout 11 as shown in FIG. 5B.

  Here, a case where rewiring cannot be performed in step S1330 is considered. In this case, in step S1340, it is determined that rewiring has not been performed, and the process proceeds to step S1360. In step S1360, since the correction mask information R is R = {M3} and not all wiring layers, the process proceeds to step S1380.

  In step S1380, since the uppermost layer in the wiring layer lower than the metal layer M3 indicated by the correction mask information R is the interlayer connection layer V3, the process returns to step S1320 after setting R = {M3, V3}.

  In step S1320, the wiring layer added to the correction mask information R, that is, the interlayer connection layer V3 is virtually riped up to generate wiring layer data, and the layout 12 shown in FIG. 7B is obtained.

  Further, in step S1330, the wirings M3a ″ and the via holes V3a ′ and V3c ′ belonging to the interlayer connection layer V3 are used to connect the terminals A and C to the via holes V3b ′ and V3d belonging to the wiring M3b and the interlayer connection layer V3. Are used to virtually connect the terminals B and D. As a result, the modified layout 20 'shown in FIG. 7C is obtained.

  As described above, according to the process of estimating the correction mask of the design method according to the present configuration example, based on the virtual rip-up (step S1320 in FIG. 6) and rewiring (step S1330 in FIG. 6), respectively. Then, the correction mask information R necessary for the layout design according to the post-change netlist N2 can be reliably generated.

  In this configuration example, the determination condition for creating the correction mask information R is based only on whether or not rewiring can be performed based on the changed netlist N2 as in step S1340 in FIG. However, the correction mask information R may be created by evaluating the wiring characteristics. In this case, each via hole can be selected from the interlayer connection layer V3 in consideration of wiring characteristics, so that a modified layout having excellent wiring characteristics can be obtained with certainty. For example, in the case shown in FIG. 7, the wiring length is short as shown in FIG. 7C by generating the corrected mask information R by evaluating the wiring length as the wiring characteristic, that is, the wiring resistance. It is possible to surely realize an excellent corrected layout with a small size.

(Second configuration example)
A mask design method and a semiconductor device according to a second configuration example of the present invention will be described with reference to FIGS. In this configuration example, the layout of the semiconductor device is set in advance so that the layout can be easily corrected regardless of whether the circuit is changed, thereby facilitating the design change and preventing the deterioration of the wiring characteristics after the change. It is aimed.

  FIG. 8 is a flowchart of the mask design method according to this configuration example. The mask design method shown in FIG. 8 is the same as the mask design method shown in FIG. 4 in that an initial layout is designed in step S1100 and step S1150 is added to facilitate design change. Layout conversion is performed for the purpose of facilitating correction.

  Hereinafter, the correction facilitating process in step S1150 of FIG. 8 will be described with reference to FIG. FIGS. 9A to 9D show layouts to be subjected to design change, before the simplification process, after the simplification process, after the simplification process and after the design, and after the simplification process and after the circuit change. FIG. FIG. 9A shows the same layout 12 as FIG. 7B in the first configuration example. The layout 12 is a layout composed of only the metal layer M2 by removing the metal layer M3 and the interlayer connection layer V3 from the initial layout 10 shown in FIG. 7A in the first configuration example.

  In step S1150 of FIG. 8, the wiring M2a that was one wiring in the layout 12 shown in FIG. 9A is divided into a wiring M2a1 and a wiring M2a2 as shown in FIG. 9B. Similarly, the wiring M2c is divided into the wiring M2c1 and the wiring M2c2, and the wiring M2d is divided into the wiring M2d1 and the wiring M2d2. The wiring M2b is not divided because it is shorter than the predetermined reference compared to the predetermined reference. As a result, the easy layout 13 shown in FIG. 9B is obtained.

  Here, as in the first configuration example, when the layout is designed based on the initial netlist N1, the layout 10 'shown in FIG. 9C is obtained. That is, the wirings M2a2, M3a1, M2a1, M3a2, M2b and the vias belonging to the interlayer connection layer V3 are used to connect the terminals A and B, and the wirings M2c2, M3c1, M2c1, M3c2, M2d2, M3c3, M2d1 The terminals C and D are connected using each via hole belonging to the interlayer connection layer V3. As a result, the layout 10 'satisfying the connection of the initial netlist N1 can be obtained in the same manner as the initial layout 10 shown in FIG.

  Further, when the circuit is changed as in the first configuration example, the layout is designed based on the changed netlist N2, for example, and the modified layout 20 '' shown in FIG. 9D is obtained. In this case, the terminals A and C are connected using the wirings M2a2, M3a ′, M2c2 and the respective via holes belonging to the interlayer connection layer V3, and the wirings M2b, M2b ′, M2d1 and the respective layers belonging to the interlayer connection layer V3 are connected. The terminals B and D are connected using via holes. As can be seen by comparing the modified layout 20 ″ shown in FIG. 9D with the modified layouts 20 and 20 ′ according to the first configuration example (see FIGS. 5C and 7C). In the modified layout 20 ″, the connection between the terminals A and C and between the terminals B and D is realized by a short wiring.

  Here, the feature of the mask design method according to this configuration example is that the wiring that can be drawn by one line is divided in advance. As a result, when the layout is corrected by changing the circuit, the layout can be easily corrected, and the wiring resistance and the wiring capacitance can be reduced by optimizing the wiring length, that is, by correcting with a shorter wiring. Therefore, signal delay due to wiring can be improved by improving wiring characteristics.

  FIGS. 10A to 10D and FIGS. 11A and 11B show an initial layout in the metal layer M2 and various facilitating processes for the initial layout in the modification of the design method according to the present configuration example. FIG. 6 is a pattern diagram showing the results and the results after the design change. FIG. 10A shows an initial layout 30 made of only the metal layer M2. Then, in the simplification process of the present modification, as shown in FIG. 10B, a wiring that is not used in the initial layout 30, that is, a redundant wiring M2h is added to the empty area between the wirings M2s. A layout 31 is obtained.

  According to this modification, by using the easy layout 31 to which the redundant wiring M2h is added, the wiring pattern that can be used in the metal layer M2 in the wiring correction after the metal layer M3 and the interlayer connection layer V3 are peeled off is obtained. Can be increased. Therefore, by increasing the wiring pattern in the metal layer M2 using the redundant wiring M2h, it is possible to optimize the wiring length and facilitate rewiring.

  Another design method can be further combined with this modification. For example, FIG. 10C shows a simplified layout obtained by applying the design method in which the wiring is divided in advance to the layout shown in FIG. 10B, that is, the method described earlier in this configuration example. 32. According to this method, by dividing the wiring M2s and the redundant wiring M2h in advance, the wiring pattern that can be used in the metal layer M2 in the wiring correction after the metal layer M3 and the interlayer connection layer V3 are peeled off is obtained. It can be increased further. Therefore, as shown in FIG. 10D, wiring can be performed by using the wiring M2s, the via hole V3e belonging to the interlayer connection layer V3, and the short wiring M3e belonging to the metal layer M3. As a result, the wiring length can be optimized to facilitate rewiring, and a layout 30 ′ that is electrically equivalent to the initial layout 30 can be obtained.

  Further, as shown in FIG. 11A, a plurality of redundant via holes V3f are added to the layout 30 ′ shown in FIG. It can be wired. As a result, a layout 30 ″ as shown in FIG. 11B is obtained. In this case, by using the wiring M2s, the via hole V3e, and the wiring M3e, a layout that is electrically equivalent to the initial layout 30 shown in FIG. 10A can be obtained, and further, the redundant wiring M2h A wiring can be added using the redundant via hole V3f and the wiring M3f. That is, since the redundant via hole V3f is used more effectively for the wiring belonging to the higher-order metal layer M3, the metal layers M2 and M3 can be more effectively used for easy rewiring and the wiring length is optimized. be able to. In this case, it is preferable to arrange redundant via holes in a staggered manner in order to use other metal layers more effectively.

  It should be noted that each simplified layout used in this configuration example, that is, each simplified layout shown in FIGS. 9B, 10B, 10C, and 11A. 13, 31, 32, and 33 may be formed in advance in the semiconductor device. According to this, when the circuit is changed, the wiring length is optimized to improve the wiring characteristics, and a semiconductor device that can easily cope with the circuit change is realized.

  In the above description of each configuration example, the three-layer metal wiring has been described. However, the present invention is not limited to this, and it is apparent that the same effect can be obtained in a two-layer metal wiring or a metal wiring having four or more layers.

  Further, in each configuration example, when the region to be changed is a part of the layout, or the metal wiring division, redundant wiring, or redundant via hole used for the correction facilitating process is used for a part of the layout. Needless to say, the effectiveness does not change.

  The configuration example relating to the present invention can also be applied to a system LSI. Many system LSIs are manufactured for specific users in the same way as ASICs. Therefore, the problems of the prior art described for the ASIC also exist for the current system LSI. Therefore, the development time and cost of the system LSI can be reduced by applying the configuration example relating to the present invention to the system LSI.

  FIG. 12 schematically shows a top view of the system LSI 50. The system LSI 50 includes a plurality of macro blocks (sometimes called IP or core) 52 and inter-macro wiring 54. The macro block 52 is, for example, a CPU, a DSP circuit, a RAM, a ROM, a clock / timing circuit, an I / O circuit, or the like. Many of the macroblock layouts can be stored in the cell library. Therefore, the layout design of the system LSI for a specific user can be performed only by designing the layout between the macroblocks after selecting a necessary macroblock from the macro library. The layout design method of the structural example regarding this invention can be used for this wiring between macroblocks.

  That is, when the macroblock wiring is formed by multilayer wiring, a desired system LSI layout can be designed by changing the wiring plane layout located as few as possible and / or as high as possible. In order to increase the degree of freedom in design, it is preferable to divide long wires or provide redundant wires (including redundant via holes) as described in the second configuration example. In addition, it is preferable to have a structure in which the input / output terminals of the redundant transistor can be connected by the uppermost wiring layer and a switch box for higher wiring in the channel region.

(Embodiment)
Hereinafter, with reference to FIGS. 13 to 19, an embodiment of a wiring layout including redundant wiring that is preferably used in a semiconductor device (including an ASIC and a system LSI) of the present invention will be described in comparison with a conventional wiring layout. To do.

  FIGS. 13 (a) and 13 (b) show two wiring plane layouts of conventional semiconductor device layout (via holes are interposed), and FIGS. 14 (a) and 14 (b) show the present invention. 2 shows two wiring plane layouts of the layout of the semiconductor device. FIGS. 13A and 14A show a state in which two wiring plane layouts are overlapped, and FIGS. 13B and 14B show a lower wiring plane layout.

  As shown in FIG. 13A, in the conventional semiconductor device, the upper layer wiring WU and the lower layer wiring WL are connected to each other at a point where they intersect with each other via the via hole V. In addition, as shown in FIG. 13B, no wiring is provided in a region where the lower layer wiring WL is unnecessary. On the other hand, as shown in FIGS. 14A and 14B, in the semiconductor device of the present invention, the redundant wiring WR and the redundant via hole VR are provided. As shown in FIG. 14B, the redundant wiring WR1 is formed in a region where no wiring is formed in the conventional lower layer wiring plane layout (FIG. 13B). The redundant wiring WR2 is formed in a region where the lower layer wiring WL and the upper layer wiring WU intersect. The redundant wiring WR2 is a single continuous wiring (FIG. 13B) in the conventional layout (FIG. 13B). The redundant wiring WR2 is divided into two at a region intersecting with the upper wiring WU. It is formed between the wirings of the book. Redundant wirings WR1 and WR2 have a cross shape. One direction of the cross is parallel to WU and the other is parallel to WL. In other words, redundant wirings WR1 and WR2 have two conductor portions extending in directions intersecting each other (different directions, typically orthogonal directions). The redundant wirings WR1 and WR2 and the redundant via hole VR can be generated, for example, in step S1150 shown in FIG.

  Next, it will be described with reference to FIGS. 15 and 16 that the wiring layout can be easily changed by using the cross-shaped redundant wiring.

  FIG. 15 shows a conventional layout in which two wirings WL and WU intersect each other, where (a) shows an overlapping state, (b) shows a lower layer layout, and (c) shows an upper layer layout. 16A and 16B show a layout having redundant wiring according to the present invention, in which FIG. 16A shows an overlapped state, FIG. 16B shows a lower layer layout, and FIG. 16C shows an upper layer layout.

  As can be seen from a comparison between FIG. 15B and FIG. 16B, in the lower layer layout according to the present invention, the lower layer wiring WL is divided into two at the intersection, and a cross-section is formed in the region between the divided WLs. The redundant wiring WR1 is provided. On the other hand, as shown in FIG. 16C, the upper layer layout according to the present invention has a redundant wiring WR2 provided in a direction orthogonal to the upper layer wiring WU (so as to overlap the lower layer wiring WL). These wirings are connected to each other using via holes VR as shown in FIG. 16A, thereby forming two wirings that intersect each other.

  Further, by using the same pattern as that of FIG. 16B for the lower layer wiring WL and using the pattern of the redundant via hole VR ′ and the upper layer wiring WU as shown in FIG. 17B and FIG. 17C. The wiring having the pattern shown in FIG. 17A can be obtained. That is, a wiring different from the connection structure shown in FIG. 16A can be realized only by changing the pattern of the via hole and the pattern of the upper layer wiring.

  Further, the redundant wiring pattern is not limited to a cross shape, and may be any shape having two conductor portions extending in mutually intersecting directions (different directions, typically orthogonal directions). For example, an S-shape as shown in FIG. 18A or an H-shape as shown in FIG. 18B may be used. Further, as shown in FIGS. 18A and 18B, if the redundant wiring WR is arranged so as to have a conductive portion overlapping with the upper wiring WU, the wiring layout can be easily changed. Can do.

  Furthermore, it is preferable to arrange the redundant wiring described above in the empty area in the conventional wiring layout unless there is a special reason. For example, as shown in FIGS. 19A and 19B, a plurality of cross-shaped redundant wirings WR may be regularly arranged. The shape of the redundant wiring WR is not limited to a cross, and may be S-shaped or H-shaped.

5 is a flowchart of a layout design method related to the present invention. It is a flowchart of the other layout design method relevant to this invention. It is a flowchart of the other layout design method relevant to this invention. It is a flowchart of the mask design method which concerns on the 1st structural example regarding this invention. (A)-(c) is a pattern figure which shows the layout before correction, during correction, and the layout after correction about the layout used as the object of the design change in a 1st structural example, respectively. It is a flowchart which shows the detail of the process which estimates a correction mask in process S1300 of FIG. (A)-(c) is a pattern figure which shows the layout before correction, during correction, and after correction about the layout used as the object of design change, when estimating a correction mask, respectively. It is a flowchart of the mask design method which concerns on the 2nd structural example of this invention. (A)-(d) are the design change target in the second configuration example, before the simplification process, after the simplification process, after the simplification process and after the design, and after the simplification process and the circuit change. It is a pattern figure which shows each subsequent layout. (A) shows the initial layout by one metal layer in the modification of the design method according to the second configuration example, (b) shows the result of the simplification process in this modification, and (c) shows another simplification process. (D) is the pattern figure which shows the layout after designing using (c), respectively. (A) is the result of the simplification process for one metal layer and an interlayer connection layer in another modification of the design method according to the second configuration example, and (b) is designed using (a). It is a pattern figure which shows each subsequent layout. It is a figure which shows the upper side figure of a system LSI typically. It is a figure which shows two wiring plane layouts (via hole is interposed between) of the layout of the conventional semiconductor device. It is a figure which shows two wiring plane layouts of the layout of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the conventional layout where two wiring WL (lower layer) and WU (upper layer) mutually cross | intersect. It is a figure which shows the layout which has the redundant wiring which concerns on embodiment of this invention in which two wiring WL (lower layer) and WU (upper layer) mutually cross | intersect. It is a figure which shows the other layout which has the redundant wiring which concerns on embodiment of this invention in which two wiring WL (lower layer) and WU (upper layer) mutually cross | intersect. It is a figure which shows the pattern of the redundant wiring which concerns on embodiment of this invention. It is a figure which shows the example of arrangement | positioning of several redundant wiring which concerns on embodiment of this invention. It is a typical top view which shows the layout of a semiconductor device. It is a flowchart of the conventional mask design method when a circuit change occurs. (A) shows the wiring plane layout before the change (part of the first layout), (B) shows the wiring plane layout after the rip-up, and (C) shows the wiring plane after the reroute (rewiring). It is a figure which shows a layout (a part of 2nd layout).

Explanation of symbols

10, 30 Initial layout 13, 31, 32, 33 Simplified layout 20, 20 ', 20''Modified layout A, B, C, D terminals

Claims (2)

An element layer forming a plurality of elements;
A plurality of wiring layers that are stacked on the element layer and form wirings that electrically connect the plurality of elements to each other;
At least one wiring layer of the plurality of wiring layers has a redundant wiring provided in a region intersecting with a wiring formed in an upper layer of the at least one wiring layer, and the redundant wirings are at least mutually A semiconductor device having two conductor portions extending in a crossing direction. An element layer forming a plurality of elements;
A plurality of wiring layers that are stacked on the element layer and form wirings that electrically connect the plurality of elements to each other;
A semiconductor device having a plurality of redundant wirings regularly arranged between wirings formed in at least one wiring layer of the plurality of wiring layers.

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