JP2005175214A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arrange a certain amount of power source capacitance inside a chip even if core transistors are integrated at high density.
SOLUTION: A plurality of core transistors 100 arranged inside a chip, a plurality of I / O cells 10 arranged so as to surround the plurality of core transistors 100, a power supply wiring 12 and a ground wiring of the plurality of core transistors 100 14 and at least one dummy transistor, which is a transistor adjacent to the I / O cell 10, among the plurality of core transistors 100, an inter-power source capacitive element provided between the power source wiring 12 and the ground wiring 14 Capacitor element wirings 42 and 44 connected to the power supply wiring 12 and the ground wiring 14 so as to function as 200 are provided.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device capable of arranging a certain amount of inter-power source capacitance inside a chip even when core transistors are integrated at a high density, and a method for manufacturing the same.

FIG. 18 is a plan view of a conventional semiconductor device. In this semiconductor device, a core transistor (not shown) is formed in an internal region 330 surrounded by a plurality of I / O cells 310 and wiring pads 320. In recent years, the core transistors in the inner region 330 have been integrated at high density and have been operated at high speed. For this reason, when the core transistor in the internal region 330 operates at high speed, the high-frequency component becomes noise and may be reflected outside the semiconductor device. In order to prevent this, a capacitive element, that is, an inter-power capacitive element may be provided between the power supply wiring and the ground wiring of the core transistor in the internal region 330 (see, for example, Patent Document 1).
JP 2000-58751 A

As a place where the inter-power supply capacitor is arranged, an empty area in which the core transistor is not formed in the internal area surrounded by the I / O cells can be considered. However, as the integration of core transistors increases, the empty area decreases, so that it may be difficult to dispose the required amount of capacitive elements. In some cases, the capacitive element may not be arranged.
The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device capable of arranging a certain amount of inter-power source capacitance inside a chip even if the core transistors are integrated at high density. The manufacturing method is provided.

In order to solve the above-described problems, a semiconductor device according to the present invention includes:
A plurality of core transistors including dummy transistors that are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
Capacitor element wiring connected to the power supply wiring and the ground wiring so that at least one of the dummy transistors functions as a power supply capacitive element provided between the power supply wiring and the ground wiring. ,
The dummy transistor is disposed next to the plurality of I / O cells.

According to this semiconductor device, the dummy transistor functions as the inter-power source capacitive element. For this reason, it is not necessary to newly secure a space for arranging the inter-power source capacitive element. Therefore, even if the integration rate of the core transistor is increased, a certain amount of the inter-power source capacitance element can be arranged to reduce noise reflected from the core transistor to the outside.
The dummy transistors may be arranged over the entire periphery of the peripheral portions of the plurality of core transistors, and the capacitor element wiring may cause each of the plurality of dummy transistors to function as an inter-power source capacitor element.

  When the dummy transistor is a P-channel MOS transistor, the capacitor element wiring may have the gate electrode, the source region, and the drain region connected to the ground wiring and the well connected to the power supply wiring. When the dummy transistor is an N-channel MOS transistor, the capacitor element wiring may have the gate electrode, the source region and the drain region connected to the power supply wiring and the well connected to the ground wiring.

  When the dummy transistor is a P-channel MOS transistor, the capacitor element wiring may have the gate electrode connected to the ground wiring and the source region and the drain region connected to the power supply wiring. When the dummy transistor is an N-channel MOS transistor, the capacitor element wiring may have a gate electrode connected to a power supply wiring and a source region and a drain region connected to a ground wiring. In these cases, in the dummy transistor, at least two adjacent gate electrodes and two gate insulating films are connected to each other, and the area of the gate electrode and the gate insulating film may be larger than that of the other core transistors. In this case, since the capacitance per power source capacitive element can be increased, noise reflected from the core transistor to the outside can be further reduced.

Other semiconductor devices according to the present invention are:
A plurality of core CMOS transistors including dummy CMOS transistors which are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core CMOS transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core CMOS transistors;
A capacitor element wiring connected to the power supply wiring and the ground wiring so that at least one of the dummy CMOS transistors functions as an inter-power supply capacitive element provided between the power supply wiring and the ground wiring; And
The dummy CMOS transistor is arranged next to the plurality of I / O cells.

  When the dummy CMOS transistor is composed of a P-channel MOS transistor formed in the N-type well and an N-channel MOS transistor formed in the P-type well, the capacitor element wiring includes the gate electrode, the source region, and the drain region of the P-channel MOS transistor. Each is connected to the ground wiring, the N-type well is connected to the power supply wiring, the gate electrode, the source region and the drain region of the N-channel MOS transistor are connected to the power supply wiring and the P-type well is connected to the ground wiring. Also good. The capacitor element wiring connects the gate electrode of the P-channel MOS transistor to the ground wiring, connects the source region and the drain region to the power supply wiring, connects the gate electrode of the N-channel MOS transistor to the power supply wiring, and connects the source region and The drain region may be connected to the ground wiring.

Other semiconductor devices according to the present invention are:
A plurality of core transistors arranged in the chip;
A voltage power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
A logic circuit configured using a part of the plurality of core transistors;
Capacitor element wiring connected to the power supply wiring and the ground wiring so that the core transistor that has not been used as the logic circuit functions as an inter-power supply capacitance element provided between the power supply wiring and the ground wiring. It comprises.

  According to this semiconductor device, the core transistor that has not been used as a logic circuit is caused to function as an inter-power source capacitive element. For this reason, it is not necessary to newly provide a space for arranging the inter-power source capacitive element. Therefore, even if the integration rate of the core transistor is increased, a plurality of inter-power source capacitance elements can be arranged to reduce noise reflected from the core transistor to the outside.

Other semiconductor devices according to the present invention are:
A plurality of core transistors including dummy transistors that are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
A logic circuit configured using a part of the plurality of core transistors;
At least one of the dummy transistors and the core transistor that has not been used as the logic circuit function as an inter-power source capacitive element provided between the power source line and the ground line, respectively. Capacitance element wiring connected to the ground wiring.

  According to this semiconductor device, the dummy transistor and the core transistor that has not been used as the logic circuit function as the inter-power source capacitive element. For this reason, it is not necessary to newly provide a space for arranging the inter-power source capacitive element. Therefore, even if the integration rate of the core transistor is increased, a plurality of inter-power source capacitance elements can be arranged to reduce noise reflected from the core transistor to the outside.

A method for manufacturing a semiconductor device according to the present invention includes:
Forming a plurality of core transistors including dummy transistors not used as transistors, and I / O cells positioned around the plurality of core transistors;
Connecting at least one of the dummy transistors to the power supply wiring and the ground wiring so as to function as an inter-power capacitive element provided between a power supply wiring and a ground wiring of the core transistor,
The dummy transistor is located next to the I / O cell.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Forming a plurality of core CMOS transistors including dummy CMOS transistors not used as transistors, and an I / O cell positioned around the plurality of core CMOS transistors;
Connecting at least one of the dummy CMOS transistors to the power supply wiring and the ground wiring so as to function as an inter-power capacitive element provided between a power supply wiring and a ground wiring of the core CMOS transistor. And
The dummy CMOS transistor is located next to the I / O cell.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Forming a plurality of core transistors;
A wiring for forming a part of the plurality of core transistors to function as a logic circuit and a core transistor not functioning as the logic circuit are connected between power supplies provided between the power supply wiring and the ground wiring. Forming a capacitor element wiring connected to the power supply wiring and the ground wiring so as to function as a capacitor element.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Forming a plurality of core transistors including dummy transistors that are not used as transistors;
A wiring for causing a part of the plurality of core transistors to function as a logic circuit is formed, and at least one of the dummy transistors and a core transistor not functioning as the logic circuit are respectively connected to the power supply wiring and the Forming a capacitor element wiring connected to the power supply wiring and the ground wiring so as to function as an inter-power supply capacitive element provided between the power supply wiring and the ground wiring.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of the semiconductor device according to the first embodiment.
In the semiconductor device according to the present embodiment, a plurality of core transistors (not shown) are densely integrated in the internal region 30 of the chip, and a plurality of I / O cells 10 are disposed around the internal region 30. In addition, a plurality of wiring pads 20 are arranged. A transistor (not shown) larger than the core transistor is formed inside the I / O cell 10.

The gate electrode of the core transistor in the internal region 30 and the gate electrode of the transistor in the I / O cell 10 are formed by simultaneously etching the same film. In general, when a portion having a large pattern and a portion having a fine pattern are etched at the same time, the etching rate of the portion having a fine pattern is lowered due to a loading effect. For this reason, in the dummy region 32 that is adjacent to the I / O cell 10 in the internal region 30, the etching rate when forming the gate electrode is affected when the large gate electrode is formed in the I / O cell 10. As a result, the etching rate is lower than the etching rate except for the dummy region 32. Therefore, in the dummy region 32, the gate electrode is formed in a shape different from the intended shape. Therefore, the transistor formed in the dummy region 32 is generally treated as a dummy transistor and may not be connected to the wiring because the quality as a core transistor may not be guaranteed.
In the present embodiment, the dummy transistor is connected to the wiring so as to function as an inter-power supply capacitive element connected between the power supply wiring and the ground wiring of the core transistor.

Next, the configuration of the inter-power source capacitive element will be described with reference to FIGS. FIG. 2 is an enlarged plan view of a region surrounded by a broken line A in FIG. 3A is a view showing a cross section AA in FIG. 2, and FIG. 3B is a view showing a cross section BB in FIG.
As shown in FIG. 2, in the planar arrangement, a plurality of core transistors 100 are arranged in a matrix in the internal region 30. In addition, a dummy transistor is formed in the dummy region 32. This dummy transistor is connected to the power supply wiring 12 of the core transistor via the capacitor element wiring 42 in order to function as the inter-power supply capacitance element 200. The device wiring 44 is connected to the ground wiring 14. The power supply wiring 12 and the ground wiring 14 are formed in the I / O cell 10 along the edge of the internal region 30.

  Specifically, as shown in the sectional view of FIG. 3A, the core transistor 100 is a P-channel MOS transistor and has the following structure. An N-type well 34 a is formed in the silicon substrate 1. An element isolation film 2 is formed on the surface of the N-type well 34a, and a P-type impurity layer 104a which is a source region and a drain region and a gate electrode 102 are formed in an element region between the element isolation films 2. Is formed. Gate electrode 102 is formed on gate oxide film 102a, and is sandwiched between P-type impurity layers 104a in a planar arrangement. An interlayer insulating film 3 is formed on the element isolation film 2, the gate electrode 102, and the P-type impurity layer 104a. A connection hole (not shown) is formed in the interlayer insulating film 3, and a wiring formed on the interlayer insulating film 3 is connected to the gate electrode 102 and the P-type impurity layer 104a through the connection hole.

  The inter-power source capacitive element 200 has the following structure. An N-type well 34 a is continuously formed on the silicon substrate 1 from below the core transistor 100 to below the inter-power supply capacitance element 200. An element isolation film 2 is formed on the surface of the N-type well 34a, and a P-type impurity layer 204a as a source / drain and a gate electrode 202 are formed in an element region between the element isolation films 2. Yes. Gate electrode 202 is formed on gate oxide film 202a and is sandwiched between P-type impurity layers 204a in a planar arrangement. The gate electrode 202 and the gate oxide film 202a are formed in a shape different from the gate electrode 102 and the gate oxide film 102a of the core transistor 100 due to the loading effect described above. An interlayer insulating film 3 is formed on the element isolation film 2, the gate electrode 102, and the P-type impurity layer 104a. In the interlayer insulating film 3, connection holes 3a and 3b located on the gate electrode 202 and the P-type impurity layer 204a are formed. A part of the capacitor element wiring 44 is embedded in the connection holes 3 a and 3 b to be connected to the gate electrode 202 and the P-type impurity layer 204 a and to the ground wiring 14.

  As shown in the cross-sectional view of FIG. 3B, the element isolation film 2 is provided with an opening 2a, and the N-type well 34a faces the interlayer insulating film 3 in the opening 2a. A connection hole 3c is formed in the interlayer insulating film 3 so as to be located on the opening 2a. The capacitive element wiring 42 is connected to the N-type well 34 a by being partially embedded in the connection hole 3 c and to the power supply wiring 12.

An equivalent circuit diagram of the inter-power source capacitive element 200 is shown in FIG. V _DD is applied from the power supply wiring 12 to the N-type well 34a through the capacitive element wiring 42, and P _SS from the ground wiring 14 to the gate electrode 202 and the source / drain through the capacitive element wiring 44 is a P-type impurity. When applied to the layer 204a, the inter-power source capacitive element 200 accumulates charges at the interface between the P-type impurity layer 204a and the N-type well 34a.

The semiconductor device having such a structure is formed as follows, for example. First, a resist pattern (not shown) is formed on the silicon substrate 1. Using this resist pattern as a mask, the silicon substrate 1 is irradiated with ions to perform ion implantation. Then, after removing the resist pattern, an N-type well 34a is formed by performing heat treatment. Next, an element isolation film 2 that isolates element regions from each other is formed by LOCOS. At this time, an opening 2 a is formed in the element isolation film 2. Next, after gate oxide films 102a and 202a are formed in the element region by a thermal oxidation method, a polysilicon film is deposited on the entire surface including the gate oxide films 102a and 202a by a CVD method. Next, the polysilicon film is etched and patterned to form the gate electrode 102 on the gate oxide film 102a and the gate electrode 202 on the gate oxide film 202a. At this time, due to the loading effect, the etching rate around the gate electrode 102 is different from the etching rate around the gate electrode 202, so that the gate electrode 202 is formed in a different shape from the gate electrode 102.
Next, impurity ions are implanted into the silicon substrate 1 using the gate electrodes 102 and 202 as a mask, and a predetermined heat treatment is performed. As a result, a P-type impurity layer 104a and a P-type impurity layer 204a are formed on the silicon substrate 1.

Further, an interlayer insulating film 3 is deposited by the CVD method. The interlayer insulating film 3 is, for example, a silicon oxide film, a BPSG (boro-phosphosilicate glass) film, an SOG (spin on glass) film, or the like. Next, a resist pattern is formed on the interlayer insulating film 3, and etching is performed using this resist pattern as a mask, so that the connection hole 3a is formed on the gate electrode 202, the connection hole 3b is formed on the P-type impurity layer 204a, A connection hole 3 c is formed on the opening 2 a of the element isolation film 2.
Next, an Al alloy film is deposited in the connection holes 3a, 3b, 3c and on the interlayer insulating film 3 by sputtering. Next, by patterning the Al alloy film, capacitor element wirings 42 and 44 made of an Al alloy film are formed. At this time, part of the wiring of the core transistor 100 may be formed simultaneously with the capacitor element wirings 42 and 44.

As described above, according to the semiconductor device of this embodiment, among the transistors formed in the internal region 30, the dummy transistor adjacent to the I / O cell 10 includes the gate electrode 202 and the P-type impurity layer 204 a having the capacitance element wiring 44. Is connected to the ground wiring 14, and the N-type well 34 a is connected to the power supply wiring 12 by the capacitive element wiring 42, and thus functions as the inter-power supply capacitive element 200. Therefore, it is possible to arrange the inter-power source capacitive element in the chip without securing a new space. Therefore, even if the integration degree of the core transistor 100 in the internal region 30 is increased, a plurality of inter-power source capacitive elements 200 can be arranged to reduce noise reflected from the core transistor 100 to the outside.
Further, since the inter-power source capacitive element 200 can be formed only by changing the patterning when forming the wiring pattern with respect to the conventional manufacturing process, the manufacturing cost does not increase compared with the conventional manufacturing process.

  FIG. 5 is an enlarged plan view of the semiconductor device according to the second embodiment, and corresponds to FIG. 2 in the first embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the semiconductor device according to the present embodiment, core transistors 110 that are N-channel MOS transistors are arranged in a matrix in the internal region 30. The core transistor 110 includes a gate electrode 102 and an N-type impurity layer 104b which is a source / drain region. The dummy transistor formed in the dummy region 32 includes a gate electrode 202 and two N-type impurity layers 204b which are source / drain regions. The P-type well 34b is continuously formed from the bottom of the core transistor 110 to the bottom of the dummy transistor. The dummy transistor is connected to the power supply wiring 12 and the ground wiring 14 by capacitive element wirings 46 and 48 so as to function as the inter-power supply capacitive element 201.

  Specifically, the capacitor element wiring 46 connects the P-type well 34 b to the ground wiring 14, and the capacitor element wiring 48 connects the gate electrode 202 and the two N-type impurity layers 204 b to the power supply wiring 12. The semiconductor device having such a structure can be formed by the same method as in the first embodiment by changing the etching pattern of the Al alloy film on the interlayer insulating film 3.

FIG. 6 shows an equivalent circuit diagram of the inter-power source capacitive element 210. Is applied to the gate electrode 202 and the N-type impurity layer 204b _{V DD} from the power supply line 12 through the capacitor wires 48, is applied to the P-type well 34b via the _{V SS} capacitive element wiring 46 from the ground wiring 14 Then, the inter-power supply capacitive element 201 accumulates electric charges at the interface between the N-type impurity layer 204b and the P-type well 34b.
According to this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 7 is an enlarged plan view of the semiconductor device according to the third embodiment, and corresponds to FIG. 2 in the first embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
In the semiconductor device according to the present embodiment, core transistors 100 that are P-channel MOS transistors are arranged in a matrix in the internal region 30. In the dummy transistor formed in the dummy region 32, the gate electrode 202 is connected to the ground wiring 14 by the capacitive element wiring 52 in order to function as the inter-power source capacitive element 210, and the two P-type impurity layers 204a are provided. The capacitor element wiring 54 is connected to the power supply wiring 12. The N-type well 34a (not shown) is connected to the power supply wiring 12 by a wiring (not shown).

  8A is a cross-sectional view showing the AA cross section of FIG. 7, and FIG. 8B is a cross-sectional view showing the BB cross section of FIG. As shown in FIG. 8A, the gate electrode 202 extends to the element isolation film 2. The interlayer insulating film 3 is formed with a connection hole 3a located on the extended portion. The capacitor element wiring 52 is connected to the gate electrode 202 by being partially embedded in the connection hole 3a. Further, as shown in FIG. 8B, the capacitor element wiring 54 is connected to the P-type impurity layer 204 a by being partially embedded in the connection hole 3 b formed in the interlayer insulating film 3.

FIG. 9 shows an equivalent circuit diagram of the inter-power source capacitive element 210. V _DD is applied from the power supply wiring 12 to the N-type well 34a through a wiring (not shown), and is applied to the P-type impurity layer 204a as the source / drain through the capacitive element wiring 54, and from the ground wiring 14 to _VSS. Is applied to the gate electrode 202 through the capacitive element wiring 52, the inter-power source capacitive element 200 accumulates charges at the interface between the gate insulating film 202a and the N-type well 34a.

In the semiconductor device having such a structure, the position where the connection holes 3a and 3b are formed is changed, the connection hole 3c is not formed, and the etching pattern of the Al alloy film on the interlayer insulating film 3 is changed. It can be manufactured by the same method as in the first embodiment.
Also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 10 is an enlarged plan view of the semiconductor device according to the fourth embodiment, and corresponds to FIG. 5 in the second embodiment. In the present embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.
In the semiconductor device according to the present embodiment, core transistors 110 that are N-channel MOS transistors are arranged in a matrix in the internal region 30. In the dummy transistor formed in the dummy region 32, the gate electrode 202 is connected to the power supply wiring 12 by the capacitive element wiring 56 to function as the inter-power supply capacitive element 211, and both the N-type impurity layers 204 b are provided. The capacitor element wiring 58 is connected to the ground wiring 14. The P-type well 34b (not shown) is connected to the ground wiring through a wiring (not shown).

FIG. 11 is an equivalent circuit diagram of the inter-power source capacitive element 211. Is applied to the gate electrode 202 V _DD from the power supply line 12 through the capacitor wiring 56, via a capacitor wiring 58 while being applied to the P-type well through a wire V _SS is not shown from the ground wiring 14 When applied to the source / drain N-type impurity layer 204b, the inter-power source capacitive element 200 accumulates electric charges at the interface between the gate insulating film 202a and the P-type well 34b.
The semiconductor device according to the present embodiment described above can achieve the same effects as those of the first embodiment.

  FIG. 12 is an enlarged plan view of the semiconductor device according to the fifth embodiment, and corresponds to FIG. 2 in the first embodiment. In this embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted. In the semiconductor device according to the present embodiment, the core transistor is composed of a CMOS transistor.

That is, in the internal region 30, a region where the core transistor 100, which is a P-channel transistor, and a region where the core transistor 110, which is an N-channel transistor, are alternately formed in a band shape in the vertical direction in the drawing. In the dummy region 32, the inter-power capacitive element 200 formed using the N-channel transistor dummy transistor and the inter-power capacitive element 201 formed using the P-channel transistor dummy transistor are alternately arranged. Has been. The connection relationship between the inter-power capacitive element 200 and the power supply wiring 12 and the ground wiring 14 is the same as in the first embodiment, and the connection relationship between the inter-power capacitive element 201 and the power supply wiring 12 and the ground wiring 14 is the same as that in the second embodiment. The same.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 13 is an enlarged plan view of a semiconductor device according to the sixth embodiment, which corresponds to FIG. 7 in the third embodiment. In the present embodiment, the same components as those in the third and fourth embodiments are denoted by the same reference numerals, and description thereof is omitted. In the semiconductor device according to the present embodiment, the core transistor is composed of a CMOS transistor.

That is, in the internal region 30, a region where the core transistor 100, which is a P-channel transistor, and a region where the core transistor 110, which is an N-channel transistor, are alternately formed in a band shape in the vertical direction in the drawing. In the dummy region 32, the inter-power capacitive element 210 formed using the N-channel transistor dummy transistor and the inter-power capacitive element 211 formed using the P-channel transistor dummy transistor are alternately arranged. Has been. The connection relationship between the inter-power capacitive element 210 and the power supply wiring 12 and the ground wiring 14 is the same as in the third embodiment, and the connection relationship between the inter-power capacitive element 211 and the power supply wiring 12 and the ground wiring 14 is the same as that in the fourth embodiment. The same.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 14 is an enlarged plan view of the semiconductor device according to the seventh embodiment, which corresponds to FIG. 13 in the sixth embodiment. FIG. 15 is a view showing a cross section taken along line AA of FIG. In the present embodiment, the same components as those in the sixth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 13, in the semiconductor device according to the present embodiment, core transistors 120 that are P-channel MOS transistors and core transistors 130 that are N-channel MOS transistors are alternately arranged in a matrix in the internal region 30. Yes. In the dummy region 32, inter-power capacitive elements 230 and 240 are formed using the dummy transistors of the core transistors 120 and 130, respectively.

  As shown in FIGS. 13 and 14, the core transistor 120 has a P-type impurity layer 122 formed on each of both ends in a planar arrangement. Gate electrodes 121 are formed adjacent to each other inside each P-type impurity layer 122, and these gate electrodes 121 are spaced apart from each other and arranged substantially in parallel. A P-type impurity layer 123 is formed between the two gate electrodes 121. In the planar arrangement of the core transistor 130, N-type impurity layers 132 are formed at both ends. Gate electrodes 131 are formed adjacent to each other inside each of the N-type impurity layers 132, and these gate electrodes 131 are spaced apart from each other and arranged substantially in parallel. An N-type impurity layer 133 is formed between the two gate electrodes 131.

  The inter-power capacitive element 230 includes a gate electrode 232 and two P-type impurity layers 234, and the inter-power capacitive element 240 includes a gate electrode 242 and two N-type impurity layers 244. The gate electrode 232 of the inter-power source capacitive element 230 has a shape in which the two gate electrodes 121 in the core transistor 120 are connected to each other, and is formed in a region covering the two gate electrodes and the gap therebetween. Therefore, the area of the gate electrode 232 is larger than the sum of the areas of the two gate electrodes 121. The gate electrode 232 is connected to the ground wiring 14 by the capacitive element wiring 62, and each of the two P-type impurity layers 234 is connected to the power supply wiring 12 by the capacitive element wiring 64.

  Further, the gate electrode 242 of the inter-power source capacitive element 240 has the same shape as the gate electrode 232, and its area is larger than the sum of the areas of the two gate electrodes 131. The gate electrode 242 is connected to the power supply wiring 12 by the capacitor element wiring 66, and each of the two N-type impurity layers 244 is connected to the ground wiring 14 by the capacitor element wiring 68.

  Further, the N-type well of the core transistor 120 is continuously formed up to the bottom of the inter-power capacitive element 230 and is connected to the power supply wiring 12 through a wiring (not shown). The P-type well of the core transistor 130 is also continuously formed below the inter-power source capacitive element 240, and is connected to the ground wiring 14 via a wiring (not shown).

The inter-power capacitive elements 230 and 240 store electric charges by the same operation as the inter-power capacitive element 210 according to the third embodiment and the inter-power capacitive element 211 according to the fourth embodiment, respectively.
According to this embodiment, the same effect as that of the sixth embodiment can be obtained. Further, since the areas of the gate electrodes 232 and 242 of the inter-power capacitive elements 230 and 240 are increased, the capacitance per inter-power capacitive element is increased. Therefore, it is possible to increase the capacity between the power supplies and further reduce noise reflected from the core transistor 100 to the outside.

FIG. 16 is an enlarged plan view of the semiconductor device according to the eighth embodiment, and corresponds to FIG. 2 in the first embodiment. In this embodiment, the same components as those in the first or second embodiment are denoted by the same reference numerals, and description thereof is omitted.
In the semiconductor device according to the present embodiment, the core transistors 100 and 110 that are CMOS transistors are formed in the internal region 30 in advance, and then a wiring pattern (not shown) that connects the core transistors 100 and 110 is designed and formed. A logic circuit is formed. For this reason, a plurality of types of semiconductor devices having different logics can be manufactured only by changing the wiring pattern that connects the core transistors 100 and 110 to each other. Here, some core transistors 100 and 110 may be unnecessary in logic design.

The N-type well 34a of the core transistor 100 is connected to the power supply wiring 12 by the capacitor element wiring 42 as in the first embodiment. In the core transistor 100 that is not required in logic design, the gate electrode 102 and the two P-type impurity layers 104a are connected to the ground wiring 14 by the capacitive element wiring 44 in order to function as the inter-power supply capacitive element 200. Further, the P-type well 34b of the core transistor 110 is connected to the ground wiring 14 by the capacitive element wiring 46 as in the second embodiment. In the core transistor 110 that is not necessary in logic design, the gate electrode 102 and the two N-type impurity layers 104 b are connected to the power supply wiring 12 by the capacitor element wiring 48 in order to function as the inter-power supply capacitive element 201.
The capacitor element wiring 44 is also connected to the gate electrode 202 and the P-type impurity layer 204a in order for the dummy transistor formed in the dummy region 32 to function as the inter-power source capacitor element 200. Are connected to the gate electrode 202 and the N-type impurity layer 204b in order to cause the dummy transistor formed in the dummy region 32 to function as the inter-power source capacitive element 201.

The capacitor element wirings 42, 44, 46, and 48 are formed simultaneously with a wiring pattern for forming a logic circuit, for example, as follows. An insulating film (not shown) corresponding to the interlayer insulating film 3 in the first embodiment is formed on the entire surface including the gate electrode 102, the P-type impurity layer 104a, and the N-type impurity layer 104b in advance. Yes. First, a resist pattern is formed on the insulating film, and the insulating film is etched using the resist pattern as a mask, so that each of the gate electrode 102 of the core transistors 100 and 110, the P-type impurity layer 104a, and the N-type impurity layer 104b. At the same time, the connection holes located on the gate electrode 202, the P-type impurity layer 204a, and the N-type impurity layer 204b of the inter-power source capacitive elements 200 and 201 are formed.
Next, an Al alloy film is formed in these connection holes and on the insulating film, for example, by sputtering. Next, a resist pattern is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. Thereby, a wiring (not shown) connected to the gate electrode 102 of the core transistor 100, a wiring (not shown) connected to the P-type impurity layer 104a, and a wiring (not shown) connected to the gate electrode 102 of the core transistor 110. ) And the wiring (not shown) connected to the N-type impurity layer 104b can be formed at the same time as the capacitor element wirings 42, 44, 46, and 48.

  According to the present embodiment, the same effect as that of the first embodiment can be obtained. In addition, since the core transistors 100 and 110 that are not used as logic circuits are used as the inter-power capacitive elements 200 and 201, the inter-power capacity can be further increased without providing a space for arranging the inter-power capacitive elements. Can be increased. Therefore, noise reflected from the core transistor 100 to the outside can be further reduced.

  FIG. 17 is an enlarged plan view of the semiconductor device according to the ninth embodiment, which corresponds to FIG. 16 in the eighth embodiment. In this embodiment, the same components as those of the third, fourth, or eighth embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the present embodiment, unlike the eighth embodiment, the core transistors 100 and 110 that are unnecessary in the logical configuration are caused to function as the inter-power source capacitive elements 210 and 211. Specifically, the gate electrode 102 of the core transistor 100 is connected to the ground wiring 14 by the capacitor element wiring 72, and the two P-type impurity layers 104 a are connected to the power supply wiring 12 by the capacitor element wiring 74. Further, the gate electrode 102 of the core transistor 110 is connected to the power supply wiring 12 by the capacitor element wiring 76, and the two N-type impurity layers 104 b are connected to the ground wiring 14 by the capacitor element wiring 78.
The capacitor element wirings 72 and 74 are also connected to the gate electrode 202 and the P-type impurity layer 204a, respectively, so that the dummy transistor formed in the dummy region 32 functions as the inter-power source capacitor element 210. Further, the capacitor element wirings 76 and 78 are also connected to the gate electrode 202 and the N-type impurity layer 204b, respectively, so that the dummy transistor formed in the dummy region 32 functions as the inter-power source capacitor element 211.
In this embodiment, the same effect as that in the eighth embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

The top view of the semiconductor device concerning a 1st embodiment The top view which expanded the area | region enclosed with the broken line A in FIG. (A) is sectional drawing which shows the AA cross section of FIG. 2, (b) is sectional drawing which shows the BB cross section of FIG. 1 is an equivalent circuit diagram of a capacitor between power supplies according to the first embodiment. The plane enlarged view of the semiconductor device concerning a 2nd embodiment Equivalent circuit diagram of the inter-power source capacitive element according to the second embodiment The plane enlarged view of the semiconductor device concerning 3rd Embodiment (A) is sectional drawing which shows the AA cross section of FIG. 7, (b) is sectional drawing which shows the BB cross section of FIG. Equivalent circuit diagram of the capacitive element between the power supplies according to the third embodiment The plane enlarged view of the semiconductor device concerning a 4th embodiment Equivalent circuit diagram of capacitive element between power supplies according to the fourth embodiment The plane enlarged view of the semiconductor device concerning a 5th embodiment The plane enlarged view of the semiconductor device concerning a 6th embodiment The plane enlarged view of the semiconductor device concerning a 7th embodiment Sectional drawing which shows the AA cross section of FIG. The plane enlarged view of the semiconductor device concerning 8th Embodiment The plane enlarged view of the semiconductor device concerning 9th Embodiment Plan view of a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3 ... Interlayer insulation film, 3a, 3b, 3c ... Connection hole 10, 310 ... I / O cell, 12 ... Power supply wiring, 14 ... Ground wiring, 20, 320 ... Wiring Pad, 30, 330 ... inner region, 32 ... dummy region, 34a ... N-type well, 34b ... P-type well, 42, 44, 46, 48, 52, 54, 56, 58, 62, 64, 66, 68, 72, 74, 76, 78 ... capacitance element wiring, 100, 110, 120, 130 ... core transistor, 102, 121, 131, 202, 232, 242 ... gate electrode, 104a, 122, 123, 204a, 234 ... P Type impurity layer, 104b, 132, 133, 204b, 244... N type impurity layer, 200, 201, 210, 211, 230, 240.

Claims (16)

A plurality of core transistors including dummy transistors that are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
Capacitor element wiring connected to the power supply wiring and the ground wiring so that at least one of the dummy transistors functions as a power supply capacitive element provided between the power supply wiring and the ground wiring. ,
The dummy transistor is a semiconductor device arranged next to the plurality of I / O cells. The dummy transistor is disposed over the entire periphery of the peripheral portion of the plurality of core transistors,
The semiconductor device according to claim 1, wherein the capacitor element wiring causes each of the plurality of dummy transistors to function as the inter-power source capacitor element. The dummy transistor is a P-channel MOS transistor,
The semiconductor device according to claim 1, wherein the capacitor element wiring has a gate electrode, a source region, and a drain region connected to the ground wiring and a well connected to the power supply wiring. The dummy transistor is an N-channel MOS transistor,
The semiconductor device according to claim 1, wherein the capacitor element wiring has a gate electrode, a source region, and a drain region connected to the power supply wiring and a well connected to the ground wiring. The dummy transistor is a P-channel MOS transistor,
The semiconductor device according to claim 1, wherein the capacitor element wiring has a gate electrode connected to the ground wiring and a source region and a drain region connected to the power supply wiring. The dummy transistor is an N-channel MOS transistor,
The semiconductor device according to claim 1, wherein the capacitor element wiring has a gate electrode connected to the power supply wiring and a source region and a drain region connected to the ground wiring.   7. The semiconductor according to claim 5, wherein at least two adjacent gate electrodes and two gate insulating films are connected to each other in the dummy transistor, and the area of the gate electrode and the gate insulating film is larger than that of the other core transistors. apparatus. A plurality of core CMOS transistors including dummy CMOS transistors which are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core CMOS transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core CMOS transistors;
A capacitor element wiring connected to the power supply wiring and the ground wiring so that at least one of the dummy CMOS transistors functions as an inter-power supply capacitive element provided between the power supply wiring and the ground wiring; And
The dummy CMOS transistor is a semiconductor device arranged next to the plurality of I / O cells. The dummy CMOS transistor includes a P-channel MOS transistor formed in an N-type well and an N-channel MOS transistor formed in a P-type well.
The capacitor element wiring connects the gate electrode, the source region and the drain region of the P-channel MOS transistor to the ground wiring and connects the N-type well to the power supply wiring, and the gate electrode of the N-channel MOS transistor. 9. The semiconductor device according to claim 8, wherein each of the source region and the drain region is connected to the power supply wiring, and the P-type well is connected to the ground wiring. The dummy CMOS transistor includes a P-channel MOS transistor formed in an N-type well and an N-channel MOS transistor formed in a P-type well.
The capacitor element wiring connects the gate electrode of the P-channel MOS transistor to the ground wiring, connects the source region and the drain region to the power supply wiring, and connects the gate electrode of the N-channel MOS transistor to the power supply wiring. The semiconductor device according to claim 8, wherein a source region and a drain region are connected to the ground wiring. A plurality of core transistors arranged in the chip;
A voltage power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
A logic circuit configured using a part of the plurality of core transistors;
Capacitor element wiring connected to the power supply wiring and the ground wiring so that the core transistor that has not been used as the logic circuit functions as an inter-power supply capacitance element provided between the power supply wiring and the ground wiring. A semiconductor device comprising: A plurality of core transistors including dummy transistors that are arranged inside the chip and are not used as transistors;
A plurality of I / O cells arranged to surround the plurality of core transistors;
A power supply wiring and a ground wiring for supplying a voltage to the plurality of core transistors;
A logic circuit configured using a part of the plurality of core transistors;
At least one of the dummy transistors and the core transistor that has not been used as the logic circuit function as an inter-power source capacitive element provided between the power source line and the ground line, respectively. A semiconductor device comprising: capacitor element wiring connected to the ground wiring. Forming a plurality of core transistors including dummy transistors not used as transistors, and I / O cells positioned around the plurality of core transistors;
Connecting at least one of the dummy transistors to the power supply wiring and the ground wiring so as to function as an inter-power capacitive element provided between a power supply wiring and a ground wiring of the core transistor,
The method for manufacturing a semiconductor device, wherein the dummy transistor is located next to the I / O cell. Forming a plurality of core CMOS transistors including dummy CMOS transistors not used as transistors, and an I / O cell positioned around the plurality of core CMOS transistors;
Connecting at least one of the dummy CMOS transistors to the power supply wiring and the ground wiring so as to function as an inter-power capacitive element provided between a power supply wiring and a ground wiring of the core CMOS transistor. And
The method of manufacturing a semiconductor device, wherein the dummy CMOS transistor is located next to the I / O cell. Forming a plurality of core transistors;
A wiring for forming a part of the plurality of core transistors to function as a logic circuit and a core transistor not functioning as the logic circuit are connected between power supplies provided between the power supply wiring and the ground wiring. Forming a capacitor element wiring connected to the power supply wiring and the ground wiring so as to function as a capacitor element. Forming a plurality of core transistors including dummy transistors that are not used as transistors;
A wiring for causing a part of the plurality of core transistors to function as a logic circuit is formed, and at least one of the dummy transistors and a core transistor not functioning as the logic circuit are respectively connected to the power supply wiring and the Forming a capacitor element wiring connected to the power supply wiring and the ground wiring so as to function as an inter-power supply capacitance element provided between the ground wiring and the semiconductor device.

Images