JP2005173860A - Data storage device, method for processing stored data, and computer program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and method for realizing ECC load data writing and reading with respect to a memory by reducing a load of a booster circuit.
An error correction code and a ratio of bit values [0] or [1] occupying all constituent bits of error correction code generation unit data are calculated, and a data pattern with low power consumption in data storage processing is an error correction code. In addition, when it is determined that the data is the inverted data of the error correction code generation unit data, the bit value inversion process is executed and written to the memory. At the time of data reading, it is determined based on the additional bit data whether or not the data written to the memory is inverted data. If the data is inverted, re-inversion processing is executed to restore the original data. Output.
[Selection] Figure 9

Description

  The present invention relates to a data storage device, a stored data processing method, and a computer program. More specifically, in a configuration for performing data writing processing with an error correction code added to a semiconductor memory, a data storage device capable of reducing the number of bias voltage application requests and reducing the load on the booster circuit, and The present invention relates to a stored data processing method and a computer program.

  An EEPROM (Electrically Erasable and Programmable Read Only Memory) is known as a non-volatile memory as a data storage rewritable semiconductor memory element. The EEPROM is used as a memory mounted on, for example, a portable device or an IC card used for security purposes.

  For example, a portable device or IC card having a function of executing encryption processing, authentication processing, etc. is controlled by a cryptographic engine or CPU for performing encryption / decryption in order to exchange data with the host device safely. An encryption / decryption program is installed. Furthermore, in order to store key data for encrypting / decrypting data, ID information, and other important data, a data rewritable nonvolatile memory is mounted. In many cases, an EEPROM is used as the nonvolatile memory. used.

  As an EEPROM, a FLOTOX (Floating Gate with Tunnel Oxide) configuration having a floating gate is known, and a configuration in which an EEPROM is realized by the same processing as a NAND flash suitable for miniaturization is known. Such an EEPROM configuration is described in Patent Document 1, for example.

  In an EEPROM, for example, a high electric field is applied between the floating gate and drain diffusion layer of a memory transistor constituting a semiconductor memory element, and charges (electrons) are released from the floating gate by FN (Fowler-Nordheim) tunneling phenomenon. There is a configuration in which data is written.

  An EEPROM having a structure in which charges (electrons) are injected / released from a floating gate by FN (Fowler-Nordheim) tunneling phenomenon is erased / written by using FN (Fowler-Nordheim) tunnel phenomenon. Sometimes it is necessary to apply a high voltage to the gate or drain.

A structural example of a FLOTOX type EEPROM is shown in FIG. The EEPROM shown in FIG. 1 has a charge accumulation state of the floating gate 102 by applying appropriate biases, that is, V _S , V _D , V _CG , V _SG to the source 106, the drain 107, the control gate 101, and the select gate 103. Change data to rewrite data.

In the FLOTOX type EEPROM shown in FIG. 1, a tunnel oxide film 104 is disposed between an n + drain 105 and a floating gate (FG) 102, and an electric field is generated in the tunnel oxide film 103 to cause an n ⁺ diffusion layer 105 and a floating gate. Data is rewritten by moving electrons between (FG) 102 and changing the charge accumulation state of floating gate 102. The current flowing through the tunnel oxide film 104 is an FN tunnel current generated by an FN (Fowler-Nordheim) tunnel phenomenon.

For example,
(A) An erase state [data “1”] in a state where electrons are injected into the floating gate (FG) 102 (the threshold value of the memory transistor (Memory Tr) is positive)
(B) Write state [data “0”] in a state where electrons are excessively extracted from the floating gate (FG) 102 (the threshold value of the memory transistor (Memory Tr) is negative).
FIG. 2 shows a bias condition at the time of data writing when defined as
FIG. 3 shows bias conditions in the data writing, erasing, and reading processes, and the respective processes.

As shown in FIG. 2, when data is written, 0 V is applied to the word line (V _CG ) of the selected page, 0 V is applied to the bit line (V _D ) of the cell in which data “1” is written, and data “0”. For example, 18 V is applied to the bit line (V _D ) of the cell in which the data is written.

  When performing the data rewriting process, the area to be rewritten is once erased (data is set to “1”), and then writing is performed by applying a bias to each bit line according to the write data.

  When the write data is “1”, since the gate 101 and the drains 105 and 107 are at the same potential, no electric field is generated in the tunnel oxide film 104 and the charge of the floating gate (FG) 102 is erased (data “1”). ") Is retained. On the other hand, when the write data is “0”, a high electric field is generated between the drain 105 and the gate 101, and electrons are extracted from the floating gate (FG) 102 to the drain 105 by this electrolysis. The threshold value of the floating gate (FG) 102 after the data “0” is written becomes negative.

  In the case of a memory for card use such as a smart card (Smart Card), the data writing unit has many specifications that support multi-byte parallel writing such as 1 to 64 bytes or 1 to 128 bytes, for example. Then, the booster circuit that charges the bit lines to the write potential at the time of data writing has the highest potential, that is, even when the write data of all the cells is “0”, For example, it is required to have the ability to charge to 18V).

  However, power supply voltages supplied to portable devices and IC cards equipped with an EEPROM tend to be as low as 2.5V or 1.8V. In particular, non-contact type IC cards are also used in which the IC is operated by rectifying and constant-voltage power generated based on electromagnetic waves received by an antenna mounted on the IC card. In a device having such a configuration, the current value that can be used is limited, and in order to generate a boosted voltage from these power supplies, a problem arises that the circuit scale of the booster circuit must be increased.

  Furthermore, in many cases, an EEPROM mounted on a device for security use is equipped with an ECC (Error Correct Code) circuit as an error correction code in order to increase data reliability, and a cell for storing the ECC data is also added to the EEPROM. Therefore, the bit line corresponding to the ECC data storage cell is also subject to load. As a result, it is necessary to further increase the scale of the booster circuit.

  In addition, devices that perform data write timing control and write processing are required to perform writing according to the control timing, and many bit lines can be charged within a specified time in time for the control timing. Necessary. As a result, a high booster circuit capability is required, and there is a problem that the booster circuit is required to be increased in size and performance, contrary to the reduction in device size.

  FIG. 4 shows a memory device configuration example equipped with an ECC circuit as an error correction code. FIG. 4 shows a FLOTOX type EEPROM configuration. The data storage area 201 stores data and ECC as an error correction code. The ECC code is calculated in a predetermined ECC calculation unit, for example, a 16-bit data unit, and a 5-bit ECC bit (for example, a Hamming Code) is set and stored for the 16-bit data.

  At the time of data writing, write data is input from the data bus 202 based on the control of the data write control signal (XRD) 203, the write data is stored in the data storage area 201 via the memory bus 211, and Data is input to the ECC circuit 205 via 211, ECC bits based on the write data are calculated, and the generated ECC bits are stored in the data storage area 201 via the ECC bus 212.

  At the time of reading data, data and ECC bits are read from the data storage area 201 based on the control of the data read control signal (XRD) 204, and the ECC bits are converted into ECC bits by the ECC circuit 205 via the memory bus 211 and the ECC bus 212. After the error correction process is executed, the corrected data is output to the data bus 202. Error correction in the ECC circuit 205 is executed based on, for example, syndrome calculation processing.

  A generation example of write data when the ECC calculation unit is 16-bit data and a Hamming Code is used as the ECC will be described with reference to FIG.

As shown in FIG. 5, the write data _is 16-bit data X 0 _{to X 15,} with respect to the 16-bit data _X 0 _{to X 15,} ECC bits _C 0 -C ₄ shown in FIG. 5 is generated The The exclusive OR (XOR) operation of the bits marked with ○ shown in FIG. 5A is executed based on the calculation formula shown in FIG. 5B, and a Hamming code C ₀ as an ECC bit is executed. ~C ₄ is calculated.

As a result, it is necessary to write 16-bit data of X _{0 to} X ₁₅ and 5-bit data of ECC bits C _{0 to} C _{4 in} the data storage area.

When data is written to the FLOTOX type EEPROM described above, 0V is applied to the bit line (V _D ) of the cell to which data “1” is written, and 18 V is applied to the bit line (V _D ) of the cell to which the data “0” is written. It is necessary to apply. The number of 0s included in the total of 21 bits, that is, 16 bits data of X _{0 to} X ₁₅ and 5 bits of ECC bits C _{0 to} C ₄ is 21 / 2≈11 as a stochastic average, In half of the write processes executed in the device, zero write of 11 to 21 occurs, and the burden on the booster circuit becomes excessive. Since it is necessary to design a booster circuit that has the ability to satisfy the specifications regardless of the write data, it is necessary to have the ability to satisfy the specifications when the write voltage is applied to all the bit lines. Will become bigger.

An error correction code such as ECC is indispensable for a device that stores data that is not allowed to generate an error, such as an encryption processing key and ID data. As a result, in order to perform an accurate data write process, the capability of the booster circuit An excellent one is required, and the problem that the scale of the booster circuit has to be increased has become conspicuous against the downsizing of devices such as portable devices and IC cards.
JP 2000-149581 A

  The present invention has been made in view of the above problems, and reduces the number of bit lines to be charged at the time of data processing in a configuration that requires data writing processing to which an error correction code is added in an EEPROM as a semiconductor memory device. Data storage device, stored data processing method, and computer capable of reducing the load on the booster circuit, reducing current consumption in the booster circuit, and reducing the circuit scale of the booster circuit・ The purpose is to provide a program.

  Furthermore, the present invention makes it possible to reduce the bit line charging time and consequently the data writing time in a configuration that requires data writing processing with an error correction code added to an EEPROM as a semiconductor memory device. Another object of the present invention is to provide a data storage device, a stored data processing method, and a computer program that enable accurate data reading in data reading.

The first aspect of the present invention is:
A data storage device,
A data storage area;
Error correction code processing means for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the storage target data stored in the data storage area has a predetermined data length;
The ratio of the error correction code generated by the error correction code processing means and the bit value [0] or [1] in all the constituent bits of the error correction code generation unit data is calculated, and the data with low power consumption in the data storage processing Bit value determination means for determining whether a pattern is the error correction code and inverted data of the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result of the bit value determination means Write data inversion control means for executing
The data storage device is characterized by comprising:

  Furthermore, in one embodiment of the data storage device of the present invention, the additional data is 1-bit data set for the unit length data, and is data having a predetermined bit value. To do.

  Furthermore, in one embodiment of the data storage device of the present invention, the error correction code is a Hamming code that can specify an error occurrence bit position.

  Furthermore, in an embodiment of the data storage device of the present invention, the error correction code processing means performs error correction processing of read data from the data storage area, and whether or not the read data is inverted data of original data. The data storage device further performs inversion of the read data when the error correction code processing means determines that the read data is inverted data of the original data. Read data inversion control means for executing processing.

  Furthermore, in an embodiment of the data storage device of the present invention, the error correction code processing means executes a syndrome calculation process for read data from the data storage area, and executes an error correction process based on the calculated syndrome. It is the structure.

  Furthermore, in one embodiment of the data storage device of the present invention, the error correction code processing means determines whether the read data is inverted data of the original data based on the bit value of the additional data included in the read data. It is the structure which performs such a determination process, It is characterized by the above-mentioned.

  Furthermore, in one embodiment of the data storage device of the present invention, the data storage area has a FLOTOX (Floating Gate with Tunnel Oxide) configuration having a floating gate.

  Furthermore, in an embodiment of the data storage device of the present invention, the data storage area is configured to apply a bias voltage to a storage cell having a bit value of 0, and the bit value determination means includes the error correction unit. The error correction code generated by the code processing means and the ratio of the bit value [0] occupying all the constituent bits of the error correction code generation unit data are calculated, and the data pattern having a small ratio of the bit value [0] is the error correction code. And a process for determining whether the data is inverted data of the error correction code generation unit data, and the write data inversion control means has a data pattern with a small percentage of bit value [0] as the error data. In the configuration that executes the reversal processing when the correction code and the error correction code generation unit data are inverted data And wherein the Rukoto.

Furthermore, the second aspect of the present invention provides
Stored data processing method,
An error correction code generation processing step for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the data to be stored is a predetermined data length stored in the data storage area;
The error correction code generated in the error correction code generation processing step and the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code generation unit data are calculated to reduce power consumption in the data storage process. A bit value determination step for determining whether a data pattern is inverted data of the error correction code and the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result in the bit value determination step A write data inversion control step for executing
A stored data processing method characterized by comprising:

  Furthermore, in one embodiment of the stored data processing method of the present invention, the additional data is 1-bit data set for the unit length data and is data having a predetermined bit value. And

  Furthermore, in an embodiment of the stored data processing method of the present invention, the error correction code is a Hamming code that can specify an error occurrence bit position.

  Furthermore, in an embodiment of the storage data processing method of the present invention, the storage data processing method further includes an error correction step of executing an error correction process of read data from the data storage area, and the read data is original data. A read data determination step for executing a determination process for determining whether the read data is inverted data, and a read data inversion for executing a read data inversion process when the read data is determined to be inverted data of the original data And a control step.

  Furthermore, in one embodiment of the stored data processing method of the present invention, the error correcting step includes a step of executing a syndrome calculating process for read data from the data storage area and executing an error correcting process based on the calculated syndrome It is characterized by being.

  Furthermore, in one embodiment of the stored data processing method of the present invention, the read data determination step determines whether the read data is inverted data of the original data based on a bit value of additional data included in the read data. It is the step which performs the determination process.

  Furthermore, in one embodiment of the stored data processing method of the present invention, the data storage area has a FLOTOX (Floating Gate with Tunnel Oxide) configuration having a floating gate, and a bias voltage is applied to a storage cell having a bit value of 0. The bit value determining step calculates a ratio of the bit value [0] occupying all the constituent bits of the error correction code and the error correction code generation unit data, and the bit value [0] A process of determining whether or not a data pattern with a small ratio is the inverted data of the error correction code and the error correction code generation unit data is executed, and the write data inversion control step has a ratio of the bit value [0]. A small data pattern includes the error correction code and the inverted data of the error correction code generation unit data. And executes the inversion process if it is.

Furthermore, the third aspect of the present invention provides
A computer program for executing data storage processing for memory,
An error correction code generation processing step for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the data to be stored is a predetermined data length stored in the data storage area;
The error correction code generated in the error correction code generation processing step and the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code generation unit data are calculated to reduce power consumption in the data storage process. A bit value determination step for determining whether a data pattern is inverted data of the error correction code and the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result in the bit value determination step A write data inversion control step for executing
There is a computer program characterized by comprising:

  The computer program of the present invention is, for example, a storage medium or communication medium provided in a computer-readable format to a computer system capable of executing various program codes, such as a CD, FD, or MO. It is a computer program that can be provided by a recording medium or a communication medium such as a network. By providing such a program in a computer-readable format, processing corresponding to the program is realized on the computer system.

  Other objects, features, and advantages of the present invention will become apparent from a more detailed description based on embodiments of the present invention described later and the accompanying drawings. In this specification, the system is a logical set configuration of a plurality of devices, and is not limited to one in which the devices of each configuration are in the same casing.

  According to the configuration of the present invention, the ratio of the bit value [0] or [1] occupying all the constituent bits of the error correction code and the error correction code generation unit data is calculated, and a data pattern with low power consumption in the data storage processing is obtained. Determining whether or not the error correction code and the error correction code generation unit data are inverted data, and when the data pattern with low power consumption is the inverted data, the bit value inversion processing is executed and written to the memory Therefore, the number of bit lines that need to be charged based on the boosted voltage can be halved, the booster circuit and current consumption can be reduced, and high-speed data writing processing can be performed.

  Further, according to the configuration of the present invention, when reading data, it is determined based on the additional bit data whether the write data to the memory is inverted data. Since the reversal process is executed and the data is returned to the original data and output, normal data can be read out.

  Details of the data storage device, the stored data processing method, and the computer program of the present invention will be described below.

  The configuration of the data storage device according to the present invention will be described with reference to FIG. The data storage device according to the present invention sets an ECC as an error correction code for write data to a memory and executes an error correction process based on the ECC for read data from the memory. It is equipped with.

  In the device configuration of FIG. 6, the data storage area 301 has a FLOTOX type EEPROM configuration. The data storage area 301 stores data and ECC as an error correction code. The ECC code is calculated for a predetermined ECC calculation unit.

  In the configuration of the present invention, for example, 1-bit additional data is additionally set for 16-bit actual data, and a total of 17-bit data is set as error correction code generation unit data. Data, for example, a Hamming Code is given. Details of the ECC data generation processing will be described later.

  At the time of data writing, write data is input to the ECC block 350 from the data bus 302, setting of additional data for the write data and calculation and addition of ECC data are executed in the ECC block 350, and then data is stored via the memory bus 311. Actual data and additional data are stored in the data (Data) storage area of the area 301, and ECC bits are stored in the data storage area 301 via the ECC bus 312.

  When data is read, actual data, additional data, and ECC bits are read from the data storage area 301 and input to the ECC block 350 via the memory bus 311 and the ECC bus 312, and error correction based on the ECC bits is performed in the ECC block 350. After the processing is executed, the corrected data is output to the data bus 302. The error correction in the ECC block 350 is executed based on, for example, a syndrome calculation process. Details of this processing will be described later.

  The data transfer timing and processing timing in the data writing process and reading process are controlled by a control signal output from a control unit such as a CPU (not shown), and executed as a process according to a preprogrammed processing program, for example. It is what is done.

  Details of the error correction code (ECC) setting process executed in the ECC block 350 in the data storage device of the present invention will be described with reference to FIGS. FIG. 7 is a diagram for explaining the details of the Hamming code calculation process executed in the error correction code (ECC) calculation executed in the ECC block 350, and FIG. 8 is executed in the ECC block 350 of the data storage device of the present invention. 6 is a flowchart for explaining a sequence of error correction code (ECC) setting processing and data and ECC bit writing processing to the data storage area 301.

  First, the details of the error correction code (ECC) calculation process executed in the ECC block 350 of the data storage device of the present invention will be described with reference to FIG. Here, as an embodiment, an example of setting an error correction code (ECC) when the ECC calculation unit is 17 bits of data including 16 bits of actual data and 1 bit of additional data and a Hamming code is adopted as the ECC will be described. .

FIG. 7A shows an ECC, that is, a Hamming code calculation processing configuration for a total of 17-bit data of 16-bit actual data of X _{0 to} X ₁₅ and 1-bit additional data X ₁₆ as an ECC calculation unit. . ECC block 350 shown in FIG. 6 receives the write data from the data bus 302 divides the data into 16-bit data as ECC calculation unit sets the 1-bit additional data bits _{X 16} relative to 16-bit data. Additional data bit X ₁₆ is a predetermined value is set to, for example, a bit value [1].

However, often when performing error correction processing on the basis of the ECC, if possible determine the normal value set for additional data bit X ₁₆ is [0] is either [1], added as data bits X _16, or a specified value of any bit values [1] or [0] it is optional.

Here, a description will be given of an example of setting the specified bit values [1] additional data bits X _16. The ECC bits are calculated based on a total of 5 bits, that is, based on a total of 17-bit data of X _{0 to} X ₁₅ 16-bit actual data and 1-bit additional data X ₁₆ using C _{0 to} C ₄ as ECC calculation units.

The exclusive OR (XOR) operation of the bits marked with ◯ shown in FIG. 7A is shown in FIG. 7B and below. Hamming codes C _{0 to} C ₄ as ECC bits are calculated based on the following equation (Equation 1).

ECC block 350 shown in FIG. 6, after enter the write data from the data bus 302 divides the data into 16-bit data as ECC calculation unit, and sets the 1-bit additional data bits _{X 16} relative to 16-bit data In accordance with the above equation, 5-bit ECC bits are calculated based on 16-bit actual data of X _{0 to} X ₁₅ and 17-bit data in total of additional data X ₁₆ .

  In the ECC block 350 shown in FIG. 6, after executing the above-described additional bit setting and ECC bit calculation processing, the actual data and the additional data are stored in the data (Data) storage area of the data storage area 301 via the memory bus 311. Stored. The ECC bit is stored in the ECC storage area of the data storage area 301 via the ECC bus 312.

  The sequence of error correction code (ECC) setting processing executed in the ECC block 350 of the data storage device of the present invention and data and ECC bit writing processing to the data storage area 301 will be described according to the flow of FIG.

In step S101, the ECC block 350 shown in FIG. 6 inputs write data from the data bus 302, divides the data into 16-bit data as an ECC calculation unit, and adds 1 bit to the 16-bit data in step S102. setting the data bits _{X 16.} Additional data bits X _16, as described above, a predetermined value, for example, the bit value [1].

In step S103, it executes a 16-bit real data _X 0 _{to X 15} input from the data bus 302, ECC for a total of 17-bit data of 1-bit additional data _{X 16,} i.e., the process of calculating the Hamming code. This ECC bit calculation processing is executed based on the above equation (Equation 1).

Next, in step S104, 16-bit actual data of X _{0 to} X ₁₅ and 1-bit additional data X ₁₆ in total 17-bit data, and constituent bits of an error correction code generated based on these data, that is, ECC A total of 22 bits of bit value [0] of 5 bits of bits C _{0 to} C ₄ is counted.

In step _S105, the 16-bit real data X 0 _{to X 15,} and 1-bit additional data _{X 16,} during configuration bits five bits of total 22 bits of ECC bits _C 0 -C _4, bit values of [0] If it is determined that the number exceeds half (number of bits 0 ≧ 12), the process proceeds to step S106, and if it is determined that the number of bit values [0] does not exceed half (number of bits 0 <12), Proceed to step S107.

During configuration bits 22 bits, if the number of bit values [0] is determined to more than half (number ≧ 12 bit 0), the process proceeds to step S106, in step _S106, 16-bit real X 0 _{to X 15} and data to generate inverted data of 1 bit additional data X _16, it generates ECC bits based on inverted data, and outputs it as data write these data in the memory area. That is, the inverted value of the data and ECC data is stored in the write latch at the corresponding address and written into the memory cell.

  Note that the inverted data is data in which when the original bit value is [0], this is [1], and when the original bit value is [1], this is [0].

In this way, the inverted 16-bit actual data of X _{0 to} X ₁₅ and the 1-bit additional data of X ₁₆ are output to the memory bus 311, stored in the data (Data) storage area of the data storage area 301, and the inverted data Are output to the ECC bus 312 and stored in the ECC storage area of the memory area.

In the case of the ECC calculation example shown in FIG. 7A, data used for each calculation of the ECC bits C _{0 to} C ₄ (data selected from X _{0 to} X ₁₅ and X ₁₆ as the target of the exclusive OR operation) ) Are all odd numbers. Exclusive OR of the plurality data (Exclusive-OR) operation, to become equal to the least significant bit after the addition of all of the data to be processed, based on the inverted data exclusive logical OR operation result of X ₀ to X ₁₆ is inverted It becomes equal to the value obtained by inverting the exclusive OR operation result of the previous original data.

Therefore, the ECC block 350 does not execute the exclusive OR operation based on the inverted data of X _{0 to} X ₁₆ , but converts the value obtained by inverting the exclusive OR operation result of the original data before the inversion to X _{0 to} X It can be set as ECC bits C _{0 to} C ₄ as the exclusive OR operation result based on ₁₆ inverted data.

That is, if it is determined that the number of bit values [0] exceeds half of the 22-bit configuration bits (number of bits 0 ≧ 12), in step S106, 16-bit actual data of X _{0 to} X ₁₅ ; generates inverted data of 1 bit additional data X _16, the generated ECC bits _C 0 -C ₄ the reversed based on the original bits, which a 16-bit real data _X 0 _{to X 15,} the _{X 16} The ECC bits based on the inverted data of the 1-bit additional data are output to the buses 311 and 312 and stored in the data storage area 301.

On the other hand, in step _S105, X 0 and 16-bit real data _{to X 15,} and 1-bit additional data _{X 16,} during configuration bits five bits of total 22 bits of ECC bits _C 0 -C _4, bit values [0 the number of] does not exceed half if it is determined that (the number of bits 0 <12), the process proceeds to step S107, without executing a reversal _process, and 16-bit real data X 0 _{to X 15,} the _{X 16} 1-bit additional data and ECC bits based on these data are output to each of the buses 311 and 312 and stored in the data storage area 301. That is, the data and the non-inverted value of the ECC data are stored in the write latch of the corresponding address and written into the memory cell.

  By this processing, it is possible to reduce the number of bit values that are [0] of data stored in the data storage area 301 and store them.

As described above with reference to FIGS. 1 to 3, when data is written to a FLOTOX type EEPROM, the bit line (V _D ) of the cell in which data “1” is written has 0 V and data “0”. It is necessary to apply, for example, 18V to the bit line (V _D ) of the cell to which is written.

According to the data storing process of the present invention described _above, include a 16-bit real data X 0 _{to X 15,} and 1-bit additional data _{X 16,} 5-bit ECC bits _C 0 -C _4, a total of 22 bits If the number of 0 is greater than half, the 16-bit actual data of X _{0 to} X ₁₅ and the inverted data of 1-bit additional data of X ₁₆ are used as write data, and the number of 0 included in 22 bits is less than half. In this case, since the 16-bit actual data of X _{0 to} X ₁₅ and the configuration data itself of 1-bit additional data of X ₁₆ are set as the write data, writing of bit [0] in the data write process can be reduced. Therefore, it is possible to reduce the total amount of applied voltage (for example, 18 V) that needs to be supplied to the bit line (V _D ) of the cell in which data “0” is written.

  As a result, it is possible to reduce the burden on the booster circuit mounted on the device that executes the data writing process to the FLOTOX type EEPROM, and the booster circuit can be downsized and the cost of the device can be reduced. Further, since the number of bit lines corresponding to the bit lines that need to be charged, that is, the cells storing the bit value [0], is reduced, the time required for charging the bit lines can be reduced, resulting in a reduction in data write time. Reduction is achieved and high speed data writing is realized.

  An error correction code such as ECC is indispensable for a device that stores data that does not allow error occurrence, such as an encryption processing key and ID data. In the conventional configuration, in order to perform an accurate data writing process, A cell having a high capability is required, and the scale of the booster circuit has to be increased. However, by executing the above-described processing of the present invention, a cell that requires [0] writing is required. Since the number can be reduced, the booster circuit can be reduced in size and the cost of the device can be reduced, and data can be written by a small booster circuit adapted to the reduction in the size of devices such as portable devices and IC cards.

  Next, a detailed configuration of the ECC block 350 that executes processing according to the flow of FIG. 8 will be described with reference to FIG.

  As shown in the figure, the ECC block 350 is located between a data bus for inputting write data to the memory or outputting data read from the memory, a memory bus connected to the memory, and an ECC bus, and writing to the memory. ECC data is generated for the data. Further, as described above with reference to FIGS. 7 and 8, the number of bit values [0] is counted, and inverted data is generated based on the count value, and ECC bits are generated based on the inverted data.

  Details of the configuration and processing of the ECC block 350 will be described with reference to FIG. First, processing at the time of data writing will be described. Based on the control of the data write control signal (XRD) 351, write data is input from the data bus and input to the ECC processing execution unit 356.

  The ECC process execution unit 356 is an error correction code (ECC) processing unit, executes a process of adding additional data bits for each ECC calculation unit, and calculates an ECC bit as an error correction code. This calculation process is executed according to (Equation 1) described above (see FIG. 7).

The ECC bits C _{0 to} C ₄ generated by the ECC processing execution unit 356, 16-bit input data X _{0 to} X ₁₅ as ECC calculation units, and 1-bit additional data X ₁₆ are output to the inversion controller 357, and , 0 is output to the counter 354 that executes counting of data.

  The counter 354 and the comparator 353 are the error correction code generated by the ECC processing execution unit 356 as the error correction code processing means and the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code generation unit data. And a bit value determination process for determining whether or not the data pattern with low power consumption in the data storage process is the inverted data of the error correction code and the error correction code generation unit data. Thus, the counter 354 and the comparator 353 function as a bit value determination unit.

The counter 354 is included in a total of 22 bits of the ECC bits C _{0 to} C ₄ generated by the ECC processing execution unit 356, 16-bit input data X _{0 to} X ₁₅ as ECC calculation units, and 1-bit additional data X ₁₆ The number of bit values [0] to be counted is counted.

  The count value in the counter 354, that is, the number [A] of bit values [0] included in 22 bits is input to the comparator 353. Further, the comparator 353 inputs the number of bit values “0” of the actual data and the additional data as the ECC calculation unit and the value [B] which is a half of the number of bits of the ECC data, and is included in the 22 bits. The number [A] of the value [0] [A] and [B] are compared in magnitude.

In the case of A> B, an operation control signal for causing the inversion controller 357 to execute the inversion process is output, and the 16-bit input data X _{0 to} X ₁₅ as the ECC calculation unit and the inversion of the 1-bit additional data X ₁₆ are output. The signal and an inverted signal of the ECC bits C _{0 to} C ₄ generated by the ECC processing execution unit 356 are generated and output as write data. Under the control of the write control signal XRD 358 for the memory, the inverted data Execute the write process.

In the case of A ≦ B, 16-bit input data X _{0 to} X ₁₅ as ECC calculation units and 1-bit additional data are not performed without performing inversion processing on the inversion controller 357 and without inverting the input value. X ₁₆ and the ECC bits C _{0 to} C ₄ generated in the ECC processing execution unit 356 are output as write data as they are, and write processing of these data is executed under the control of the write control signal XRD 358 for the memory.

  As described above, when the inversion controller 357 determines that the data pattern with low power consumption in the data storage processing for the data storage area is the error correction code (ECC) and the inverted data of the ECC generation unit data, the bit value inversion is performed. Execute the process.

  That is, a control signal is output to the inversion controller 357 based on the determination result of the bit value determination means configured by the counter 354 and the comparator 353, and the data pattern with low power consumption in the data storage processing for the data storage area is inverted. The data is generated by the controller 357 and output as data stored in the memory.

  When data is read, actual data, additional data, and ECC bits are read from the data storage area based on the control of the data read control signal (XRD) 359, and the ECC processing execution unit 356 detects errors based on the ECC bits. Correction processing is executed. As described above, in the processing of the present invention, the write data may be inverted, and in the case of data reading, the ECC processing execution unit 356 determines whether the read data is inverted data. Determine and execute error correction processing according to the determination.

  Further, when the read data is inverted data, the ECC processing execution unit 356 outputs a control signal for causing the inversion controller 355 to execute the inversion processing, and causes the inversion processing of the data after error correction to be performed. Are output to the data bus under the control of the data read signal XRD352. When the read data is not inverted data, the ECC process execution unit 356 outputs the data after error correction under the control of the data read signal XRD 352 without outputting a control signal for causing the inversion controller 355 to execute the inversion process. Output to the bus.

  Data reading from the memory, error correction processing, and inversion control processing will be described with reference to FIGS.

  FIG. 10 is a diagram for explaining the details of the syndrome calculation process for error bit detection executed by the ECC process execution unit 356. FIG. 11 is a flowchart showing a processing sequence of error correction processing and inversion control processing executed when reading data.

First, the details of the syndrome calculation process for error bit detection executed by the ECC process execution unit 356 will be described with reference to FIG. FIG. 10A shows a total of 22 16-bit actual data of X ₀ ′ to X ₁₅ ′ as ECC operation units and 5-bit ECC bits C ₀ ′ to C ₄ ′ of 1-bit additional data X ₁₆ ′. A syndrome S _{0 to} S ₄ calculation processing configuration for bit data is shown. It should be noted that what is indicated by adding ['] to each bit data means that it may be an error bit and does not necessarily match the write data.

The ECC processing execution unit 356 shown in FIG. 9 has 16 bits of actual data X ₀ ′ to X ₁₅ ′, 1 bit additional data X ₁₆ ′, and ECC bits C ₀ ′ to C ₄ ′ from the memory area, for a total of 22 bits. enter the calculated syndromes _S 0 to S _4. Note that the read data may be inverted data.

The syndrome S _{0 to} S ₄ calculation process is a process executed as an exclusive OR (XOR) operation process of bits marked with “◯” shown in FIG. The calculation formulas for calculating the syndromes S _{0 to} S ₄ are shown in FIG. 10B and the following formula (Formula 2).

The ECC processing execution unit 356 executes the above-described syndrome calculation, and based on the calculated values of the syndromes S _{0 to} S ₄ , the 16-bit actual data of X ₀ ′ to X ₁₅ ′ and the 1-bit additional data X ₁₆ ′ 5 bits ECC bits C ₀ ′ to C ₄ ′, whether or not 22 bits of data error are included, and if an error is included, the error occurrence bit is
a) 16-bit actual data of X ₀ ′ to X ₁₅ ′,
b) 1-bit additional data X ₁₆ ',
c) 5 ECC bits C ₀ ′ to C ₄ ′,
It is determined whether it is.
These discrimination processing can be performed based on the syndrome S ₀ to S ₄ calculated value.

  When reading data, the ECC process execution unit 356 and the inversion controller 355 execute different processes based on the presence / absence of an error and the bit position of the error. The processing according to each aspect is summarized as follows.

(1) When no error has occurred (1-1) When the additional bit is inverted, that is, when X ₁₆ ′ = 0, the output data from the ECC processing execution unit 356 is inverted by the inversion controller 355. Output.
(1-2) When the additional bit is not inverted, that is, when X ₁₆ ′ = 1, the output data from the ECC processing execution unit 356 is output as it is without being inverted by the inversion controller 355.

(2) When an error occurs in the ECC bits C ₀ ′ to C ₄ ′ (2-1) When the additional bit is inverted, that is, when X ₁₆ ′ = 0, the ECC processing execution unit 356 The output data is inverted by the inversion controller 355 and output.
(2-2) When the additional bit is not inverted, that is, when X ₁₆ ′ = 1, the output data from the ECC processing execution unit 356 is output as it is without being inverted by the inversion controller 355.

(3) When an error occurs in the 16-bit actual data of X ₀ ′ to X ₁₅ ′ (3-1) When the additional bit is inverted, that is, when X ₁₆ ′ = 0, ECC processing execution unit In 356, error bit correction processing is executed, and the corrected output data is inverted by the inversion controller 355 and output.
(3-2) When the additional bit is not inverted, that is, when X ₁₆ ′ = 1, the ECC bit execution unit 356 executes error bit correction processing, and the inverted output data is inverted by the inversion controller 355. It outputs as it is without making it.

(4) When an error occurs in the additional data of X ₁₆ ′ (4-1) When the additional bit after error correction is inverted, that is, when X ₁₆ ′ = 0, the ECC processing execution unit 356 Is inverted by the inversion controller 355 and output.
(4-2) When the additional bit after error correction is not inverted, that is, when X ₁₆ ′ = 1, the output data from the ECC processing execution unit 356 is output as it is without being inverted by the inversion controller 355.

  As described above, the ECC processing execution unit 356 determines whether or not the bit value is inverted when writing the data to the memory based on the value of the additional bit, and executes the data writing process involving the inversion of the bit value. Only in some cases, it is possible to cause the inversion controller 355 to execute data inversion processing and output inverted data, that is, original data.

  Next, a processing sequence of error correction processing and inversion control processing executed when reading data will be described with reference to FIG.

In step S201, the data read from the memory area (16-bit actual data of X ₀ ′ to X ₁₅ ′ and 1-bit additional data X ₁₆ ′) is input to the ECC processing execution unit 356 via the memory bus. The bits (C ₀ ′ to C ₄ ′) are input to the ECC processing execution unit 356 via the ECC bus.

In step S202, the ECC processing execution unit 356 converts the input data (16-bit actual data of X ₀ ′ to X ₁₅ ′ and 1-bit additional data X ₁₆ ′) and ECC bits (C ₀ ′ to C ₄ ′). Based on this, the syndromes S _{0 to} S ₄ calculation processing is executed. This calculation process is executed based on the above-described (Formula 2).

Based on the syndrome _S 0 to S ₄ calculated in step S203, it determines the presence or absence of error. If there is no error, the process advances to step S204 to determine whether or not the additional bit is inverted, that is, whether X ₁₆ ′ = 0 or X ₁₆ ′ = 1.

When the additional bit is inverted, that is, when X ₁₆ ′ = 0, the process proceeds to step S206, and the output data from the ECC processing execution unit 356 is inverted by the inversion controller 355 and output.

When the additional bit is not inverted, that is, when X ₁₆ ′ = 1, the process proceeds to step S205, and the output data from the ECC processing execution unit 356 is output as it is without being inverted by the inversion controller 355.

  If it is determined in step S203 that an error is included, the process proceeds to step S207, the error is corrected, and the process proceeds to step S204.

In step S204, the following processing is executed based on the correct X ₁₆ ′ value in the corrected data.

If the value of the additional bit is inverted, that is, if the correct value of X ₁₆ ′ = 0, the process proceeds to step S206, where error correction processing is performed in the ECC processing execution unit 356, and the output data after error correction is inverted. Inverted by the controller 355 and output.

If the value of the additional bit is not inverted, that is, if the correct value of X ₁₆ ′ = 1, the process proceeds to step S205, where error correction processing is performed in the ECC processing execution unit 356, and the output data after error correction is inverted. The controller 355 outputs the signal as it is without being inverted.

  Through the above processing, error correction and data inversion are executed reliably, and data equal to the original write processing data is output to the data bus as read data.

  According to the data writing method and the reading method of the present invention described above, the number of writes of the bit value [0] per write processing unit to the memory is suppressed to almost half or less of the total number of bits of the write unit. The number of bit lines that need to be charged based on the boosted voltage can be halved, the booster circuit and current consumption can be reduced, and high-speed data write processing is possible.

  When reading data, it is determined based on the additional bit data whether the write data to the memory is inverted data. If the data is inverted, re-inversion processing is performed to obtain original data. Since the data is returned and output, normal data reading can be performed.

  The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the gist of the present invention. In other words, the present invention has been disclosed in the form of exemplification, and should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims section described at the beginning should be considered.

  The series of processes described in the specification can be executed by hardware, software, or a combined configuration of both. When executing processing by software, the program recording the processing sequence is installed in a memory in a computer incorporated in dedicated hardware and executed, or the program is executed on a general-purpose computer capable of executing various processing. It can be installed and run.

  For example, the program can be recorded in advance on a hard disk or ROM (Read Only Memory) as a recording medium. Alternatively, the program is temporarily or permanently stored on a removable recording medium such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. It can be stored (recorded). Such a removable recording medium can be provided as so-called package software.

  The program is installed on the computer from the removable recording medium as described above, or is wirelessly transferred from the download site to the computer, or is wired to the computer via a network such as a LAN (Local Area Network) or the Internet. The computer can receive the program transferred in this manner and install it on a recording medium such as a built-in hard disk.

  Note that the various processes described in the specification are not only executed in time series according to the description, but may be executed in parallel or individually according to the processing capability of the apparatus that executes the processes or as necessary. Further, in this specification, the system is a logical set configuration of a plurality of devices, and the devices of each configuration are not limited to being in the same casing.

  As described above, the present invention calculates the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code and the error correction code generation unit data, and the data pattern with low power consumption in the data storage processing Is a bit line that needs to be charged based on the boost voltage because the bit value inversion process is executed and the data is written to the memory when it is determined that the data is the inverted data of the error correction code and the error correction code generation unit data. The number can be halved, the booster circuit and current consumption can be reduced, and high-speed data write processing can be performed. Therefore, data can be written by a small booster circuit adapted to miniaturization of devices such as portable devices and IC cards, and can be applied to portable devices and IC cards.

  Further, according to the configuration of the present invention, when reading data, it is determined based on the additional bit data whether the write data to the memory is inverted data. Since the reversal process is executed and the data is returned to the original data and output, normal data can be read out. Therefore, data can be written by a small booster circuit adapted to miniaturization of devices such as portable devices and IC cards, and the present invention can be applied to portable devices and IC cards.

It is a figure which shows the structure of EEPROM of a FLOTOX type. It is a figure which shows the example of a setting of the bias voltage at the time of the data writing in a FLOTOX type EEPROM. It is a figure which shows the example of a setting of the bias voltage at the time of the data execution in the FLOTOX type EEPROM at the time of data writing. It is a figure which shows the detail of a EEPROM structure of a FLOTOX type. It is a figure explaining the calculation process of ECC. It is a figure which shows the device structure of the data storage device which concerns on this invention, ie, the data storage device carrying the ECC (Error Correct Code) circuit as an error correction code. It is a figure explaining the calculation process of ECC in the data storage device concerning the present invention. 4 is a flowchart illustrating an ECC calculation process and a data write process sequence in the data storage device according to the present invention. It is a figure which shows the detailed structure of the ECC block in the data storage device which concerns on this invention. It is a figure explaining the syndrome calculation process at the time of the data reading in the data storage device which concerns on this invention. It is a flowchart explaining the data read-out process sequence containing the syndrome calculation process and data inversion process in the data storage device which concerns on this invention.

Explanation of symbols

101 Control Gate 102 Floating Gate 103 Select Gate 104 Tunnel Oxide Film 105 Drain 106 Source 107 Drain 201 Data Storage Area 202 Data Bus 203 Data Write Control Signal (XRD)
204 Data read control signal (XRD)
205 ECC circuit 211 Memory bus 212 ECC bus 301 Data storage area 302 Data bus 311 Memory bus 312 ECC bus 350 ECC block 351 Data write control signal (XRD)
352 Data read control signal (XRD)
353 Comparator 354 Counter 355 Inversion controller 356 ECC processing execution unit 357 Inversion controller 358 Data write control signal (XRD)
359 Data read control signal (XRD)

Claims (16)

A data storage device,
A data storage area;
Error correction code processing means for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the storage target data stored in the data storage area has a predetermined data length;
The ratio of the error correction code generated by the error correction code processing means and the bit value [0] or [1] in all the constituent bits of the error correction code generation unit data is calculated, and the data with low power consumption in the data storage processing Bit value determination means for determining whether a pattern is the error correction code and inverted data of the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result of the bit value determination means Write data inversion control means for executing
A data storage device comprising:   The data storage device according to claim 1, wherein the additional data is 1-bit data set for the unit length data, and is data having a predetermined bit value.   The data storage device according to claim 1, wherein the error correction code is a Hamming code capable of specifying an error occurrence bit position. The error correction code processing means includes
An error correction process for read data from the data storage area, and a determination process for determining whether the read data is inverted data of the original data;
The data storage device further includes:
In the error correction code processing means, when it is determined that the read data is the inverted data of the original data, a read data inversion control means for executing an inversion process of the read data;
The data storage device according to claim 1, comprising: The error correction code processing means includes
5. The data storage device according to claim 4, wherein a syndrome calculation process is performed on read data from the data storage area, and an error correction process based on the calculated syndrome is executed. The error correction code processing means includes
5. The data according to claim 4, wherein a determination process is performed to determine whether or not the read data is inverted data of the original data based on a bit value of additional data included in the read data. Storage device.   2. The data storage device according to claim 1, wherein the data storage area has a FLOTOX (Floating Gate with Tunnel Oxide) configuration having a floating gate. The data storage area is
A configuration in which a bias voltage is applied to a storage cell having a bit value of 0,
The bit value determining means calculates a ratio of the error correction code generated by the error correction code processing means and the bit value [0] occupying all the constituent bits of the error correction code generation unit data. It is a configuration that executes a process of determining whether or not a data pattern with a small ratio is the inverted data of the error correction code and the error correction code generation unit data,
The write data inversion control means is configured to execute inversion processing when a data pattern with a small bit value [0] ratio is inversion data of the error correction code and the error correction code generation unit data. The data storage device according to claim 1, wherein: Stored data processing method,
An error correction code generation processing step for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the data to be stored is a predetermined data length stored in the data storage area;
The error correction code generated in the error correction code generation processing step and the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code generation unit data are calculated to reduce power consumption in the data storage process. A bit value determination step for determining whether a data pattern is inverted data of the error correction code and the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result in the bit value determination step A write data inversion control step for executing
And a stored data processing method.   10. The stored data processing method according to claim 9, wherein the additional data is 1-bit data set for the unit length data, and is data having a predetermined bit value.   10. The stored data processing method according to claim 9, wherein the error correction code is a Hamming code capable of specifying an error occurrence bit position. The stored data processing method further includes:
An error correction step of performing error correction processing of read data from the data storage area;
A read data determination step for performing a process of determining whether the read data is inverted data of the original data;
When it is determined that the read data is the inverted data of the original data, a read data inversion control step for executing an inversion process of the read data;
10. The stored data processing method according to claim 9, further comprising: The error correction step includes
13. The stored data processing method according to claim 12, wherein the stored data processing method is a step of executing a syndrome calculation process for read data from the data storage area and executing an error correction process based on the calculated syndrome. The read data determination step includes
13. The storage according to claim 12, wherein the step of determining whether or not the read data is inverted data of the original data based on a bit value of the additional data included in the read data. Data processing method. The data storage area is a FLOTOX (Floating Gate with Tunnel Oxide) configuration having a floating gate, and has a configuration for applying a bias voltage to a storage cell having a bit value of 0,
The bit value determination step calculates a ratio of the bit value [0] to all the constituent bits of the error correction code and the error correction code generation unit data, and a data pattern having a small ratio of the bit value [0] indicates the error Executing a process for determining whether the correction code and the inverted data of the error correction code generation unit data;
The write data inversion control step performs an inversion process when a data pattern having a small bit value [0] ratio is inversion data of the error correction code and the error correction code generation unit data. The stored data processing method according to claim 9. A computer program for executing data storage processing for memory,
An error correction code generation processing step for executing error correction code generation processing for error correction code generation unit data in which additional data is additionally set to unit length data in which the data to be stored is a predetermined data length stored in the data storage area;
The error correction code generated in the error correction code generation processing step and the ratio of the bit value [0] or [1] to all the constituent bits of the error correction code generation unit data are calculated to reduce power consumption in the data storage process. A bit value determination step for determining whether a data pattern is inverted data of the error correction code and the error correction code generation unit data;
Bit value inversion processing when it is determined that the data pattern with low power consumption in the data storage processing is the inverted data of the error correction code and the error correction code generation unit data based on the determination result in the bit value determination step A write data inversion control step for executing
A computer program characterized by comprising:

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