JP2005167278A - Bipolar transistor and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bipolar transistor that has a low saturation voltage between the collector and emitter, has a small size, and can be manufactured by a small number of processes, and to provide a semiconductor device in which the bipolar transistor and a MOS transistor are formed on the same substrate. <P>SOLUTION: A high-concentration region 15 for reducing the saturation voltage VCE (sat) between the collector and emitter is formed so that a base region 13 of an NPN transistor 10 is surrounded. The high-concentration region 15 needs not be formed so deep to reach a buried layer 11, thus reducing lateral expansion. When forming a source region 24 and a drain region 25 of an NMOS transistor 20 formed on the same silicon substrate 30 along with the NPN transistor 10, a high-concentration region 15 can be formed in the same process, thus excluding an exclusive diffusion process for forming the high-concentration region 15, and manufacturing a semiconductor device 1 with a small number of processes. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bipolar transistor and a semiconductor device. More specifically, the present invention relates to a bipolar transistor with a reduced collector-emitter saturation voltage and a semiconductor device in which the bipolar transistor and a MOS transistor are formed on the same substrate.

  FIG. 5 shows a structure of a conventional semiconductor device in which an NPN transistor and an NMOS transistor are formed on the same substrate. 5A is a plan view and FIG. 5B is a cross-sectional view.

In the NPN transistor 80, an N + buried layer 82 containing As (arsenic), Sb (antimony), etc. is formed in a P-type silicon substrate 81, and a collector region 83 composed of an N− layer is formed on the N + buried layer 82. A base region 84 made of a P− layer is formed in 83, and an emitter region 85 made of an N layer is formed in the base region 84. A collector wall 86 made of an N + layer in which P (phosphorus) is diffused is formed in the collector region 83, and a collector contact region 87 made of an N + layer in which As is diffused is formed in the collector wall 86. A collector electrode 88 is connected to the surface. The collector wall 86 is provided to reduce the collector series resistance of the NPN transistor 80 and reduce the collector-emitter saturation voltage V _CE (sat). A base electrode 91 is connected to the base region 84 via a base contact region 89 made of a P + layer. An emitter electrode 93 is connected to the emitter region 85 via an emitter contact region 92. 94 is an element isolation oxide film layer (LOCOS), and 95 is an insulating film.

  The NMOS transistor 90 diffuses As in the P-type silicon substrate 81 to form a source region 96 and a drain region 97 composed of an N + layer, and a gate composed of a SiO 2 film on an intermediate region between the source region 96 and the drain region 97. A gate electrode 99 is formed through an insulating film 98. Around the gate electrode 99, an LDD region 100 made of N− in which P (phosphorus) is diffused is formed. A source electrode 101 is connected to the source region 96, and a drain electrode 102 is connected to the drain region 97.

As described above, the NPN transistor 80 of the conventional semiconductor device is provided with the collector wall 86 for the purpose of reducing the collector-emitter saturation voltage V _CE (sat). Since the collector wall 86 is formed so deep as to reach the buried layer 82 by high-concentration impurity thermal diffusion, the collector wall 86 extends in a wide range in the lateral direction. For this reason, there is a problem that the distance between the collector electrode 88 and the base electrode 91 is increased, and the transistor size is increased. Further, in order to form the collector wall 86 deep enough to reach the buried layer 82, a dedicated thermal diffusion process for forming the collector wall 86 is required. Therefore, the semiconductor having the NPN transistor 80 and thus the NPN transistor 80 is required. There has been a problem that the number of manufacturing steps of the apparatus is increased.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a bipolar transistor having a low collector-emitter saturation voltage, a small size, and capable of being manufactured in a small number of steps, and the bipolar transistor and the MOS transistor. An object of the present invention is to provide a semiconductor device formed on the same substrate.

In order to achieve the above object, a bipolar transistor according to the present invention comprises a base region formed in a collector region and an emitter region formed in the base region, and surrounds almost the entire circumference of the base region. Thus, a high concentration region for reducing the collector-emitter saturation voltage having a higher concentration than that of the base region was formed.

  Since this high concentration region is formed so as to surround almost the entire circumference of the base region, the saturation voltage between the collector and the emitter is not formed so as to reach the buried layer like the collector wall in the conventional bipolar transistor. Therefore, the lateral spread can be reduced. Therefore, the size of the bipolar transistor can be made smaller than before. Further, since the high concentration region can be formed by using the manufacturing process of other elements formed on the same substrate together with the bipolar transistor, a dedicated diffusion step for forming the high concentration region is omitted, and there are few. A bipolar transistor can be manufactured by the number of processes.

  The semiconductor device of the present invention is a semiconductor device in which a base region is formed in a collector region, and a bipolar transistor and a MOS transistor formed by forming an emitter region in the base region are formed on the same substrate. A high concentration region for reducing the collector-emitter saturation voltage was formed so as to surround almost the entire circumference of the region.

  Since the high concentration region does not need to be formed deep enough to reach the buried layer unlike the collector wall in the conventional bipolar transistor, the lateral spread can be reduced. Therefore, the size of the bipolar transistor can be made smaller than before. In addition, since the high concentration region can be formed by using the manufacturing process of the MOS transistor formed on the same substrate together with the bipolar transistor, a dedicated diffusion step for forming the high concentration region can be omitted. Therefore, since the heat treatment process accompanying diffusion can be reduced, the extension of the diffusion length of the already formed diffusion region can be reduced, and a highly accurate and highly reliable semiconductor device can be provided. Moreover, since the diffusion process is reduced once, the semiconductor device can be manufactured with a small number of processes.

  The high concentration region may be formed in the same process as the source region and drain region of the MOS transistor. In this way, by forming the high concentration region for reducing the collector-emitter saturation voltage of the bipolar transistor in the same process as the source region and drain region of the MOS transistor, a dedicated diffusion for forming the high concentration region is formed. A process can be omitted and a semiconductor device can be manufactured with a small number of processes.

  The high concentration region is preferably formed in the same process as a region for countermeasures against electrostatic breakdown provided in a source region and a drain region of the MOS transistor. Thus, by forming the high concentration region for reducing the collector-emitter saturation voltage of the bipolar transistor in the same process as the region for countermeasures against electrostatic breakdown of the MOS transistor, a dedicated region for forming the high concentration region is formed. Thus, the semiconductor device can be manufactured with a small number of steps.

  The high-concentration region includes a first region formed in the same process as a region for preventing electrostatic breakdown provided in a source region and a drain region of the MOS transistor, and the same process as a source region and a drain region of the MOS transistor. It is desirable that the second region formed by Thus, between the collector and emitter of the bipolar transistor, the first region formed in the same process as the region for countermeasures against electrostatic breakdown of the MOS transistor and the second region formed in the same process as the source region and the drain region. Also by configuring a high concentration region for reducing the saturation voltage, the semiconductor device can be manufactured with a smaller number of processes than in the prior art.

  As described above, in the bipolar transistor of the present invention, the high concentration region for reducing the collector-emitter saturation voltage is formed so as to surround the entire circumference of the base region of the bipolar transistor, so that the transistor size is increased. Without this, the collector-emitter saturation voltage can be reduced. Further, since the high concentration region can be formed by using the manufacturing process of other elements formed on the same substrate together with the bipolar transistor, a dedicated diffusion step for forming the high concentration region is omitted, and there are few. It can be manufactured with the number of steps.

  In the semiconductor device of the present invention, a high concentration region for reducing the collector-emitter saturation voltage is formed so as to surround almost the entire circumference of the base region of the bipolar transistor, so that the collector-emitter region is not increased without increasing the transistor size. The saturation voltage can be reduced. In addition, since the high concentration region can be formed by using the manufacturing process of the MOS transistor formed on the same substrate together with the bipolar transistor, a dedicated diffusion step for forming the high concentration region is not necessary and accompanying the diffusion. Since the number of heat treatment steps is reduced, a highly accurate and highly reliable semiconductor device can be manufactured with a small number of steps.

  Next, embodiments of the present invention will be described with reference to the drawings.

  1A is a plan view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 1B is a cross-sectional view. This semiconductor device 1 is formed by forming an NPN transistor 10 and an NMOS transistor 20 on the same silicon substrate 30.

  The NPN transistor 10 diffuses As (arsenic), Sb (antimony), etc. in a P-type silicon substrate 30 to form an N + buried layer 11, and forms a collector region 12 composed of an N− layer thereon. A base region 13 made of a P− layer is formed in the collector region 12, and an emitter region 14 made of an N layer is formed in the base region 13.

A high concentration region 15 for reducing the collector-emitter saturation voltage V _CE (sat) is formed in the collector region 12 so as to completely surround the entire circumference of the base region 13. The electrode 16 is connected. The high concentration region 15 is composed of an N + layer in which As (arsenic) is diffused.

  A base contact region 17 made of a P + layer is formed in the base region 13, and a base electrode 18 is connected to the surface of the base contact region 17. An emitter electrode 21 is connected to the emitter region 14 via an emitter contact region 19. 22 is an element isolation oxide film layer (LOCOS), and 23 is an insulating film.

  The NMOS transistor 20 diffuses As in the P-type silicon substrate 30 to form a source region 24 and a drain region 25 made of an N + layer, and is made of an SiO 2 film on an intermediate region between the source region 24 and the drain region 25. A gate electrode 27 is formed through a gate insulating film 26. Around the gate electrode 27, a low concentration diffusion region (LDD) region 28 made of an N− layer in which P (phosphorus) is diffused is formed. A source electrode 31 is connected to the source region 24, and a drain electrode 32 is connected to the drain region 25.

  The high concentration region 15 is formed in the same process when the source region 24 and the drain region 25 of the NMOS transistor 20 are formed. That is, when As is diffused in the P-type silicon substrate 30 to form the source region 24 and the drain region 25 made of the N + layer, As (arsenic) having the same concentration as the source region 24 and the drain region 25 in the collector region 12 is formed. Is diffused to form a high concentration region 15 made of an N + layer.

  The high concentration region 15 does not need to be formed deep enough to reach the buried layer 82 (11) like the collector wall 86 in the NPN transistor 80 having the conventional structure shown in FIG. Can be small. Therefore, the size of the NPN transistor 10 can be made smaller than before.

Further, by forming the high concentration region 15 for reducing the collector-emitter saturation voltage V _CE (sat) of the NPN transistor 10 by using the process of forming the source region 24 and the drain region 25 of the NMOS transistor 20, The semiconductor device 1 can be manufactured with a small number of processes by omitting a dedicated diffusion process for forming the high concentration region 15.

  The high concentration region 15 also functions as a guard ring that prevents formation of parasitic transistors.

  FIG. 2 is a sectional view showing a second embodiment of the semiconductor device according to the present invention. In the semiconductor device 2, an NPN transistor 40 and an NMOS transistor 50 are formed on the same silicon substrate 30. 1 differs from the semiconductor device 1 of FIG. 1 in that the high concentration region 41 formed in the collector region 12 of the NPN transistor 40 is composed of an N + layer in which P (phosphorus) having a diffusion coefficient larger than As (arsenic) is diffused. In addition, an electrostatic breakdown countermeasure region 51 is formed by diffusing P (phosphorus) in the source region 24 and the drain region 25 of the NMOS transistor 50.

  The high concentration region 41 is formed in the same process when the region 51 for countermeasures against electrostatic breakdown of the NMOS transistor 50 is formed. That is, when P (phosphorus) is diffused in the P-type silicon substrate 30 to form an N + layer countermeasure 51 for electrostatic breakdown, the same concentration as the electrostatic breakdown countermeasure 51 in the collector region 12 is formed. P (phosphorus) is diffused to form a high concentration region 41 made of an N + layer.

Thus, the high concentration region 41 for reducing the collector-emitter saturation voltage V _CE (sat) of the NPN transistor 40 is formed by using the step of forming the region 51 for countermeasures against electrostatic breakdown of the NMOS transistor 50. As a result, a dedicated diffusion step for forming the high concentration region 41 can be omitted, and the semiconductor device 2 can be manufactured with a small number of steps.

  FIG. 3 is a sectional view showing a third embodiment of the semiconductor device according to the present invention. This semiconductor device 3 is formed by forming an NPN transistor 60 and an NMOS transistor 70 on the same silicon substrate 30. 2 differs from the semiconductor device 2 of FIG. 2 in that a high concentration region 61 formed in the collector region 12 of the NPN transistor 60 includes a first region 61A composed of an N + layer in which P (phosphorus) is diffused, and As (arsenic). The second region 61B is made of a diffused N + layer.

  The first region 61A of the high concentration region 61 is formed in the same process when forming the region 51 for countermeasure against electrostatic breakdown of the NMOS transistor 70, and the second region 61B is formed when forming the source region 24 and the drain region 25. Are formed in the same process. That is, when P (phosphorus) is diffused in the P-type silicon substrate 30 to form an N + layer countermeasure 51 for electrostatic breakdown, the same concentration as the electrostatic breakdown countermeasure 51 in the collector region 12 is formed. First region 61A made of N + layer is formed by diffusing P (phosphorus), and As is diffused in region 51 for countermeasure against electrostatic breakdown to form source region 24 and drain region 25 made of N + layer. At this time, As of the same concentration as the source region 24 and the drain region 25 is diffused in the first region 61A, thereby forming a second region 61B made of an N + layer.

As described above, the collector-emitter saturation voltage V _CE (sat) of the NPN transistor 40 is obtained by using the formation process of the electrostatic breakdown countermeasure region 51 of the NMOS transistor 70 and the formation process of the source region 24 and the drain region 25. By forming the high concentration region 61 for reducing the above, it is possible to omit the dedicated diffusion step for forming the high concentration region 61 and to manufacture the semiconductor device 3 with a small number of steps.

4 shows collector-emitter resistance characteristics (V _CE (sat) / I _C ) in the NPN transistor having the conventional structure shown in FIG. 5 and the NPN transistor having the structure of the embodiment shown in FIGS. That is, the measurement result of the change characteristic of the collector-emitter saturation voltage V _CE (sat) with respect to the collector current I _C is shown. As can be seen from the measurement result, as shown by the curve b, in the case of the first embodiment, the resistance value increases slightly when the collector current I _C becomes larger than in the case of the conventional structure (curve c). However, the overall characteristics are almost the same as those of the conventional structure. In the case of the second and third embodiments, as indicated by the curve d, the resistance value becomes smaller as the collector current I _C becomes larger than in the conventional structure. Here, the curve a is a diagram showing the current-voltage characteristics when the collector wall is not formed in the conventional structure.

In the above embodiment, the high concentration region for reducing the collector-emitter saturation voltage V _CE (sat) of the NPN transistor is formed so as to completely surround the entire circumference of the base region 13. It may be formed without a part.

  In the above embodiment, the semiconductor device in which the NPN transistor and the NMOS transistor are formed on the same substrate has been described. However, the present invention is a semiconductor in which the PNP transistor and the PMOS transistor are formed on the same substrate. It can also be applied to devices. In that case, the dopant type and the conductivity type of each region described in the above embodiment are all reversed.

  As described above, the bipolar transistor of the present invention can form a high concentration region by using a manufacturing process of another element formed on the same substrate together with the bipolar transistor, thereby forming the high concentration region. Therefore, it can be manufactured with a small number of steps without using a dedicated diffusion step, and thus can be applied to various devices in an integrated circuit.

(A) is a top view which shows 1st Embodiment of the semiconductor device concerning this invention, FIG.1 (b) is sectional drawing. It is sectional drawing which shows 2nd Embodiment of the semiconductor device concerning this invention. It is sectional drawing which shows 3rd Embodiment of the semiconductor device concerning this invention. Collector - is a graph showing measurement results of the emitter resistance characteristic _{(V CE (sat) / I} C). (A) is a top view which shows the structure of the conventional semiconductor device, (b) is sectional drawing.

Explanation of symbols

1: Semiconductor device 2: Semiconductor device 3: Semiconductor device 10: NPN transistor (bipolar transistor)
11: buried layer 12: collector region 13: base region 14: emitter region 15: high concentration region 16: collector electrode 18: base electrode 20: NMOS transistor (MOS transistor)
21: Emitter electrode 24: Source region 25: Drain region 27: Gate electrode 30: Silicon substrate 31: Source electrode 32: Drain electrode 40: NPN transistor (bipolar transistor)
41: High concentration region 50: NMOS transistor (MOS transistor)
51: Area for countermeasures against electrostatic breakdown 60: NPN transistor (bipolar transistor)
61: High concentration region 61A: First region 61B: Second region 70: NMOS transistor (MOS transistor)

Claims (5)

In a bipolar transistor in which a base region is formed in a collector region and an emitter region is formed in the base region,
A bipolar transistor characterized in that a high concentration region having a higher concentration than the base region is formed so as to reduce a collector-emitter saturation voltage so as to surround substantially the entire circumference of the base region. In a semiconductor device in which a base region is formed in a collector region and an emitter region is formed in the base region and a bipolar transistor and a MOS transistor are formed on the same substrate,
A semiconductor device characterized in that a high-concentration region having a higher concentration than the base region is formed so as to reduce the collector-emitter saturation voltage so as to surround substantially the entire circumference of the base region.   The semiconductor device according to claim 2, wherein the high concentration region is formed in the same process as the source region and the drain region of the MOS transistor.   3. The semiconductor device according to claim 2, wherein the high concentration region is formed in the same process as a region for countermeasures against electrostatic breakdown provided in a source region and a drain region of the MOS transistor.   The high-concentration region includes a first region formed in the same process as a region for countermeasures against electrostatic breakdown provided in a source region and a drain region of the MOS transistor, and the same process as a source region and a drain region of the MOS transistor. The semiconductor device according to claim 2, comprising: a second region formed by:

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