JP2005158107A - Signal processing circuit for optical disk recording / reproducing apparatus - Google Patents

Abstract

A signal processing circuit of an optical disc recording / reproducing apparatus is provided that can test the signal processing circuit (recording data generation circuit, etc.) at a frequency exceeding an upper limit speed of an LSI tester.
In a signal processing circuit of an optical disc recording / reproducing apparatus for recording and reproducing data with respect to an optical disc, an EFM signal (EFM signal output) is output from a recording data generation unit, and the data reproducing unit is provided inside the signal processing circuit. (CD-DSP9) and test whether or not recording data was correctly generated by performing playback processing on the delivered EFM signal (“Check if there are C1 and C2 errors by LSI tester. ]) Is performed (signal processing circuit ST1).
[Selection] Figure 2

Description

  The present invention relates to a signal processing circuit of an optical disc recording / reproducing apparatus, and in particular, an optical disc recording / reproducing which enables a test of the signal processing circuit (recording data generation circuit, etc.) to be performed at a frequency exceeding the upper limit speed of an LSI tester. The present invention relates to a signal processing circuit of the apparatus.

FIG. 6 is a block diagram illustrating a conventional optical disc recording / reproducing apparatus.
This optical disc recording / reproducing apparatus 100 can record and reproduce CD-R / RW, DVD + R / RW, RW, and DVD-R / RW.

  As shown in FIG. 6, the optical disc recording / reproducing apparatus 100 includes an optical disc 101, a spindle motor 102, a motor driver 103, a servo controller 104, an optical pickup 105, a read amplifier 106, a CD / DVD decoder 107, and a CD-ROM / DVD error correction. 108, buffer manager 109, buffer RAM 110, ATAPI / SCSI host interface 111, D / A converter 112, ATIP / ADIP / LPP decoder 113, write clock generator 114, CD / DVD encoder 115, CD-ROM / DVD Parity encoder 116, A laser control circuit 117, a CPU 118, a ROM 119, and a RAM 120 are provided.

  The optical disc recording / reproducing apparatus 100 rotates the optical disc 101 with a spindle motor 102. The spindle motor 102 is rotationally controlled by a motor driver 103 and a servo controller 104. The optical pickup 105 includes a semiconductor laser, an optical system, a focus actuator, a track actuator, a light receiving element, a position sensor, and the like (not shown), and irradiates the optical disc 101 with laser light.

  Next, the operation of the optical disc recording / reproducing apparatus 100 will be described separately for “data reproduction” for reading data on the optical disc and for “data recording” for writing data on the optical disc. Data reproduction is performed by a data reproduction circuit 100A indicated by a one-dot chain line in the drawing. Data recording is performed by a recording data generation circuit 100B indicated by a two-dot chain line.

  In “data reproduction”, a reproduction signal obtained by the optical pickup 105 is amplified by a read amplifier 106, binarized, and then input to a CD / DVD decoder 107. The CD / DVD decoder 107 performs EFM demodulation and CIRC calculation (deinterlib, error correction) in the case of the CD format on the input data, and performs 8-16 demodulation in the case of the DVD format, and the subsequent CD-ROM Input to / DVD error correction 108.

  The CD-ROM / DVD error correction unit 108 stores the input data in the buffer RAM 110 as needed via the buffer manager 109, and performs error correction processing on the stored data in order to further improve the reliability of the data. I do. Also in this case, data exchange with the buffer RAM 110 such as reading of stored data and data writing back by error correction is performed via the buffer manager 109.

Data for which the error correction processing has been completed by the CD-ROM / DVD error correction 108 is read out by the ATAPI / SCSI host interface 111 via the buffer manager 109 and transferred to the host.
When the data on the optical disc is music data (CD-DA), the data output from the CD / DVD decoder 107 is input to the D / A converter 112 and taken out as an analog audio signal.
In the case of the CD format, the CD / DVD decoder 107 also processes and outputs the subcode data. Time information on the optical disk can be obtained from the subcode data.

  In “data recording”, the wobble signal on the optical disc is input to the ATIP / ADIP / LPP decoder 113 via the optical pickup 105, and the synchronization signal and time information / ID information are received by the ATIP / ADIP / LPP decoder 113. Generate demodulated. The write clock generator 114 generates a channel clock corresponding to the writing speed. The CD / DVD encoder 115 enables writing from an accurate position based on information obtained from the ATIP / ADIP / LPP decoder 113.

  However, when writing after an area where data has already been written by appending etc., the quality of the Wobble signal is bad, and the ATIP / ADIP / LPP decoder 113 may not be able to generate accurate synchronization signals, time information, and ID information. is there. In this case, it is also possible to perform alignment by using the subcode sync, subcode data, and ID information at the time of data reproduction described above.

  Data at the time of data recording is transferred from the host to the buffer RAM 110 via the buffer manager 109. The CD-ROM / DVD Parity encoder 116 reads the data in the buffer RAM 110 via the buffer manager 109, adds an error correction code, EDC code, SYNC code, header information, ID information, etc., and writes it back to the buffer RAM 110.

  Also, the CD-ROM / DVD Parity encoder 116 reads the prepared data from the buffer RAM 110 via the buffer manager 109, and writes the data to the SRAM 115a for CIRC calculation in the CD / DVD encoder 115 in the case of the CD format. In the case of the CD format, the CD / DVD encoder 115 performs CIRC calculation on the data in the CIRC calculation SRAM 115a, adds an error correction code and interleaves, and outputs the EFM-modulated data after the calculation.

For DVD format, output 8-16 modulated. Data output from the CD / DVD encoder 115 is recorded on the optical disc 101 via the laser control circuit 117 and the optical pickup 105.
The CPU 118 grasps the current state for data reproduction and data recording in data reproduction and data recording, and issues a command. (For example, Patent Document 1)

By the way, as described above, the CIRC operation SRAM 115a is used for operations in the circuit (record data generation circuit 100B) when generating record data.
The CIRC operation SRAM 115a is required to have an operation speed corresponding to the data recording speed. For example, considering the case of 48 times recording, the CIRC arithmetic SRAM 115a also needs to operate at about 206 MHz corresponding to 48 times.
JP 2003-059051 A

  However, in the LSI test performed at the time of product (optical disc recording / reproducing apparatus) shipment, the upper limit frequency of the LSI tester is determined, and the control circuit (recording data generation circuit 100B) including the CD / DVD encoder 115 is operated at 48 times speed or equivalent. Currently, no tests have been performed.

  The reason is as follows. That is, in the test at the time of product shipment in the current recording data generation process, a clock is supplied from the LSI tester, operation conditions and data are input, and the recording data generation circuit 100B of the optical disc recording / reproducing apparatus 100 operates accordingly. , EFM signal is output.

  This is because the operation test at a frequency exceeding the upper limit frequency of the LSI tester cannot be performed because the LSI tester determines whether or not the EFM output is correct at a timing according to the clock frequency.

  Under such circumstances, when operating at a frequency exceeding the upper limit speed of the LSI tester, there is a problem that the operation of the CIRC arithmetic SRAM 115a becomes abnormal, or the recording data generation circuit 100B malfunctions without a speed margin. The defect could not be sorted out by the LSI tester.

  The present invention has been made to solve the above-described problems, and is an optical disc recording / reproducing that enables the signal processing circuit (recording data generation circuit, etc.) to be tested at a frequency exceeding the upper limit speed of the LSI tester. An object is to provide a signal processing circuit of an apparatus.

In order to achieve this object, the invention according to claim 1 is a signal processing circuit of an optical disc recording / reproducing apparatus for recording and reproducing data on an optical disc.
The EFM signal from the recording data generation unit (EFM signal output) is transferred to the data playback unit within the signal processing circuit (CD-DSP 9)), and playback processing is performed on the transferred EFM signal, so that This is a configuration (signal processing circuit ST1 in FIG. 2) for performing a test of whether or not recording data can be generated (“whether there is no C1 error or C2 error by an LSI tester”).

  The above configuration is illustrated in FIGS. 1A, 1B, and 2, for example. In this configuration, the recording data (EFM data) generated using the built-in SRAM (CIRC arithmetic SRAM 6) is transferred to the data reproducing unit inside the circuit, and the data is reproduced.

  In this way, the signal processing circuit SТ1 only receives the initial setting information from the LSI tester, and generates recording data with the clock generated by the PLL (not shown) inside the signal processing circuit SТ1, and the data Can be played back, and can be tested for abnormalities and operating at the actual operating speed without being restricted by the upper limit frequency of the LSI tester.

The invention according to claim 2 is the signal processing circuit of the optical disc recording / reproducing apparatus according to claim 1,
A configuration (signal processing circuit ST2 in FIG. 3) includes a circuit (input data generation unit 10 in FIG. 3) for inputting data that is the basis of the recording data.

The above configuration is illustrated in FIG. 3, for example. According to the first aspect, since the internal PLL generates the clock, it is not necessary to supply the clock, but the data (data input from the host in actual use) that generates the recording data is external (in the test at the time of product shipment). LSI tester).
Accordingly, the invention according to claim 2 has the input data generation unit 10 inside the signal processing circuit ST2, and the data is input from the input data generation unit 10, thereby eliminating the need for external data input.

In addition, the built-in SRAM and the signal processing circuit have a data dependency on such a malfunction that causes a malfunction only when a specific data pattern is processed.
Therefore, by making it possible to arbitrarily set the data input by the input data generation unit 10, it is possible to perform test selection at the time of product shipment of the built-in SRAM or signal processing circuit having data dependency on the defect.

According to a third aspect of the present invention, in the signal processing circuit of the optical disc recording / reproducing apparatus according to the first aspect,
A configuration (circuit processing circuit ST4 in FIG. 5) including a circuit for determining whether or not the data after the reproduction processing is correct data is provided.

The above configuration is illustrated in FIG. 5, for example.
According to the first and second aspects of the invention, it is possible to determine whether the product is non-defective or defective by test selection, but it is not possible to know where in the data the error is.

Therefore, the present invention causes the data comparator 11 to store and determine the correct value of the error-corrected data of the CD-DSP 9 corresponding to the input data, resulting in an error that was not possible in claims 1 and 2. Data location can be specified.
In this way, not only test selection but also evaluation / analysis of defective products based on error location data can be performed.

  According to the first aspect of the present invention, the CD-DSP performs data reproduction processing on the EFM signal generated by the recording data generation processing and observes the C1 error and the C2 error from the outside. There is no need to supply a clock from the LSI tester in the selection by the tester, the signal processing circuit (signal processing circuit ST1) can be operated at a speed at which it is actually used, Test selection of the signal processing circuit becomes possible.

According to the second aspect of the present invention, since the input data to the signal processing circuit (signal processing circuit ST2) is supplied from the internal input data generation unit, no external data input is required, and the LSI at the time of product shipment Test selection at a speed that is actually used is possible without being restricted by the upper limit of the frequency of LSI testers.
In addition, by making it possible to arbitrarily select the input data, it is possible to cope with test selection of the built-in SRAM and the signal processing circuit that have data dependence on the malfunction symptoms.

  According to the third aspect of the invention, by having a portion for comparing the data after error correction of the CD-DSP and the data after error correction corresponding to the input data, not only the test selection but also the error location. It becomes possible to identify and evaluate / analyze malfunction symptoms.

[Embodiment]
1A and 1B are diagrams showing a basic configuration and a flow of data processing according to an embodiment of the present invention. FIG. 1A shows a case of recording data generation processing, and FIG. 1B shows a case of data reproduction processing. . Note that, in the case where the function is almost the same as that already described in FIG. 6, the reference numerals in FIG. 6 are shown in parentheses (for example, buffer manager 2 (109)).

  The signal processing circuit of the present embodiment includes a host interface 1 (111), a buffer manager 2 (109), a buffer RAM 3 (110), a sector processor 4 (function substantially equivalent to the CD-ROM / DVD Parity encoder 116), It comprises a CD interface 5, a CIRC operation SRAM 6 (115a), a CD encoder 7 (115), a strategy 8, and a CD-DSP 9 (function substantially equivalent to the CD / DVD decoder 107).

In the case of recording data generation processing, as shown in FIG. 1A, recording data input from a host (not shown) is transferred from the host interface 1 to the buffer RAM 3 via the buffer manager 2. .
The sector processor 4 reads the data in the buffer RAM 3 via the buffer manager 2, adds an error correction code, EDC code, SYNC code, header information, ID information, etc., and writes it back to the buffer RAM 3.

Further, the CD interface 5 reads out the data processed by the sector processor 4 from the buffer RAM 3 via the buffer manager 2 and writes it into the CIRC operation SRAM 6.
The CD / encoder 7 performs CIRC operation on the data in the CIRC operation SRAM 6, adds an error correction code and interleaves, performs EFM modulation on the operation-completed data, and transfers the data to the strategy 8.
The strategy 8 processes the EFM signal and outputs it to a laser control circuit (not shown) (117 in FIG. 6).

  In the case of data reproduction processing, as shown in FIG. 1B, a reproduction signal from a medium (optical disk) is input to the CD-DSP 9, and the CD-DSP 9 performs EFM demodulation and CIRC on the input data. Perform operations (deinterleaving, error correction). The CD interface 5 stores the processed data in the buffer RAM 3 via the buffer manager 2, and in order to further improve the reliability of the stored data, the sector processor 4 Perform error correction processing.

  Also in this case, data transfer to and from the buffer RAM 3 such as reading of stored data and data writing back by error correction is performed via the buffer manager 2. The data for which error correction processing has been completed as described above is transferred to the host via the buffer manager 2 by the host interface 1.

[About claim 1]
The invention of claim 1 will be described with reference to FIG. FIG. 2 is a block diagram of a signal processing circuit ST1 for explaining the invention of claim 1. In FIG.
The present invention transfers the EFM signal originally output to the laser control circuit (117 in FIG. 6) to the CD-DSP 9 in the configuration of FIG. 1 (signal processing circuit ST1), and the CD-DSP 9 reproduces data for the signal. It is characterized by performing processing.

  The signal processing circuit ST1 of the present invention has a CIRC operation SRAM 6 for data operation. The built-in SRAM 6 must be tested at the time of product shipment, but the SRAM 6 is generally tested independently of other circuits by providing a test circuit around the SRAM.

  Generally, the test circuit includes a circuit for enabling direct access to the built-in SRAM from an external pin, and a circuit for testing several types of fixed patterns written in the SRAM from the test circuit. However, the LSI tester must perform clock supply to the SRAM, write data input and output data correctness determination, and the upper limit value of the LSI tester frequency becomes the upper limit value of the SRAM test frequency.

  Also, as a method of testing the recording data generation process, it is common to create a function pattern that sets the clock supply, operating condition setting, and output expectation value from an LSI tester, and then tests using this function pattern. It is. Even in the test using the function pattern, the test cannot exceed the upper limit because of the restriction by the upper limit frequency of the LSI tester.

  On the other hand, in actual use, the built-in SRAM needs to operate at a speed corresponding to the recording speed on the medium. For example, when the recording speed to the medium is 48 times, the built-in SRAM needs to operate at about 206 MHz. However, the upper limit of the test frequency of the current LSI tester is generally about 100 MHz, and the test at the actual speed cannot be performed on the SRAM.

  Further, as the recording speed increases, the operation margin for the speed of the signal processing circuit decreases. However, the signal processing circuit cannot be tested at the actual speed due to restrictions of the LSI tester. As a result, SRAMs and signal processing circuits that do not have a speed margin and cause problems at high frequencies close to actual use cannot be tested at high frequencies, so they cannot be sorted out and shipped as good products. There is a risk of being.

Therefore, the present invention is characterized in that recording data generated using the built-in SRAM is transferred to the CD-DSP, and the CD-DSP performs data reproduction processing on the signal.
If the SRAM is defective or the signal processing circuit has no operating margin, appropriate recording data cannot be generated, and data playback processing is performed on the recording data that was not correctly generated. If this is done, the CD-DSP issues an error during the error correction process.

Information on errors in this CD-DSP error correction is written in a register in the CD-DSP. By observing the CD-DSP error correction register from the outside, it is possible to test the normal operation of the SRAM and signal processing circuit.
Also, the LSI tester gives initial values of the operation contents and conditions to this signal processing circuit. After that, after operating this signal processing circuit for an arbitrary time, whether or not the error correction of CD-DSP results in an error The LSI tester does not need to determine whether the output from the signal processing circuit is correct or not at a certain timing.

  Therefore, the signal processing circuit can operate based on the clock generated by the built-in PLL, and there is no need to supply the clock from the LSI tester. In other words, the signal processing circuit to be tested and the built-in SRAM can operate at a high frequency, that is, an actual use speed without being restricted by the test upper limit frequency of the LSI tester. The proper operation of the built-in SRAM can be tested.

  In the basic configuration described above (FIG. 1), the EFM signal output to the laser control circuit (not shown) is finally transferred to the CD-DSP 9 by the strategy 8 by the recording data generation process, and the CD-DSP 9 Data reproduction processing. At this time, if there is a defect in the built-in CIRC SRAM 6 or the signal processing circuit in the recording data generation process, an incorrect EFM signal is delivered to the CD-DSP 9.

  When the CD-DSP 9 performs data reproduction processing on the incorrect EFM signal, the CD-DSP 9 generates a C1 error or a C2 error during the error correction process. The C1 error is the result of error detection in the C1 sequence in the EFM signal received by the CD-DSP 9, and the C2 error is the error correction result of correcting the data after correction in the C1 sequence with the C2 sequence. It is.

  Information on these C1 error and C2 error is stored in a register in the CD-DSP 9. In an actual drive, the CD-DSP 9 may generate a C1 error and a C2 error as a result of a decrease in read quality due to factors other than the signal processing circuit such as a pickup and media, but in the configuration of the present invention, the strategy is Since the EFM signal output from the CD-ROM 9 is directly transferred to the CD-DSP 9, there is no cause for read quality degradation. If the CD-DSP 9 generates a C1 error or C2 error during the data playback process, Indicates that a problem has occurred.

  If this series of processes is performed at an actual speed, for example, 48 times the equivalent speed, it is possible to perform tests at high frequencies that could not be realized due to restrictions on the upper limit frequency of LSI testers, and SRAMs that cause problems with high frequency operation The signal processing circuit can be selected at the time of product shipment.

[About claim 2]
According to a second aspect of the present invention, in the circuit configuration shown in the first aspect (FIG. 2), there is provided a part for generating and inputting data that is the basis of the recording data.
The configuration of claim 2 (signal processing circuit ST2) is shown in FIG.
In actual use, the data that is the source of the recording data is input from the host to the signal processing circuit (signal processing circuit ST2) via the host interface 1. By providing the input data generation unit 10 instead of the host and inputting data from the input data generation unit 10 to the host interface 1, it is not necessary to supply input data from the outside of the control circuit.

  The input data generated by the input data generation unit 10 may be selected so that increment data, decrement data, 0, 1 fixed data, and the like can be generated. The reason is that if there is a defect in the built-in SRAM, it depends on the speed and depending on the data.

  Therefore, by having the input data generation unit 10 that can select the type of data as in this configuration, it becomes possible to input arbitrary data, and even if the built-in SRAM has a malfunction symptom depending on the data, the product is shipped. Test selection at the time becomes possible.

  3 shows the configuration of the signal processing circuit (signal processing circuit ST2) in which the buffer RAM 3 is built, but when the buffer RAM is not built in, the configuration shown in FIG. realizable.

  In the configuration of FIG. 3, the input data generated by the input data generation unit 10 has been input to the host interface 1, but as shown in FIG. Therefore, the present invention can be realized in a signal processing circuit that does not include the buffer RAM 3.

  Further, the host interface 1 or the CD interface 5 may be selected as the data input destination from the input data generation unit.

[Claim 3]
According to a third aspect of the present invention, in the circuit configuration shown in the first aspect of the invention, there is provided a part for determining whether or not the data for which the CD-DSP has finished error correction is correct.
The configuration (signal processing circuit ST4) is shown in FIG. FIG. 5 shows the configuration (signal processing circuit ST2) shown in FIG. 3 shown in the description of claim 2.

  Arbitrary arbitrary input data is input from the input data generation unit 10 to generate recording data. Thereafter, the CD-DSP 9 performs error correction in the data reproduction processing process, but the CD-DSP 9 corrects the error. The corresponding data corresponds to the input data.

For example, if the input data from the input data generation unit 10 is increment data, data corresponding to the one-to-one data will appear after the error correction of the CD-DSP 9.
Therefore, as shown in FIG. 5, a data comparison unit 11 is provided to input data after error correction of the CD-DSP 9. The data comparison unit 11 holds the correct data after error correction of the CD-DSP 9 corresponding one-to-one with the input data, and whether the held data is the same as the data actually input from the CD-DSP 9. Determine whether.

If it can be determined that the retained data and the input data from the CD-DSP 9 are the same, the recording data has been correctly generated. If it is determined that the holding data is not the same, there is some error in the recording data. This indicates that there is a problem with the built-in SRAM or signal processing circuit.
The data comparison unit 11 holds this determination result in an internal register. In the test at the time of product shipment, the test selection can be performed by observing the register holding value of the determination result from the LSI tester.

  Further, when determining that they are not the same, the difference between the data after error correction of the CD-DSP 9 and the correct data held by the data comparison unit 11 may be observed from the outside. By storing different data addresses and data in the register of the data comparison unit 11 and observing them from the outside, not only test selection at the time of product shipment but also evaluation / analysis of error symptoms can be performed. become.

2A and 2B are diagrams showing a basic configuration and a data processing flow of an embodiment to which the present invention is applied, in which FIG. 3A shows a case of recording data generation processing and FIG. 3B shows a case of data reproduction processing. It is a block diagram explaining the invention of claim 1. It is a block diagram explaining the invention of claim 2. FIG. 5 is a block diagram that can realize the invention of claim 2 even in a signal processing circuit that does not incorporate a buffer RAM; It is a block diagram explaining the invention of claim 3. It is a block diagram of the conventional optical disk recording / reproducing apparatus.

Explanation of symbols

ST1 to ST4 Signal processing circuit 1 Host interface 2 Buffer manager 3 Buffer RAM
4 Sector processor 5 CD interface 6 CIRC operation SRAM
7 CD / Encoder 8 Strategy 9 CD-DSP
DESCRIPTION OF SYMBOLS 10 Input data generation part 11 Data comparison part 100 Conventional optical disk recording / reproducing apparatus 100A Data reproduction circuit 100B Recording data generation circuit 101 Optical disk 102 Spindle motor 103 Motor driver 104 Servo controller 105 Optical pick-up 106 Read amplifier 107 CD / DVD decoder 108 CD- ROM / DVD error correction 109 Buffer manager 110 Buffer RAM
111 ATAPI / SCSI Host Interface 112 D / A Converter 113 ATIP / ADIP / LPP Decoder 114 Write Clock Generator 115 CD / DVD Encoder 116 CD-ROM / DVD Parity Encoder 117 Laser Control Circuit 118 CPU
119 ROM
120 RAM120

Claims (3)

In a signal processing circuit of an optical disc recording / reproducing apparatus for recording and reproducing data with respect to an optical disc,
The EFM signal from the recording data generation unit is transferred to the data reproduction unit within the signal processing circuit, and the reproduction processing is performed on the received EFM signal to test whether the recording data has been generated correctly. A signal processing circuit for an optical disk recording / reproducing apparatus. In the signal processing circuit of the optical disc recording / reproducing apparatus according to claim 1,
A signal processing circuit for an optical disc recording / reproducing apparatus, comprising a circuit for inputting data that is the source of the recording data. In the signal processing circuit of the optical disc recording / reproducing apparatus according to claim 1,
A signal processing circuit for an optical disc recording / reproducing apparatus, comprising: a circuit for determining whether or not the data after the reproduction process is correct data.

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