JP2005150644A - High frequency wiring structure, high frequency wiring structure forming method, and high frequency signal waveform shaping method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new wiring structure for a high frequency mounting substrate for mounting a VLSI or the like.
A wiring pattern constituting a transmission line through which a high-frequency signal is transmitted is composed of a plurality of segments S _{0 to} S ₁₁ having different characteristic impedances due to differences in shape. And determine the respective characteristic impedance Z ₀ to Z ₁₁ of a plurality of segments, to generate in two segments each other boundaries of the adjacent reflected waves to reduce the waveform distortion of the signal propagating through the transmission line.
[Selection] Figure 1

Description

  The present invention relates to a high-frequency wiring structure, a high-frequency mounting substrate using the high-frequency wiring structure, an integrated circuit and a high-frequency mounting substrate, a method for forming a high-frequency wiring structure, and a waveform shaping method for a high-frequency signal.

  As the internal signal speed of VLSI (very large scale integrated circuit) increases, the signal on the printed circuit board or ceramic substrate (high frequency mounting board) on which the VLSI is mounted needs to be increased in speed (high frequency). Recently, the frequency of a signal propagating on a transmission line of a high-frequency mounting circuit board is increasing from MHz to GHz. Due to such high speed, the electrical length (wavelength) of the high-frequency signal (frequency of 200 MHz or more) on the substrate is shorter than the average length of the wiring on the substrate. It must be designed as a transmission line. This point is described in Non-Patent Documents 1 and 2. When actually viewed as a transmission line, reflection noise occurs on the transmission line because there are mismatched portions of various characteristic impedances on the transmission line. As a result, waveform distortion occurs in the signal propagating through the wiring. Waveform distortion significantly degrades the signal quality. In particular, when these distortions occur in the clock signal, which is the most important signal, it often directly leads to a malfunction of a VLSI (very large scale integrated circuit). Therefore, it is necessary to keep the ideal signal quality with little distortion especially for the clock signal. As the frequency increases, waveform distortion becomes a cause of malfunction not only in clock signals but also in signals transmitted on the data bus and address bus.

The problem of waveform distortion caused by impedance mismatch is shown in FIG. Sent from VLSI signal (digital signal) is transmitted to the wiring of the characteristic impedance Z _0, it is terminated by the terminating resistor. Here, if the components such as VLSI or module wiring is connected, these components can be regarded as equivalent to the capacitive load C _L. These loads become impedance mismatch points on the wiring having a uniform characteristic impedance Z ₀ , and reflection noise is generated at this point. The reflected noise propagates while reflecting on the wiring, and this is superimposed on the digital signal to cause a large waveform distortion.

  Conventionally, for impedance matching of wiring on a substrate, a “load trace method” (Non-Patent Document 3) or a “Stub Series Terminated Logic Method” (Non-Patent Document 4) that adjusts impedance in the vicinity of an impedance mismatch point is used. I came.

As a conventional technique, a technique has been proposed in which an integrated circuit that generates a signal that cancels a reflected wave is added to a transmission line (Non-Patent Document 5).
Yuzo Sakurai, “High-speed transmission line design in the gigahertz era”, IEICE Technical Report FTS2001-34, Vol. 101, no. 475, pp. 21-28, issued in 2001 Hirokazu Toya, “A Wiring Design Method Suitable for High-Speed / Fine Processes and Considering Signals as Electromagnetic Waves”, Science (C), Vol. J85-C No. 3, PP. 117-124, issued in 2002 "High speed digital system design method" written by Norihiko Ueno and Yoshie Nakamura, published by Nikkei BP, 2001 “High-Speed, Small-Amplitude I / O Interface Circuits for Memory Bus Application” by Masao TAGUCHI, IEICE Trans. Electronics, Vol. E77-C, no. 12, pp. 1944-1950, published in 1994 Tamura Yasunori, Goto Kotaro, Saito Misato, Hariko Makoto, Wakayama Shigetoshi, Ogawa Shinji, Kato Koji, Taguchi Yasuo, and Imamura Kenji, “Equalization Technology for Inter-Chip High-Speed Signal Transmission”, Science Theory (C-II) , Vol. J82-C-II No. 5, PP. 239-246, 1999 and Information Processing Vol. 40, no. 8, pp. 795-800, published in 1999

  However, in the methods described in Non-Patent Documents 3 and 4 described above, since impedance is locally matched, it is difficult to completely eliminate reflection, and when there are many mismatch points, the reflected waves are superimposed on each other to generate a large signal. Deterioration may occur. In the technique described in Non-Patent Document 5, it is necessary to prepare a special integrated circuit.

  The speeding up of the signal will be indispensable in the future, and the higher the speed, the higher the frequency components with short electrical length. Therefore, waveform distortion due to impedance mismatching is further increased. Therefore, a new signal wiring structure capable of realizing high signal quality and a design method thereof (wiring structure forming method; waveform shaping method) are required.

  An object of the present invention is to provide a high-frequency wiring structure capable of reducing waveform distortion of a high-frequency signal, a high-frequency mounting substrate using the high-frequency wiring structure, an integrated circuit, a high-frequency mounting substrate, a method for forming a high-frequency wiring structure, and a high frequency The object is to provide a signal waveform shaping method.

  Another object of the present invention is to provide a new wiring structure for a high-frequency mounting board on which a VLSI or the like is mounted and a design method thereof.

  The present invention proposes a transmission line structure, that is, a high-frequency wiring structure, which divides a wiring pattern into a plurality of segments, thereby adjusting the impedance globally and canceling the reflected wave, instead of local adjustment as in the prior art. In the present specification, this transmission line is referred to as a segment transmission line (STL).

  First, the present invention aims to improve a high-frequency wiring structure including a wiring pattern that constitutes a transmission line through which a high-frequency signal (signal having a frequency of 200 MHz or more) is transmitted. In the present invention, the wiring pattern is constituted by a plurality of segments having different characteristic impedances due to differences in shape. The characteristic impedance of each of the plurality of segments is determined so that a reflected wave that reduces the waveform distortion of the signal propagating through the transmission line is generated at the boundary between two adjacent segments. The basic idea of the present invention is to reverse the idea of the conventional wiring design that has prevented the generation of reflected waves, and to actively generate reflection at the boundary between two adjacent segments of the transmission line. Is to reduce the waveform distortion of the signal. In other words, the technical idea of the present invention is that the waveform of the signal propagating through the transmission line is shaped by overlapping the characteristic impedance of each of the plurality of segments with the reflection noise generated at the boundary between the segments. It is to be determined as follows. In this way, it is possible to reduce the waveform distortion more reliably than the prior art by using only the shape of the wiring pattern without preparing a special integrated circuit or the like.

  The high-frequency wiring structure of the present invention can be applied to a high-frequency mounting substrate provided on an insulating substrate, but the high-frequency wiring structure of the present invention is adopted for a wiring pattern inside an integrated circuit such as a microprocessor. Of course, it is good. If the frequency of the signal is further increased, the problem of reflection naturally occurs even in the wiring pattern in the integrated circuit, but the present invention is effective even in the integrated circuit.

  The present invention is applied to a high frequency mounting substrate having a wiring pattern constituting a transmission line for transmitting a high frequency signal of 200 MHz or more on the surface of an insulating substrate and on which an integrated circuit electrically connected to the wiring pattern is mounted. In this case, the wiring pattern is composed of a plurality of segments with different characteristic impedances due to differences in shape, and the transmission lines are propagated by overlapping the characteristic impedance of each of the segments with the reflection noise generated in each segment. It may be determined that the waveform of the signal to be shaped is shaped.

  Here, the characteristic impedance of the segment can be set to a predetermined value by changing at least one of the width dimension, the length dimension, and the thickness dimension of the segment. In particular, when the characteristic impedance of the segment is set by changing the width dimension while keeping the length dimension of the segment constant, it is relatively easy to set the characteristic impedance.

  The method of the present invention is a method of forming a high-frequency wiring structure having a wiring pattern that constitutes a transmission line through which a high-frequency signal is transmitted, by a plurality of segments having different characteristic impedances due to different shapes. In the method of the present invention, an optimization algorithm such as a genetic algorithm is used to generate a reflected wave that reduces the waveform distortion of a signal propagating through a transmission line at the boundary between two adjacent segments (a plurality of segments). The characteristic impedance of each of the plurality of segments is designed so that the waveform of the signal propagating through the transmission line is shaped by overlapping the reflection noise generated in each segment. As an optimization algorithm applicable in the present invention, other known appropriate optimization algorithms can be used in addition to the genetic algorithm.

  Here, evolution calculations such as genetic algorithm and genetic programming, which are one of optimization algorithms, are described in the following documents (1) and (2). In recent years, attempts to use the techniques described in the following references (1) and (2) for hardware design have been actively reported within the framework of “evolutionary hardware” [below References (3), (4) and (5)]. Among them, there are some reports that apply GA and GP to circuit design [refer to the following documents (6), (7), (8)]. However, these are attempts to determine the values of circuit components such as transistors and capacitances so as to optimize the gain of the circuit, and are not related to the design of the transmission line. Also, Cheldavi et al. Use a genetic algorithm to determine the S parameter of the transmission line, which is a study on estimation of the S parameter of the transmission line whose structure is already known [Document (9) below] reference]. Therefore, the method using a conventionally known genetic algorithm is different in target structure from the transmission line divided into segments proposed in the invention, and its purpose and method are also different.

Reference (1): D. E. “Genetic Algorithms in Search Optimization” by Goldberg, Machining Learning, Addison-Wesley, 1989 (2): John R. “Genetic Programming” written by Koza on the Programming of Computers of Means of Natural Selection, MIT Press, 1992 (3): “Evolutionary hardware” information processing by Tetsuya Higuchi, Vol. 40, no. 8, pp. 795-800, 1999 publication (4): Hitomi Henmi and Takashi Gomi “Evolving hardware” IEICE Transactions, Vol. J84-C, No. 7, pp. 543-551, 2001 publication (5): “Special Issue on from Biology to Hardware and Bac” by Moshe Shipper and Daniel Mange, Eds, IEEE Trans. Evolutionary Computation, Vol. 3, No. 3, pp. 165-250.
Reference (6): Forrest H. et al. Bennett III, and John R. “Automatic Synthesis, Placement, and Routing of an Affiliate Circuit by Genetic Programming,” by Koza, Jessen Yu and William Mydlowec. Proc. Int'l Conf. Evolable Systems 2000 (ICES2000), pp. 1-10, Edinburgh, 2000 published (7): “A Note on Designing Logical Circuits Using SAT” by Giovanni Gomez Estrada, Proc. Int'l Conf. Evolable Systems 2003 (ICES 2003), pp. 410-421, Trondheim, 2003. Publication (8): “Circuit Design Using Evolution Algorithm” by Thomas Beelstein, Jan Dienstühl, Christian Feist and Marc Pompl. Congress on Evolutionary Computation 2003 (CEC 2003), CD-ROM, Honolul, 2003 Publications (9): “Modeling of Nonuniform Compiled Company of Ahmad CHELDVI and Gholamari REZAI-Rand. Fundamentals,
Vol. E83-A, no. 10, pp. 2023-2034, issued in 2000 The present invention can also be specified as a method of shaping a high-frequency signal by changing a high-frequency wiring structure including a wiring pattern that constitutes a transmission line through which a high-frequency signal is transmitted. Even in this case, the wiring pattern is composed of a plurality of segments having different characteristic impedances due to differences in shape, and the characteristic impedance of each of the plurality of segments is propagated through the transmission line by superimposing reflection noise generated in each segment. Determine to shape the waveform of the signal. Then, the shape of a plurality of segments may be designed using the genetic algorithm described above.

  According to the present invention, it is possible to obtain an advantage that waveform distortion can be reduced more reliably than in the prior art by using only the shape of a wiring pattern without preparing a special integrated circuit or the like.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, in the embodiment of the present invention, for example, a wiring pattern constituting a transmission line for transmitting a high frequency signal of 200 MHz or more is provided on the surface of an insulating substrate and electrically connected to the wiring pattern. The wiring pattern on the high-frequency mounting substrate on which the integrated circuit is mounted is divided into a plurality of segments S _{0 to} S ₁₁ . An independent characteristic impedance Z _i (Z _{0 to} Z ₁₁ ) is given to each segment S _{0 to} S ₁₁ . As a result, a mismatch point of characteristic impedance is generated at the boundary between two adjacent segments (the boundary between S ₀ and S ₁ , the boundary between S ₁ and S ₂ , etc.), and a reflected wave is generated. In this embodiment, the characteristic impedance of the reflected wave generated at each boundary, the capacitive load C _L reflected wave generated by also mutually superposed, including individual as cancel one another segment S ₀ to S ₁₁ Adjust Z _i (Z _{0 to} Z ₁₁ ). In other words, in this embodiment, the concept of conventional wiring design, which has been designed to prevent the generation of reflected waves, is reversed, and the waveform distortion is reduced by superimposing these at the boundaries of each segment. Let

Here, if the number of segments m, the value of possible characteristic impedance of each segment and n as capable throughout combination becomes as n ^m. For example, when the (1 [Omega increments in the range of 100Ω) m = 10, n = 100, becomes ways ^{100 10,} all test search becomes impossible. Therefore, in the embodiment, a genetic algorithm is applied to determine the characteristic impedance of each segment. As shown in FIG. 2, each characteristic impedance Z _{0 to} Z ₁₁ of the segmented transmission line can be directly mapped to a gene on an individual chromosome (Chromosome). Genetic manipulation can be applied. As will be described later, specifically, in addition to the characteristic impedance Z _i (Z _{0 to} Z ₁₁ ) of each segment S _{0 to} S ₁₁ , the transmission line termination resistance _RT and damping resistance R _O are also design parameters. Include these and map to genes.

After determining the characteristic impedance Z _i (Z _{0 to} Z ₁₁ ) of each segment S _{0 to} S ₁₁ , the shape of each segment is designed so as to realize Z _i . Specifically, the characteristic impedance Z _i is a function of the wiring width W _i , the thickness T _i , the insulator thickness D _i , and the relative dielectric constant ε _r of the substrate insulator (Z _i = f ( W _i , T _i , D _i , ε _r )). In practice, the thickness T _i and the insulator thickness D _i are generally constant (ie, T and D) for all wiring patterns on the substrate. Therefore, the characteristic impedance Z _i is realized by changing the width dimension W _i for each of the segments S _{0 to} S ₁₁ . FIG. 3 shows an example of a segmented transmission line intended for a microstrip line on a printed circuit board as a high frequency mounting circuit board. In FIG. 3, a plan view of the wiring pattern is shown in the upper stage, and a cross-sectional view of each part is shown individually in the lower stage. In the example of FIG. 3, the length L of each segment is equal. However, when the present invention is applied, the length L of the segment may be variable and the length may be different for each segment. In this case, since the propagation length of the reflected wave varies depending on the length L _{i of} each segment, it is necessary to determine the segment length L _i as a parameter similar to the characteristic impedance Z _i by a genetic algorithm.

Next, a segmented transmission line design support system will be described. In order to realize the method of the present invention, a design support system for a segmented transmission line was created. FIG. 4 shows the configuration of this system. In the present specification, the created design management program is called an STL designer, and this system is composed of this program and an existing electronic circuit simulator (SPICE). Here, the STL designer is responsible for the flow control of the entire segmented transmission line (STL) design, optimization calculation by genetic algorithm, activation of the electronic circuit simulator (SPICE), and OS [currently using Unix (registered trademark)] Run the interface with the shell. The electronic circuit simulator (SPICE) is an electronic circuit simulator which has been widely used all over the world since the start of development in the late 1960s. “Http://bwrc.eecs.berkeley.edu/Classes/IcBook/ "SPICE /" and "Resale Saleh, Takahide Inoue and Yukihiko Ido" Current status and future prospects of circuit simulators--Implementation issues based on expectations of simulators and overseas research trends "Science theory (A), Vol. -A No. 8, PP. 1188-1196, 1991 ”is described in detail. In addition, many experimental results on transmission lines using an electronic circuit simulator (SPICE) have been reported so far, and their high reliability is widely recognized. For example, “Hiroshi Hirose and Hiroto Yasuura's“ Bus Delay Reduction Method Considering Crosstalk ”, Theory of Science (A), Vol. J83-A No. 8, PP. 989-998, 2000”, “Tetsuro Endo” , Toshihiko Funaki, Hiroki Nakamura, Hiroshi Sakuraba and Fujio Tsujioka, “New Substrate Contact Type Pass Transistor”, Science Review (C), Vol. J84-C No. 3, PP. 192-198, 2001 ”and“ Sekine Toshikazu, Kunibayashi Kobayashi and Izumi Yokokawa, “Time-domain analysis of lossy heterogeneous lines using the FDTD method”, Science (A), Vol. J84-A No. 8, PP. There is a report in “Issuance of 2001”.

  The STL designer is a script written in the script language “perl”, and the electronic circuit simulator SPICE and the STL designer perform the following linking operations.

  1. The STL designer performs GA calculation (genetic operation) on circuit model parameters (characteristic impedance and termination resistance value of each segment of the segmented transmission line). The electronic circuit simulator (SPICE) is used for fitness evaluation in the GA calculation (genetic operation). Specifically, in a GA evaluation (fitness evaluation), a circuit description of a segmented transmission line including an input / output circuit is output as a file (circuit description file).

  2. After outputting the circuit description file, the STL designer activates the electronic circuit simulator (SPICE).

  3. The electronic circuit simulator (SPICE) reads a circuit description file, analyzes the circuit description file, and outputs the analysis result as a signal waveform result file (signal wave form file).

  4). The STL designer reads the signal waveform result file, calculates the fitness (fitness) based on the signal waveform result file, and continuously executes the GA calculation (genetic operation).

Next, genetic manipulation will be described. As shown in FIG. 3, each characteristic impedance (Z _{0 to} Z ₁₁ ) of the transmission line divided into segments can be directly mapped to an individual gene. By this mapping, crossover, mutation, and selection operations can be applied as they are without generating lethal genes.

The fitness function for fitness evaluation can be defined by “how close to an ideal transmission waveform”. That is, let I (t) be an ideal propagation waveform with ideal impedance matching (ideal wave form), R (t) be a propagation waveform (wave form under adjusting) to be shaped by the method of the present invention, and T Is the period,

Can be defined as

  FIG. 5 shows a relationship between an ideal transmission waveform (ideal wave form) and a transmission waveform (wave form under adjusting) to be shaped. Here, Diff is equal to the absolute value of the difference between I (t) and R (t) indicated by the hatched portion in FIG.

  Next, the segmented transmission lines were evaluated for actual printed circuit board wiring. A specific wiring system used is a clock supply wiring of DIMM (Dual In-line Memory Module) used in personal computers and the like. FIG. 6 shows a wiring system as a design object. In FIG. 6, a DIMM is a memory module that is mounted on a printed circuit board and constitutes a main memory. How wide a memory bandwidth can be supplied to the CPU greatly affects the system performance. Since the memory bandwidth is determined by the product of the transfer speed and the data width, it is necessary to supply a high-speed and high-quality clock signal in order to operate the DIMM at high speed. In order to propagate high-speed and high-quality signals on the substrate, it is necessary to realize an ideal transmission structure with less reflection. In the clock supply wiring system of the DIMM, the DIMM itself becomes an impedance mismatch point with respect to the transmission structure and causes waveform distortion. Although it is difficult to supply such an ideal clock signal with a current personal computer and the performance of the CPU clock frequency reaches several GHz, the clock signal speed on the board is about several hundred MHz. Stay on.

As shown in FIG. 6, in a normal clock signal supply system, a clock signal output from a clock driver passes through a damping resistor _RD and then passes through a transmission line on the substrate (clock line (Clock in the figure)). line)) and is terminated with a termination resistor _RT . The characteristic impedance Z ₀ of the transmission line is usually about 70Ω. In this evaluation experiment, Z ₀ = 76Ω was determined from the actual measured value of the wiring system.

  A clock signal pin (Clock In in the figure) of the DIMM is connected to this transmission line, and the clock signal is supplied from here to the DIMM. In a normal DIMM, there are two clock signal pins on one side of the DIMM, and FIG. 6 corresponds to this. In this evaluation object, the length of the transmission line is 10 cm. This length is a range of a typical clock signal wiring length (several centimeters to about 20 centimeters).

A circuit diagram for FIG. 6 is shown in FIG. The transmission line is divided into a plurality of segments, each having a different characteristic impedance Z _i (in this figure, an example in which the transmission line is divided into 10 segments Z ₁ to Z ₁₀ is shown). The DIMM is equivalent to the load capacitance C _l at the position of the clock signal pin, and in this evaluation, C _l = 10 pF from the actual measurement value. The clock driver is expressed as the signal source V and the internal resistance R _on.

The design goal is to obtain the characteristic impedance Z _i of each segment that realizes an ideal clock signal at the clock signal input points (observation points) P1 and P2, and the above-described “segment division transmission line design support system” is used. .

  The evaluation results will be described below.

[Experiment 1]
8 to 13 show the experimental results when the switching time (rise / fall) of the clock signal to be transmitted is 20 ps, the signal amplitude is 3.3 V, and the period is 10 ns. FIG. 8 shows an observation waveform in the basic matching wiring system at the observation point P1, and FIG. 9 shows an observation waveform in the basic matching wiring system at the observation point P2. FIG. 10 shows an observation waveform at the observation point P1 in the segment division transmission system, and FIG. 11 shows an observation waveform at the observation point P2 in the segment division transmission system. FIG. 12 shows an observation waveform at observation point 1 in the load trace system (conventional method), and FIG. 13 shows an observation waveform at observation point 2 in the load trace system (conventional method). Since the signal switching portion includes a high frequency component, a large reflection noise occurs due to this switching. In this experiment, a very short rise time (20 ps) was set to evaluate the effect of the segmented transmission line in this signal switching, and the clock frequency was as slow as 100 MHz. Note that the switching time 20 ps is shorter than the current clock signal switching time, but in the future, a 10 GHz class clock signal will be required in a VLIS (very large scale integrated circuit). However, GHz-class clock transmission is desired, and this value is sufficiently realistic to realize this requirement. The amplitude of the signal was 3.3 [V].

  8 and 9 are waveforms observed at observation points P1 and P2 when a DIMM is connected to the basic matching wiring system, respectively. Here, the basic matching wiring system is an ideal transmission system in which impedance matching is perfectly achieved when there is no load (when a load such as a DIMM is not connected). 8 and 9 also show the waveforms (ideal wave form in the figure) observed at the observation points P1 and P2 when only the basic matching wiring system (no load) is shown. In the case of only the basic matching wiring system, the clock signal propagates in an ideal waveform as it is without distortion. On the other hand, when a DIMM is connected to this basic matching wiring system, the DIMM becomes an impedance mismatch point, and reflection noise (reflection noise in the figure: reflection noise) is generated, resulting in a large distortion in the ideal waveform. Further, this waveform distortion causes a signal transmission delay (Delay in the figure).

  10 and 11 show observed waveforms at the observation points P1 and P2 by the segment division transmission line shown in FIG. For comparison, the ideal waveform (ideal wave form) shown in FIG. 8 is also shown. A slight transmission delay (Delay in the figure) and level oscillation are observed, but the delay time is about 200 ps (observation point P2), which is about 1/5 of the delay time in FIG. Further, the level of vibration is not so great as to cause malfunction, and almost ideal signal transmission is realized. Note that the number of GA individuals used for the design of this segmented transmission line is 10, and the result of evolution of about 300 generations was used.

Here, the fitness value obtained when the DIMM is connected to the basic matching wiring system (Z ₀ = 76Ω) with the fitness value according to the formulas (1) and (2) is represented as “ _original” , and the adaptation obtained by the segmented transmission line If the degree of improvement is f _STL and the improvement rate r _imp is defined as the ratio of both

It becomes. This improvement rate also shows that the signal quality of the transmission signal is greatly improved by the segmented transmission line.

12 and 13 show observed waveforms at the observation points P1 and P2 when using the load trace method that is a conventional technique (for comparison, the ideal waveform (ideal wave form) shown in FIG. 8 is also shown. ). Load tracing method, as shown in FIG. 14, to the connected load C _L in the transmission line (characteristic impedance Z _0), the characteristic impedance in the vicinity of the wiring locally adjusted (characteristic impedance Z ' change), is a technique to approximate the combined impedance of _{C L} and Z 'to _{Z 0.} Specifically, in this experiment, the transmission system shown in FIG. 15 was used. The length of the load trace the respective length 1cm either side of the C _l, its characteristic impedance Z 'is Z than matching calculation of characteristic impedance' was = 526Ω (details described in the Appendix). Here, it is difficult in the manufacturing process to realize a high impedance wiring such as Z ′ = 526Ω, and actually a wiring having a value of about 100 to 150Ω (as high as possible within a manufacturable range) is used. However, this theoretical calculation value Z ′ = 526 [Ω] was used for comparison this time. As described above, the other parameters Z ₀ , R _T , (R _on + R _D ) 76Ω were used. 12 and 13, the large reflection noise shown in FIG. 8 is eliminated, but the delay time (Delay) is increased, and a large vibration (Bounce Noise) of the signal level is observed. This is thought to be because the value of Z ′ became very large as a result of trying to eliminate the influence of the load C ₁ with the local impedance Z ′, and therefore the inductance became very high locally. Such local impedance matching is effective when the digital signal switching time is long, that is, when the frequency component in the signal switching is low. However, at high speed switching, the load trace portion becomes a distributed constant instead of a lumped constant, so that the effect is reduced as shown in this result.

Table 1 shows the results of the segmented transmission line obtained in this design. Table in wire width _{(transmission-line-width) W} i is the characteristic impedance _{Z i} and the wiring shape of the relation

Sought by. Here, D (= 140 mμ) and T (= 35 mμ) are the thickness of the insulator of the substrate and the thickness of the wiring, respectively (see FIG. 3). Ε _r (= 4.2) is the dielectric constant of the insulator.
[Experiment 2]
To assess the dependence of the signal switching time, it summarizes the results of the case of changing the rise time of the experiment 1 to t _{r =} 200 ps in Table 2. Also in this experiment, the improvement rate by the segmented transmission line is r _imp = 2.66, and a high effect is obtained.

As can be seen from the comparison between Table 1 in FIG. 16 and Table 2 in FIG. 17, the characteristic impedances Z _i of the corresponding segments are different. In particular, when the rise time is 20 ps, Z ₆ is 64Ω, which is the highest characteristic impedance value of all the segments (FIG. 16). On the other hand, when the rise time is 200 ps, Z ₆ is 22Ω, which is the lowest characteristic impedance value of all the segments (FIG. 16). This is because different reflection noises occur because the frequency components in the signal switching are different. The segmented transmission line is adapted to these different reflection noises, and an ideal transmission signal is realized by adjusting the characteristic impedance of each segment in each case.

[Experiment 3]
In Experiment 1 and Experiment 2, the experiment was conducted paying attention to the switching of signals that cause particularly large waveform distortion. For this reason, a slow value of 100 MHz was used for the clock frequency. In this experiment, the experiment was performed with the signal period (clock frequency) set to 500 MHz. The signal wavelength of 500 MHHz is almost equal to the transmission line length of 10 cm (FIG. 7). Therefore, it is considered that more multiple reflections occur than in Experiments 1 and 2. Therefore, in this experiment, the number of segments was set to 20, and the degree of freedom was further increased to cope with this (all other set values are the same as those in Experiment 2). The results are summarized in Table 3 in FIG. The waveforms observed at P1 are shown in FIGS. FIG. 18 shows an observed waveform (Wave Form under Capacitance) when a DIMM is connected to the basic matching wiring system and an ideal waveform (Ideal Wave Form) when there is no DIMM. It can be seen that due to the influence of the DIMM connection, a large reflection noise is generated, and the rectangular wave switching portion (rising and falling portions) is greatly scraped and distorted like a sine waveform. FIG. 19 shows a waveform (Wave Form under Capacitance) and an ideal waveform (Ideal Wave Form) of the segmented transmission line. It can be seen that the signal switching portion greatly cut out in FIG. 18 is improved and is shaped into a waveform that approaches the ideal waveform. Also in this experiment, r _imp = 2.13, and a good improvement effect is obtained.

  From the above experiment, it was found that the transmission waveform on the designed transmission line and the transmission waveform on the conventional transmission line were compared and evaluated, and the quality of the transmission waveform was improved more than twice, and an ideal transmission waveform was obtained.

The characteristic impedance Z ′ of the wiring is decomposed into a capacitance C ′ and an inductance L ′ as follows.

Here, t _pd is a transmission delay time determined by the dielectric constant of the insulator of the wiring board. The characteristic impedance of the connected load trace with load capacitance C _L can be calculated by C ′, L ′, t _pd and C _L , and this value is made equal to Z _0.

It is expressed. Thus, Z ′ = 526 [Ω] is obtained by substituting Z ₀ = 76Ω, C ′ = 10 [pF], and t _pd = 112 [ps].

It is a circuit diagram which shows the concept of a segment division | segmentation transmission line. It is a figure which shows the mapping on the chromosome of the characteristic impedance and resistance of the segment division | segmentation transmission line of FIG. It is a figure which shows the example of a segment division | segmentation transmission line. It is a figure which shows the structure of a segment division | segmentation transmission line design support system. It is a figure which shows the fitness value by the difference of a shaping object waveform and an ideal waveform. It is a figure which shows the structure of the memory module connected to the clock wiring on a printed circuit board. It is a figure which shows the circuit of FIG. It is a figure which shows the observation waveform in the basic matching wiring system in the observation point P1. It is a figure which shows the observation waveform in the basic matching wiring system in the observation point P2. It is a figure which shows the observation waveform in the observation point P1 in a segment division | segmentation transmission system. It is a figure which shows the observation waveform in the observation point P2 in a segment division | segmentation transmission system. It is a figure which shows the observation waveform in the observation point 1 in a load trace system (conventional method). It is a figure which shows the observation waveform in the observation point 2 in a load trace system (conventional method). It is a figure used in order to demonstrate the conventional impedance matching method (load trace method). It is a figure for demonstrating the design of the load trace with respect to a memory module type | system | group. 6 is a chart showing the results of Experiment 1. 6 is a chart showing the results of Experiment 2. It is a figure which shows the waveform of the observation point P1 of a basic matching wiring system. It is a figure which shows the waveform of the observation point P1 of a segment division | segmentation transmission system. 10 is a chart showing the results of Experiment 3. It is a figure which shows the relationship between the wiring on a very large-scale integrated circuit mounting board | substrate, and reflected noise.

Explanation of symbols

S _{0 to} S ₁₁ segment Z _{0 to} Z ₁₁ characteristic impedance R _T termination resistance R _O damping resistance

Claims (11)

A high-frequency wiring structure having a wiring pattern constituting a transmission line through which a high-frequency signal is transmitted,
The wiring pattern is composed of a plurality of segments having different characteristic impedances due to differences in shape,
The characteristic impedance of each of the plurality of segments is determined so that a reflected wave that reduces waveform distortion of the signal propagating through the transmission line is generated at a boundary between two adjacent segments. Wiring structure for high frequency. A high-frequency mounting substrate comprising the high-frequency wiring structure according to claim 1 on an insulating substrate. An integrated circuit comprising the high-frequency wiring structure according to claim 1 in an internal wiring pattern. A high-frequency mounting substrate that includes a wiring pattern that constitutes a transmission line that transmits a high-frequency signal of 200 MHz or more on the surface of an insulating substrate, and on which an integrated circuit that is electrically connected to the wiring pattern is mounted,
The wiring pattern is composed of a plurality of segments having different characteristic impedances due to differences in shape,
The characteristic impedance of each of the plurality of segments is determined such that a waveform of the signal propagating through the transmission line is shaped by overlapping reflection noise generated at the boundary of each segment. Mounting board for high frequency. The high frequency mounting substrate according to claim 4, wherein the characteristic impedance of the segment is set to a predetermined value by changing at least one of a width dimension, a length dimension, and a thickness dimension of the segment. The high-frequency mounting substrate according to claim 2, wherein the characteristic impedance of the segment is set by changing a width dimension of the segment with a constant length dimension. A method of forming a high-frequency wiring structure having a wiring pattern that constitutes a transmission line through which a high-frequency signal is transmitted, by a plurality of segments having different characteristic impedances due to differences in shape,
Using the optimization algorithm, the characteristic impedance of each of the plurality of segments is set such that a reflected wave that reduces waveform distortion of the signal propagating through the transmission line is generated at a boundary between two adjacent segments. A method for forming a high-frequency wiring structure characterized by designing. 8. The method of forming a high-frequency wiring structure according to claim 7, wherein the characteristic impedance is designed by designing the width dimension of the segment with the length dimension of the segment being constant. The method for forming a high-frequency intention line structure according to claim 7, wherein the optimization algorithm is a genetic algorithm. A method of shaping a waveform of the high-frequency signal by changing a high-frequency wiring structure having a wiring pattern that constitutes a transmission line for transmitting a high-frequency signal,
The wiring pattern is constituted by a plurality of segments having different characteristic impedances due to differences in shape,
The characteristic impedance of each of the plurality of segments is determined so as to shape the waveform of the high-frequency signal propagating through the transmission line by superimposing reflection noise generated in each segment. Method. The method for shaping a waveform of a high-frequency signal according to claim 10, wherein the shape of the plurality of segments is designed using an optimization algorithm.

Images