JP2005150565A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A step of planarizing an interlayer insulating film is eliminated in a semiconductor device having an STI structure and a manufacturing method thereof.
A silicon substrate, an STI3 embedded in a groove formed on the surface of the silicon substrate 1, and a gate in the groove formed on the surface of the silicon substrate 1 in a region surrounded by the STI3. A source comprising a gate electrode 7 formed through an insulating film 5 and an N-type low-concentration diffusion layer 9, an N-type high-concentration diffusion layer 11 and a silicide layer 13 formed on the silicon substrate 1 on both sides of the gate electrode 7. A region and a drain region are provided. The groove for the gate electrode 7 and the groove for the STI 3 are equal in depth, and both grooves are formed simultaneously. An insulating film 15 is formed on the STI 3 and the silicide layer 3, and the upper surface of the gate electrode 7 is formed at the same height as the insulating film 15.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a transistor is formed on a semiconductor substrate having an element isolation film (called STI (shallow trench isolation)) embedded in a groove formed on the surface of the semiconductor substrate. The present invention relates to a semiconductor device and a manufacturing method thereof.

Conventionally, in a semiconductor device, a gate electrode of a transistor is formed by forming a polysilicon thin film on a silicon substrate and selectively etching it. The source region and the drain region of the transistor are formed by implanting impurities in a self-aligned manner with respect to the gate electrode after forming the gate electrode. Further, in the fine process, in order to improve the transmission speed of the gate electrode, the source region, and the drain region, the surface portions of the gate electrode, the source region, and the drain region are silicided to reduce the resistance and improve the gate delay (for example, , See Patent Document 1).
In addition, there is a semiconductor device in which a trench is formed on the surface of a silicon substrate in an element isolation region and an STI is formed by embedding an oxide film in the trench (see, for example, Patent Document 2).

A conventional semiconductor device and a manufacturing method thereof will be described with reference to FIG.
(1) A trench for an element isolation film is formed on the surface of a P-type silicon substrate 41, and an STI 43 is formed by embedding an oxide film in the trench. After forming the gate insulating film 45 on the silicon substrate 41, a polysilicon film for the gate electrode is formed on the gate insulating film 45, and the polysilicon film is patterned by photolithography and etching techniques to form the gate electrode 47. Form. Using the gate electrode 47 as a mask, N-type impurity implantation is performed on the silicon substrate 41 to form an N-type low concentration diffusion layer 49 (see (a)).

(2) A sidewall spacer 51 made of an oxide film is formed on the side wall of the gate electrode 47. Using the gate electrode 47 and the spacer 51 as a mask, an N-type impurity is implanted into the silicon substrate 41 to form an N-type high concentration diffusion layer 53 (see (b)).

(3) Silicide layers 55 are respectively formed on the surface portions of the gate electrode 47 and the N-type high concentration diffusion layers 53 and 53 by a so-called salicide method in which silicon exposed portions are silicided in a self-aligned manner (see (c)). . The two sets of the N-type low concentration diffusion layer 49, the N-type high concentration diffusion layer 53, and the silicide layer 55 constitute a source region and a drain region.

(4) An interlayer insulating film 57 made of an oxide film is formed on the entire surface of the silicon substrate 41. A step is generated in the interlayer insulating film 57 due to the gate electrode 47 (see (d)).
(5) Since the step of the interlayer insulating film 57 becomes a problem in the upper wiring formation process, planarization is performed by applying CMP (chemical mechanical polishing) or the like. Thereafter, a contact hole 59 is formed in the interlayer insulating film 57 corresponding to the formation region of the gate electrode 47 and the N-type high concentration diffusion layers 43, 43, and tungsten 61 is buried in the contact hole 59 (see (e)).
Japanese Patent Laid-Open No. 2003-45888 JP 2003-289144 A

  As described above, in the prior art, since the gate electrode is provided on the silicon substrate, a step is generated in the interlayer insulating film due to the gate electrode. Therefore, a flattening process of the interlayer insulating film is necessary to eliminate the step. I was trying.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having an STI structure and a method for manufacturing the same, and a semiconductor device capable of reducing the number of manufacturing steps by eliminating the step of planarizing the interlayer insulating film, and a method for manufacturing the same. It is what.

  The semiconductor device of the present invention includes a semiconductor substrate, an element isolation film embedded in a groove formed on the surface of the semiconductor substrate, and a surface of the semiconductor substrate in a region surrounded by the element isolation film. A gate electrode formed through a gate insulating film in the formed groove, and a source region and a drain region formed on the semiconductor substrate on both sides of the gate electrode, and the gate electrode groove and the element isolation The depth of the groove for the film is equal. Here, the depth of the groove for the gate electrode and the groove for the element isolation film means that the two grooves are substantially equal, including the case where the depth differs due to oxidation treatment after the formation of both grooves. .

In the semiconductor device of the present invention, an example in which the material of the gate electrode is Cu (copper) can be given.
The source region and the drain region may be formed shallower than the gate electrode.
The source region and the drain region may be provided with a silicide layer on the surface portion.
The source region and the drain region may have a double diffusion structure including a low concentration diffusion layer and a high concentration diffusion layer formed shallower than the low concentration diffusion layer.

In addition, at least a nitride film and an interlayer insulating film are formed on the source region, the drain region, and the gate electrode, and the first connection hole, the source region, and the drain region are formed in the insulating film on the gate electrode. A second connection hole is formed in the upper insulating film, and a wiring groove is formed in the interlayer insulating film including a region where the first connection hole and the second connection hole are formed, and the first connection hole, the first connection hole, and the second connection hole are formed. The conductive material may be embedded in the two connection holes and the wiring groove. Here, an oxide film may be formed between the gate electrode and the nitride film. In that case, the insulating film on the gate electrode includes the oxide film. In addition, an oxide film may be formed between the source and drain regions and the nitride film. In that case, the insulating film over the source region and the drain region includes the oxide film.
Further, an example in which the conductive material embedded in the first connection hole, the second connection hole, and the wiring groove is Cu can be given.
Furthermore, the example which the said 1st connection hole and any one said 2nd connection hole are connected through the said groove | channel for wiring can be mentioned.

The method for manufacturing a semiconductor device of the present invention includes the following steps (A) to (E).
(A) forming a trench in the element isolation film formation scheduled region and the gate electrode formation scheduled region of the semiconductor substrate, and embedding an insulating material in the trench to form an element isolation film;
(B) forming a source region and a drain region in the semiconductor substrate on both sides of the gate electrode formation scheduled region;
(C) a step of selectively removing the element isolation film in the gate electrode formation scheduled region;
(D) forming a gate insulating film on the groove inner wall of the gate electrode formation scheduled region;
(E) A step of forming a gate electrode by embedding a gate electrode material in the trench in the region where the gate electrode is to be formed via the gate insulating film.

In the manufacturing method of the present invention, the step (E) includes an example in which Cu is used as the gate electrode material and the gate electrode is formed by a damascene method.
In the step (B), the source region and the drain region may be formed shallower than the trench in the region where the gate electrode is to be formed.
The step (B) may include a step of forming a silicide layer on the surface portions of the source region and the drain region.
The step (B) may include a step of forming a low concentration diffusion layer as the source region and the drain region and a high concentration diffusion layer shallower than the low concentration diffusion layer.

After the step (E), at least a nitride film and an interlayer insulating film are sequentially formed on the gate electrode, the source region, and the drain region, and a first connection hole is formed in the insulating film on the gate electrode. A wiring groove is formed in the interlayer insulating film including the second connection hole in the insulating film on the source region and the drain region, and the formation region of the first connection hole and the second connection hole. A step of embedding a conductive material in the connection hole, the second connection hole, and the wiring groove may be included.
Furthermore, the example which embeds Cu as said electrically-conductive material in the said 1st connection hole, the said 2nd connection hole, and the said groove | channel for wiring by the damascene method can be given.
Furthermore, when the wiring groove is formed in the interlayer insulating film, an example of forming a wiring groove for connecting the first connection hole and one of the second connection holes can be given.

In the semiconductor device of the present invention, the gate electrode is formed in the groove formed on the surface of the semiconductor substrate in the region surrounded by the element isolation film via the gate insulating film. Since the gate electrode is formed by embedding the gate electrode material in the trench of the electrode formation planned region via the gate insulating film, the height of the upper surface of the gate electrode and the insulating film around the surface of the semiconductor substrate or the gate electrode is the same. Accordingly, a step due to the gate electrode can be eliminated with respect to the insulating film above the gate electrode. Accordingly, since it is not necessary to perform a planarization process such as CMP on the insulating film above the gate electrode, the number of manufacturing steps can be reduced, and the process margin after forming the gate electrode can be increased.
Furthermore, in the semiconductor device of the present invention, the depth of the groove for the gate electrode and the groove for the element isolation film are equal, and in the manufacturing method of the present invention, the groove for the gate electrode and the groove for the element isolation film are formed simultaneously. The number of manufacturing steps can be reduced as compared with the case where the groove for the gate electrode and the groove for the element isolation film are formed separately.
Further, since the gate electrode is embedded, the prior art required a sufficient space between the gate electrode and the contact. However, in the present invention, this is not necessary, and the design rule can be reduced.
Furthermore, in the manufacturing method of the present invention, the source region and the drain region can be formed in a step before the gate electrode formation, and it is not necessary to limit the lateral diffusion when forming the source region and the drain region. Activation is possible.

  In the semiconductor device of the present invention, the material of the gate electrode is Cu, and in the manufacturing method of the present invention, if step (E) uses Cu as the gate electrode material and the gate electrode is formed by the damascene method, polysilicon, etc. Thus, it is possible to form a transistor having a gate electrode having a lower resistance and no gate delay than a gate electrode made of the above semiconductor material.

  In the semiconductor device of the present invention, the source region and the drain region are formed to be shallower than the gate electrode, and in the manufacturing method of the present invention, the step (B) includes the step of forming the source region and the drain region in the region where the gate electrode is to be formed. If it is formed shallowly, a margin for punch-through can be increased even when designed with the same area as compared with the conventional technique in which a gate electrode is formed on a substrate. Furthermore, since a channel can be formed also in the depth direction, a long gate length can be obtained even in the same area as compared with the prior art. Thereby, for example, the planar gate length can be reduced to the minimum value of pattern processing accuracy.

  In the semiconductor device of the present invention, the source region and the drain region are provided with a silicide layer on the surface portion, and in the manufacturing method of the present invention, the step (B) is a step of forming a silicide layer on the surface portion of the source region and the drain region. In this case, the resistance of the source region and the drain region can be reduced.

  In the semiconductor device of the present invention, the source region and the drain region have a double diffusion structure composed of a low-concentration diffusion layer and a high-concentration diffusion layer. In the manufacturing method of the present invention, the step (B) is a source region and a drain region. If the step of forming the low concentration diffusion layer and the high concentration diffusion layer is included, the breakdown voltage of the source region and the drain region can be improved.

  In the semiconductor device of the present invention, at least a nitride film and an interlayer insulating film are formed on the source region, the drain region, and the gate electrode, and the first connection hole, the source region, and the drain region are formed in the insulating film on the gate electrode. A second connection hole is formed in each of the insulating films, and a wiring groove is formed in the interlayer insulating film including a region where the first connection hole and the second connection hole are formed. The first connection hole, the second connection hole, and the wiring In the manufacturing method of the present invention, after the step (E) in the manufacturing method of the present invention, at least a nitride film and an interlayer insulating film are sequentially formed on the gate electrode, the source region, and the drain region so that the gate is formed. A first connection hole in the insulating film on the electrode, a second connection hole in the insulating film on the source region and the drain region, and a wiring groove in the interlayer insulating film including the formation region of the first connection hole and the second connection hole Forming the first connection hole By including a step of embedding a conductive material in the second connection hole and the wiring groove, a conventional technique of forming a connection hole in the interlayer insulating film and forming a wiring pattern on the interlayer insulating film (see, for example, Patent Document 2) .)), One more wiring layer can be secured. Further, in the semiconductor device of the present invention and the semiconductor device manufactured by the manufacturing method of the present invention, since the gate electrode and the element isolation film are embedded in the semiconductor substrate, the formation of the gate electrode, the element isolation film, the source region and the drain region is formed. Since the step on the surface of the semiconductor substrate including the region can be eliminated or reduced, the nitride film can be formed without lowering the coverage.

  Further, in the semiconductor device of the present invention, the conductive material embedded in the first connection hole, the second connection hole and the wiring groove is Cu, and the first connection hole and the second connection hole are formed by the damascene method in the manufacturing method of the present invention. If Cu as a conductive material is embedded in the wiring groove, the resistance can be reduced as compared with the conventional technique in which tungsten is embedded in the connection hole.

  Further, in the semiconductor device of the present invention, the first connection hole and any one of the second connection holes are connected via the wiring groove, and the wiring groove is formed in the interlayer insulating film in the manufacturing method of the present invention. When forming a wiring groove for connecting the first connection hole and any one of the second connection holes, the connection hole and the interlayer insulation formed in the interlayer insulating film as in the prior art. The gate electrode and the source or drain region can be short-circuited without using a wiring pattern formed on the film.

1A and 1B are diagrams illustrating an embodiment of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA in FIG. In (A), some insulating films are not shown.
An STI trench is formed on the surface of a P-type silicon substrate (semiconductor substrate) 1, and an insulating material such as an oxide film is buried in the trench to form STI3. A trench for a gate electrode formed at the same depth as the trench for STI 3 is formed on the surface of the silicon substrate 1 in a region surrounded by STI 3, and a conductive material, For example, Cu is embedded to form the gate electrode 7. The gate insulating film 5 is made of, for example, an oxide film having a thickness of about 10 to 100 Å (angstrom). A barrier metal layer (not shown) is formed between the gate insulating film 5 and the gate electrode 7.

  A source region and a drain region are formed in the silicon substrate 1 on both sides of the gate electrode 7. The source region and the drain region include an N-type low concentration diffusion layer 9 formed by introducing an N-type impurity, and an N-type high concentration diffusion layer 11 formed at a higher concentration and shallower than the N-type low concentration diffusion layer 9. It has a double diffusion structure consisting of The N-type low concentration diffusion layer 9 is formed shallower than the gate electrode 7, that is, the source region and the drain region are formed shallower than the gate electrode 7. Further, a silicide layer 13 is provided on the surface of the N-type high concentration diffusion layer 11. The thickness of the silicide layer 13 is, for example, 100 to 300 mm.

Except for the formation region of the gate electrode 7 and the gate insulating film 5, an insulating film 15 (not shown in (A)) is formed on the STI 3 and the silicide layer 13. The top surfaces of the gate electrode 7, the gate insulating film 5, and the insulating film 15 are the same and are formed flat. As the insulating film 15, a single layer film of an oxide film or a nitride film, a laminated film of an oxide film and a nitride film, or the like can be used. Here, a nitride film is used as the insulating film 15.
A nitride film 17 (not shown in (A)) is formed on the gate electrode 7, the gate insulating film 5, and the insulating film 15. The nitride film 17 functions as a CAP insulating film for preventing diffusion of Cu which is a material of the gate electrode 7. The thickness of the nitride film 17 is, for example, 50 to 200 mm.

An interlayer insulating film 19 (not shown in (A)) made of, for example, an oxide film is formed on the nitride film 17. A contact hole 21 is formed in the nitride film 17 and the interlayer insulating film 19 on the gate electrode 7 in a region different from between the source region and the drain region. Contact holes 23 are formed in the insulating film 15, the nitride film 17, and the interlayer insulating film 19 on the source region and the drain region, respectively. A conductive material, for example, tungsten 25 is embedded in the contact holes 21 and 23.
Although not shown, a wiring pattern, another interlayer insulating film on the upper layer side, a final protective film, and the like are formed above the interlayer insulating film 19.

FIG. 2 is a process cross-sectional view for explaining an embodiment of the manufacturing method. This embodiment will be described with reference to FIGS.
(1) Grooves are formed to a depth of, for example, 3000 to 8000 mm in the element isolation film formation planned region and the gate electrode formation planned region of the silicon substrate 1, and an STI 3 is formed by embedding an insulating material, for example, an oxide film in the trench. By ion implantation, an N-type impurity such as phosphorus or arsenic is finally diffused shallower than the depth of STI 3 in the silicon substrate 1 on both sides of the region where the gate electrode is to be formed. Here, phosphorus is 90 KeV, 1 × 10 ^12. Implantation is performed under conditions of about ˜1 × 10 ¹³ cm ⁻² to form the N-type low concentration diffusion layer 9 (see FIG. 2A). However, the ion implantation conditions are not limited to this. For example, the ion implantation conditions may be such that the N-type low concentration diffusion layer 9 is finally formed deeper than the STI 3.

(2) By ion implantation, an N-type impurity, for example, phosphorus or arsenic is implanted into the formation region of the N-type low-concentration diffusion layer 9 so that the concentration is higher than that of the N-type low-concentration diffusion layer 9 and the depth is shallower. The N-type high concentration diffusion layer 11 is formed shallower than the N-type low concentration diffusion layer 9 by implanting arsenic under the above conditions, here, about ¹⁵ KeV and 1 × 10 ¹⁵ cm ⁻² . A silicide layer 13 is formed to a thickness of 100 to 300 mm on the surface portion of the N-type high concentration diffusion layer 11 by the salicide method. Here, cobalt silicide was formed as the silicide layer 13. However, other metal materials such as titanium or tungsten may be used as the metal material for silicidation. An insulating film 15 made of a nitride film is formed on the entire surface of the silicon substrate 1 including the STI 3 and the silicide layer 13 by a CVD method to a thickness of about 200 to 300 mm (see FIG. 2B).

(3) A resist pattern 27 having an opening corresponding to the gate electrode formation scheduled region is formed on the insulating film 15 by photolithography and an insulating film in the gate electrode formation planned region using the resist pattern 27 as a mask by an etching technique. 15, the STI 3 and the silicide layer 13 are selectively removed to form a trench for the gate electrode (see FIG. 2C).
(4) A gate insulating film 5 made of an oxide film is formed on the inner wall of the gate electrode trench by a thermal oxidation method or a CVD method to a thickness of about 10 to 100 mm (see FIG. 2D).

(5) Cu is embedded in the trench for the gate electrode through the gate insulating film 5 by a so-called damascene method to form the gate electrode 7 (see FIG. 2E). Here, the description of the step of forming a barrier film formed between the gate insulating film 5 and the gate electrode 7 is omitted. In this embodiment, Cu is embedded in the trench as the conductive material for the gate electrode 7, but other materials such as tungsten may be used.
(6) In order to prevent diffusion of Cu which is a material of the gate electrode 7, a nitride film 17 is formed on the entire surface of the silicon substrate 1 including the gate electrode 7, the gate insulating film 5 and the insulating film 15 by CVD, for example. The film thickness is about 200 mm (see FIG. 2 (f)).

(7) An interlayer insulating film 19 made of an oxide film is formed on the nitride film 17 by, eg, CVD. Here, since the gate electrode 7 is formed by embedding Cu in the trench in the region where the gate electrode is to be formed through the gate insulating film 7 in the step (5), the interlayer insulating film 19 is caused by the gate electrode 7. Since there is no step, it is not necessary to perform a planarization process such as CMP, the number of manufacturing steps can be reduced, and the process margin after forming the gate electrode can be increased.
Contact holes 21 are formed in the nitride film 17 and the interlayer insulating film 19 on the gate electrode 7 by photolithography and etching techniques, and the insulating film 15, the nitride film 17 and the interlayer insulating film 19 on the source region and the drain region are formed. Contact holes 23 are respectively formed. Here, in the prior art, it was necessary to ensure a sufficient space between the gate electrode and the contact. However, in this embodiment, since the gate electrode 7 is embedded, it becomes unnecessary, so the design rule can be reduced. Can do.
After the contact holes 21 and 23 are formed, a conductive material such as tungsten 25 is embedded in the contact holes 21 and 23 (see FIG. 1).

In the above embodiment, the groove for the gate electrode 7 and the groove for STI 3 are formed at the same time, so the number of manufacturing steps is smaller than when the groove for gate electrode 7 and the groove for STI 3 are formed separately. can do.
Further, in the above embodiment, in the steps (1) and (2), the source region and the drain region are formed in a step prior to the formation of the gate electrode 7, so that the lateral region is formed when the source region and the drain region are formed. There is no need to limit the diffusion in the direction, and sufficient activation is possible.

Furthermore, since Cu is used as the material of the gate electrode 7, a transistor having the gate electrode 7 having a lower resistance and no gate delay than the gate electrode made of a semiconductor material such as polysilicon is realized.
Furthermore, since the source region and the drain region have the silicide layer 13 on the surface portion, the resistance of the source region and the drain region can be reduced.
Furthermore, since the source region and the drain region have a double diffusion structure including the N-type low concentration diffusion layer 9 and the N-type high concentration diffusion layer 11, the breakdown voltage of the source region and the drain region can be improved.

  Further, since the source region and the drain region are formed shallower than the gate electrode 7, a margin for punch-through is increased even when the same area is designed as compared with the conventional technique in which the gate electrode is formed on the substrate. Can do. Further, since the channel can be formed in the depth direction, a longer gate length can be obtained even in the same area as in the conventional technique. For example, the planar gate length can be reduced to the minimum value of pattern processing accuracy.

  In the above embodiment, the contact hole 21 for the gate electrode 7 is provided in a region different from that between the source region and the drain region. However, the contact hole 21 is provided on the gate electrode 7 between the source region and the drain region. Also good. In that case, the area occupied by the transistor on the chip can be further reduced.

  3A and 3B are diagrams showing another embodiment of the semiconductor device, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along the line BB in FIG. In (A), a part of the insulating film and Cu wiring are not shown. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

An STI 3 is formed on the surface of the silicon substrate 1. A groove for a gate electrode is formed on the surface of the silicon substrate 1 in a region surrounded by the STI 3, and a gate electrode 7 is formed in the groove via a gate insulating film 5. The silicon substrate 1 on both sides of the gate electrode 7 has a double diffusion structure including an N-type low concentration diffusion layer 9 and an N-type high concentration diffusion layer 11, and a silicide layer 13 is formed on the surface of the N-type high concentration diffusion layer 11. A source region and a drain region are formed.
An insulating film 15 is formed on the STI 3 and the silicide layer 13. A nitride film 17 and an interlayer insulating film 19 are formed on the gate electrode 7, the gate insulating film 5, and the insulating film 15.

A contact hole (first connection hole) 31 is formed in the nitride film 17 on the gate electrode 7, and a contact hole (second connection hole) 33 is formed in the insulating film 15 and the nitride film 17 on the silicide layer 13 in the source and drain regions. Is formed. A wiring trench 35 is formed in a region including the contact hole 31 and 33 formation region of the interlayer insulating film 19. The wiring groove 35 on the contact hole 31 on the gate electrode 7 and the wiring groove 35 on one of the source region and the drain region, for example, the contact hole 33 on the source region, are continuously formed. A conductive material such as Cu is embedded in the contact holes 31 and 33 and the wiring groove 35 to form a Cu wiring 37. The gate electrode 7 and the silicide layer 13 in the source region are electrically connected via a Cu wiring 37.
Although not shown in the drawing, in the upper layer than the interlayer insulating film 19 and the wiring pattern 37, another wiring pattern on the upper layer side, another interlayer insulating film on the upper layer side, a final protective film, and the like are formed.

FIG. 4 is a process sectional view for explaining another embodiment of the manufacturing method. This embodiment will be described with reference to FIGS.
(1) The STI 3, the gate insulating film 5, the gate electrode 7, the N-type low-concentration diffusion layer 9, the N-type are formed on the silicon substrate 1 by the same steps as the above-described steps (1) to (6) described with reference to FIG. A high concentration diffusion layer 11, a silicide layer 13, an insulating film 15 and a nitride film 17 are formed (see FIG. 4A).

(2) An interlayer insulating film 19 made of an oxide film is formed on the nitride film 17 by, eg, CVD. Here, similarly to the step (6) described with reference to FIG. 2, there is no step due to the gate electrode 7 with respect to the interlayer insulating film 19, so that it is not necessary to perform a planarization process such as CMP, and the manufacturing process. The number can be reduced, and the process margin after forming the gate electrode can be increased (see FIG. 4B).

(3) Contact holes 31 are formed in the nitride film 17 and interlayer insulating film 19 on the gate electrode 7 by photolithography and etching techniques, and the insulating film 15, nitride film 17 and interlayer insulation on the source region and the drain region are formed. Contact holes 33 are respectively formed in the film 19 (see FIG. 4C).

(4) A trench 35 for wiring is formed in a predetermined region of the interlayer insulating film 19 including the region where the contact holes 31 and 33 are formed by photolithography and etching. Here, the nitride film 17 functions as an etching stopper layer. In this embodiment, a wiring groove 35 on the contact hole 31 on the gate electrode 7 and a wiring groove 35 on the contact hole 33 on the source region are continuously formed (see FIG. 4D).

(5) Cu wiring 37 is formed by embedding Cu in the contact holes 31 and 33 and the wiring groove 35 by the damascene method. Thereby, the gate electrode 7 and the silicide layer 13 in the source region are electrically connected via the Cu wiring 37, and the Cu wiring 37 is connected to the silicide layer 13 in the drain region (see FIG. 3).

  In this embodiment, the contact holes 31 and 33 are formed in the insulating film 15 and the nitride film 17, and the Cu wiring 37 is formed in the interlayer insulating film 19. Therefore, the embodiment described with reference to Patent Document 2 and FIG. Compared to the example, one more wiring layer can be secured. Furthermore, since the gate electrode 7 and the STI 3 are embedded in the silicon substrate 1 and the level difference on the surface of the silicon substrate 1 is eliminated, the nitride film 17 can be formed without reducing the coverage.

  Furthermore, since Cu is embedded in the contact holes 31 and 33, the resistance can be reduced as compared with the conventional technique in which tungsten is embedded in the contact holes. Further, since the same material (Cu) is used for the conductive material in the contact holes 31 and 33 and the material of the Cu wiring 37, the contact resistance can be eliminated.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made within the scope of the present invention described in the claims.
For example, in the above embodiment, the present invention is applied to an N-channel transistor, but the present invention is not limited to this, and can be applied to a P-channel transistor.

In the above embodiment, the source region and the drain region are formed with a double diffusion structure. However, the present invention is not limited to this, and the source region and the drain region are formed with a single diffusion layer. May be.
In the above embodiment, the silicide layers are formed on the surface portions of the source region and the drain region. However, the present invention is not limited to this, and the silicide layers are not necessarily formed on the surface portions of the source region and the drain region. It does not have to be formed.

In the embodiment described with reference to FIGS. 3 and 4, the wiring groove 35 is formed so as to short-circuit the gate electrode 7 and the source region by the Cu wiring 37, but the present invention is not limited to this. For example, a wiring groove is formed so as to short-circuit the gate electrode and the drain region, or the potential is guided to a desired region without short-circuiting the gate electrode, the source region and the drain region. A wiring groove can be formed in a desired region.
In the embodiment described with reference to FIGS. 3 and 4, Cu is used as the wiring material. However, the present invention is not limited to this, and for example, tungsten may be used as the wiring material.

  In the embodiment of the manufacturing method described with reference to FIG. 4, the gate electrode 7 and the source region are short-circuited by the wiring groove Cu wiring 37 after the formation of the contact holes 31 and 33 (step (3)). However, the present invention is not limited to this. For example, the wiring groove 35 may be formed so as to short-circuit the gate electrode and the drain region, or the gate electrode, the source region, and the drain. A wiring groove can be formed in a desired region, for example, by leading those potentials to a desired region without short-circuiting the region.

1A and 1B are diagrams illustrating an example of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA in FIG. It is process sectional drawing for demonstrating one Example of a manufacturing method. It is a figure which shows the other Example of a semiconductor device, (A) is a top view, (B) is sectional drawing in the BB position of (A). It is process sectional drawing for demonstrating the other Example of the manufacturing method. It is process sectional drawing for demonstrating the conventional semiconductor device and its manufacturing method.

Explanation of symbols

1 Silicon substrate 3 STI
5 Gate insulating film 7 Gate electrode 9 N-type low concentration diffusion layer 11 N-type high concentration diffusion layer 13 Silicide layer 15 Insulating film 17 Nitride film 19 Interlayer insulating films 21 and 23 Contact hole 25 Tungsten 27 Resist pattern 31 and 33 Contact hole 35 Wiring groove 37 Cu wiring

Claims (16)

  A semiconductor substrate, an element isolation film embedded in a groove formed on the surface of the semiconductor substrate, and a gate in the groove formed on the surface of the semiconductor substrate in a region surrounded by the element isolation film A gate electrode formed through an insulating film; and a source region and a drain region formed in the semiconductor substrate on both sides of the gate electrode; and the depth of the groove for the gate electrode and the groove for the element isolation film Semiconductor devices with equal   The semiconductor device according to claim 1, wherein a material of the gate electrode is Cu.   The semiconductor device according to claim 1, wherein the source region and the drain region are formed shallower than the gate electrode.   The semiconductor device according to claim 1, wherein the source region and the drain region have a silicide layer on a surface portion.   The said source region and the said drain region are equipped with the double diffused structure which consists of a high concentration diffusion layer formed shallower than the low concentration diffusion layer and the said low concentration diffusion layer. Semiconductor device.   At least a nitride film and an interlayer insulating film are formed on the source region, the drain region, and the gate electrode, and a first connection hole, a source region, and a drain region are formed in the insulating film on the gate electrode. A second connection hole is formed in each of the insulating films, and a wiring trench is formed in the interlayer insulating film including a region where the first connection hole and the second connection hole are formed, and the first connection hole and the second connection hole are formed. 6. The semiconductor device according to claim 1, wherein a conductive material is embedded in the connection hole and the wiring groove.   The semiconductor device according to claim 6, wherein the conductive material embedded in the first connection hole, the second connection hole, and the wiring groove is Cu.   The semiconductor device according to claim 6 or 7, wherein the first connection hole and one of the second connection holes are connected via the wiring groove. A manufacturing method of a semiconductor device including the following steps (A) to (E).
(A) forming a trench in the element isolation film formation scheduled region and the gate electrode formation scheduled region of the semiconductor substrate, and embedding an insulating material in the trench to form an element isolation film;
(B) forming a source region and a drain region in the semiconductor substrate on both sides of the gate electrode formation scheduled region;
(C) a step of selectively removing the element isolation film in the gate electrode formation scheduled region;
(D) forming a gate insulating film on the groove inner wall of the gate electrode formation scheduled region;
(E) A step of forming a gate electrode by embedding a gate electrode material in the trench in the region where the gate electrode is to be formed via the gate insulating film.   The manufacturing method according to claim 9, wherein the step (E) uses Cu as the gate electrode material and forms the gate electrode by a damascene method.   11. The manufacturing method according to claim 9, wherein in the step (B), the source region and the drain region are formed shallower than a groove in the gate electrode formation scheduled region.   The manufacturing method according to claim 9, wherein the step (B) includes a step of forming a silicide layer on a surface portion of the source region and the drain region.   13. The step (B) includes a step of forming a low concentration diffusion layer as the source region and the drain region and a high concentration diffusion layer shallower than the low concentration diffusion layer. The manufacturing method as described.   After the step (E), at least a nitride film and an interlayer insulating film are sequentially formed on the gate electrode, the source region, and the drain region, and a first connection hole and the source are formed in the insulating film on the gate electrode. Forming a second connection hole in the insulating film on the region and the drain region; and forming a wiring groove in the interlayer insulating film including a region where the first connection hole and the second connection hole are formed; The manufacturing method according to claim 9, further comprising a step of embedding a conductive material in the second connection hole and the wiring groove.   The manufacturing method according to claim 14, wherein Cu as the conductive material is embedded in the first connection hole, the second connection hole, and the wiring groove by a damascene method.   The manufacturing method according to claim 14, wherein when forming the wiring groove in the interlayer insulating film, a wiring groove for connecting the first connection hole and one of the second connection holes is formed.

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