JP2005149768A - TFT array inspection method and TFT array inspection apparatus - Google Patents

Abstract

Data line defects and TFT internal circuit defect defects are detected.
SOLUTION: Very small parasitic capacitances (Cp1 to Cp3) exist between the organic EL electrode 10 and the surrounding wirings 21 to 23 and the electrodes. By applying a pulse signal at an appropriate timing to each of the scan signal line 22, the data line 21, and the power supply line 23, information on the voltage Vdd of the power supply line 23 can be obtained between the organic EL electrode 10 and the surrounding wiring or between electrodes. The organic EL electrode is held by the parasitic capacitance. In the normal pixel of the TFT array, the voltage of the organic EL electrode generated by the applied voltage Vdd is held by the parasitic capacitance. This defective voltage is different from that of a normal pixel due to a circuit abnormality in a defective pixel. Defect detection is performed by reading the potential of the organic EL electrode at this time as potential information, and an array inspection of the organic EL TFT array is performed.
[Selection] Figure 3

Description

  The present invention relates to a TFT array inspection apparatus used for inspecting a TFT array substrate used in a liquid crystal display, an organic EL display, or the like.

  An electron beam method and an optical method are known as TFT array inspection devices. In this conventional TFT array inspection device, a TFT array defect is detected by measuring the potential state of the TFT substrate obtained by irradiating the TFT substrate with an electron beam or light and detecting pixels having abnormal potentials on the TFT substrate. To do. Examples of TFT array inspection apparatuses using electron beams include Patent Documents 1 and 2, and examples of TFT array inspection apparatuses using light include Patent Documents 3 and 4.

FIG. 14 shows a configuration example of a driving circuit of a conventional active matrix type liquid crystal TFT array. The configuration example of FIG. 14 includes a liquid crystal electrode 100 made of an ITO electrode and a drive circuit 101, and the drive circuit 101 includes an output FET 102 (Q ₀ ) and a holding capacitor 103. The source and gate of the output FET 102 (Q ₀ ) are connected to the data line 121 and the scan signal line 122, respectively, and the drain is connected to the holding capacitor 103. A voltage held in the holding capacitor 103 is applied to the liquid crystal electrode 100.
There are two data signals and scan signals as input signals for the liquid crystal TFT array. Here, the scan signal is a signal on the scan signal lines 122 of the TFT array, a gate electrode of the output FET 102 (MOSFET) in each pixel described as _{Q 0} gate.

When _{Q 0} gate of the output FET102 is a p-channel MOSFET, when L-level pulses to the _{Q 0} gate is applied, the data signal from the data line 121 is held in the holding capacitor 103, the voltage is for a liquid crystal It is applied to the electrode 100 (for example, ITO electrode).
For example, if a certain TFT pixel is defective, the data signal cannot be accurately applied to the liquid crystal electrode of the pixel. That is, a voltage different from the intended voltage is applied to the liquid crystal electrode of the defective pixel. Similarly, even if there is a defect in the scan signal line 122 or the data line 121, it is detected as a defect.

  In the TFT array inspection for liquid crystal, a scan signal (FIG. 15A) and a data signal (FIG. 15B) having a voltage pattern as shown in FIG. 15 are applied, and the potential of the liquid crystal electrode at that time is measured. Then, a defect inspection is performed by detecting a liquid crystal electrode exhibiting an abnormal potential.

  Conventionally, defects are detected by applying a voltage on the data line and measuring an abnormal value of the potential of the liquid crystal electrode.

However, when the TFT array is an organic EL array, it is different from the case of the liquid crystal TFT array described above. As shown in FIG. 16, the liquid crystal TFT array is a voltage drive type that applies a constant voltage to the liquid crystal, whereas the organic EL array is a current drive type. In addition to the basic circuit configuration as in the embodiment of the present invention, the driving circuit for driving the organic EL array includes a current programming method, a voltage programming method, a time division method, an inverter method, etc. It is known that there is (Non-patent Document 1).
JP 2000-3142 A JP-A-11-265678 Japanese Patent No. 3994948 Japanese Patent No. 3275103 NIKKEI MICRODEVICE JULY 2003 July 1 issue p111-p118 Nikkei Business Publications, Inc.

  FIG. 17 is a configuration example of an organic EL drive circuit. The organic EL drive circuit has a drive method such as a current program method, a voltage program method, a time division method, an inverter method, etc., improved in this configuration example. The configuration example of FIG. 17 is shown as a representative example of these. .

  In the configuration of FIG. 17, the TFT array has two types of signal / control lines, a scan signal line and a data line, in addition to the power line of the EL driving TFT. In other driving systems, the operation and number of these signal / control lines are different, but the configuration of the data line for the luminance signal and the scan signal line for controlling the timing of each TFT cell are the same.

Similarly to the driving circuit for the TFT array for liquid crystal, the organic EL driving circuit 11 is a circuit in which the voltage corresponding to the voltage of the data line controls Q ₀ when the scan signal pulse is applied from the scan signal line 22. 13, and a voltage corresponding to the voltage is applied to the gate electrode 12 a of the output FET 12. Incidentally, it may not match the data signal, the data applied to Q _0, the voltage held in the Q _0.

  The organic EL is a current driving element (light emission is controlled by the amount of current passed), and the inspection is performed before the organic EL film is formed. In the completed organic EL display, the current flowing through the organic EL element 14 is controlled by the voltage of the gate electrode 12a. However, since the inspection is performed before the organic EL layer is formed, the organic EL drive circuit is in an incomplete state, and no current can flow through the output FET 12. The liquid crystal TFT array is also inspected before the step of producing the liquid crystal. However, in the case of the liquid crystal TFT array, the electrical operation does not change regardless of whether or not the liquid crystal is turned on.

  In general, as shown in FIG. 17, the organic EL TFT array has three input lines including a data line 21, a scan signal line 22, and a power supply line 23 (Vdd line). It becomes the structure which controls the electric current sent through the electrode 10 (for example, ITO electrode). The simplest circuit configuration of this configuration is shown in FIG. Hereinafter, the operation of the organic EL TFT circuit will be described with reference to FIG.

The data line 21 is connected to the source (or drain) of the control circuit 13 of Q ₀ , and at the moment when the pulse of the scan signal on the scan signal line 22 is applied, the data signal voltage at that time is applied to the holding capacitor 13 b. Retained. The holding capacitor 13 b is connected to the gate electrode 12 a of the output FET 12. In the completed circuit in which the organic EL is formed, the current flowing through the output FET 12 is controlled by the voltage of the holding capacitor 13b. However, the organic EL element 14 is not formed at the time of inspection. For this reason, the organic EL electrode 10 is in an open state. In this situation, when the output FET 12 is in the On state, a voltage equal to the voltage Vdd of the power supply line 23 is unconditionally applied to the organic EL electrode 10.

  Even when the output FET 12 is in the OFF state, the potential of the organic EL electrode 10 is finally the power supply line regardless of the data signal voltage because of a slight leakage current between the source and drain of the output FET 12. It becomes equal to the voltage Vdd.

  For this reason, for example, even when the FET 13a of the control circuit 13 is malfunctioning or the data signal is not normally applied, the malfunction state is hardly reflected in the potential of the organic EL electrode 10. In this state, even if there is no difference in the potential of the electrode for organic EL, there is a difference in the way the current flows after the formation of the organic EL layer, which becomes a defect.

  As described above, when the organic EL TFT array is inspected by simply applying a pulse to the data line and the scan signal line as has been done in the conventional liquid crystal inspection, the TFT circuit in the pixel is defective or the data line. This defect could not be detected.

  Regarding the power line defect, since the power supply voltage Vdd is connected to the organic EL electrode via the output FET, the power supply voltage Vdd signal is directly transmitted to the organic EL electrode 10, so that the conventional data signal is supplied to the power supply. Although it can be detected to some extent by the method applied to the line, sufficient defect inspection cannot be performed.

  Note that the above-described problem also exists in the drive method such as the current program method, the voltage program method, the time division method, and the inverter method.

  Accordingly, an object of the present invention is to detect data line defects and TFT internal circuit defect defects in an organic EL TFT array.

  A very small parasitic capacitance exists between the organic EL electrode and the surrounding wiring and electrodes. By applying a pulse signal at an appropriate timing to each of the scan signal line, data line, or power supply line for controlling the TFT array, information on the voltage Vdd of the power supply line is obtained from the organic EL electrode and the surrounding wiring or between the electrodes. The organic EL electrode is held by the parasitic capacitance.

  In the normal pixel of the TFT array, the voltage of the organic EL electrode generated by the applied voltage Vdd is held by the parasitic capacitance. This defective voltage is different from that of a normal pixel due to a circuit abnormality in a defective pixel. Defect detection is performed by reading the potential of the organic EL electrode at this time as potential information, and an array inspection of the organic EL TFT array is performed.

  The TFT array inspection method of the present invention includes a parasitic capacitance between an organic EL electrode on a TFT substrate and a wiring arranged around the organic EL electrode, or the parasitic capacitance and the organic EL electrode and the TFT substrate. A voltage is generated in the organic EL electrode via a parasitic capacitance with the drive circuit, and the defect of the array is inspected by measuring the potential of the organic EL electrode.

  One aspect of the array inspection of the present invention includes an organic EL electrode, a TFT substrate drive circuit, and a wiring including a power supply line, and a voltage is applied from the power supply line to the organic EL electrode. The step of setting to the first potential state and the application of the voltage from the power supply line to the organic EL electrode are stopped, and the organic EL electrode is set to the second potential by the parasitic capacitance between the organic EL electrode, the drive circuit, and the wiring. A step of changing the voltage of the power supply line to change the organic EL electrode to a third potential state by the parasitic capacitance, and a step of measuring the second potential state and / or the third potential state The defect inspection of the TFT array for organic EL is performed by this potential.

  The wiring includes signal and control lines such as a scan signal line and a data line of the TFT array in addition to the power supply line. An inspection signal of a predetermined pattern corresponding to the defect inspection item is applied to each line of the wiring, and the parasitic capacitance is determined. A voltage is generated, and the defect is inspected by measuring the potential of the organic EL electrode.

  The inspection signal can be a plurality of signal patterns. The first pattern of the inspection signal holds the first potential state of the organic EL electrode at the H level and turns off the output FET that controls the application of voltage from the power supply line to the organic EL electrode. The application of voltage to the electrode for electrode is stopped, the electrode for organic EL is set to the second potential state, the voltage of the power line of the output FET is changed to a voltage level lower than the H level, and the electrode for organic EL is set to the third potential. State.

  In the second pattern of the inspection signal, the first potential state of the organic EL electrode is held at the L level, and the output FET that controls the application of the voltage from the power supply line to the organic EL electrode is turned off. The voltage application to the electrode for electrode is stopped, the electrode for organic EL is set to the second potential state, the voltage of the power line of the output FET is changed to a voltage level higher than the L level, and the electrode for organic EL is set to the third potential. State.

  The third pattern of the inspection signal is an output FET that holds the first potential state of the organic EL electrode at an intermediate level between the H level and the L level and controls the application of voltage from the power supply line to the organic EL electrode. Is turned off, voltage application to the organic EL electrode is stopped, the organic EL electrode is set to the second potential state, the voltage of the power line of the output FET is changed to a voltage level lower than the intermediate level, and the organic EL The electrode is in the third potential state.

  The fourth pattern of the inspection signal is an output FET that holds the first potential state of the organic EL electrode at an intermediate level between the H level and the L level, and controls application of a voltage from the power supply line to the organic EL electrode. Is turned off to stop the voltage application to the organic EL electrode to bring the organic EL electrode to the second potential state, and the voltage of the power line of the output FET is changed to a voltage level higher than the intermediate level. The working electrode is set to the third potential state.

  The TFT array inspection apparatus of the present invention is an inspection apparatus for performing an array inspection of an organic EL TFT comprising an organic EL electrode, a TFT substrate drive circuit, and a wiring including a power supply line. Voltage measuring means for measuring the potential of the electrode, analysis means for performing defect analysis using the measured voltage, and inspection signal forming means for outputting an inspection signal to the wiring are provided. The inspection signal forming means applies a predetermined pattern inspection signal corresponding to the defect inspection item to each line of the wiring, and parasitic capacitance between the organic EL electrode and the wiring and between the organic EL electrode and the drive circuit. A voltage corresponding to the above is generated in the organic EL electrode, and the defect is inspected by measuring the potential of the organic EL electrode.

  In organic EL TFT arrays, TFT parasitic capacitance is used, and appropriate pulse signals are applied to signal / control lines, such as data lines and scan signal lines, and power supply lines, so that data line defects and TFT internal circuits Defective defects can also be detected.

  Hereinafter, the best mode for carrying out the invention will be described with reference to the drawings.

  FIG. 1 shows an example of a plan view of pixels in an organic EL TFT array. In this example, an example in which a p-channel MOSFET is used as the TFT will be described, but other types such as an n-channel MOSFET and a CMOS may be used.

  Each pixel includes an organic EL electrode 10 and a drive circuit 11, and wiring patterns 20 such as a data line 21, a power supply line 23, and a scan signal line 22 are wired around the pixel. A parasitic capacitance 30 exists between the organic EL electrode 10 and each wiring pattern 20 or drive circuit 11 as shown in FIG. Further, in a TFT, a relatively large capacitance generally exists between a gate and a source or between a gate and a drain. Here, as an example, let us consider the parasitic capacitance between each line of the data line and the power supply line and the organic EL electrode, and the gate-drain capacitance of the output FET. In practice, however, there may be other parasitic capacitances with the Gnd line and other circuit units.

  In consideration of the parasitic capacitance of the organic EL electrode 10 and the data line 21, power supply line 23, and scan signal line 22, the circuit of the organic EL TFT array shown in FIG. 16 can be rewritten as shown in FIG. it can. In FIG. 3, Cp1 to Cp3 indicate parasitic capacitances.

  In the circuit diagram of FIG. 3, when only the peripheral portion of the output FET 12 is represented by an equivalent circuit, FIG. 4 is obtained. In order to simplify the circuit, the operation of the output FET 12 is assumed to be an On / Off operation at the time of inspection, and is replaced with a switch controlled by a data signal and a scan signal of the output FET 12.

  Here, an example in which a p-channel enhancement type MOSFET having the characteristics as shown in FIG. 5 is used as the output FET 12 will be described. When the gate voltage with respect to the source voltage becomes lower than a certain threshold voltage Vr, the output FET 12 flows the current in the On state, and when the voltage is higher than the threshold voltage VT, the output FET 12 becomes the Off state. That is, in the output FET 12, the gate voltage is Off at the H level and On at the L level with respect to the source voltage. When the output FET 12 is in the On state, the potential of the organic EL electrode is equal to the voltage Vdd of the power supply line 23. While the gate voltage is changed from the H level to the L level, the output FET 12 is turned off at the gate voltage Vgate1 where Vgate1−Vdd = VT.

  The potential change of the organic EL electrode when changing from the On state to the Off state is approximately as follows. At the moment when the output FET 12 is turned off (the moment when the gate voltage becomes Vgate1), the potential of the organic EL electrode 10 is Vdd. However, when the gate voltage is increased thereafter, the organic FET is coupled by the gate-drain capacitance Cp2. The potential of the EL electrode 10 is lowered. Further, when the Vdd voltage and the data signal are changed thereafter, the potential of the organic EL electrode 10 is also changed by coupling with the respective lines by the capacitances Cp1 and Cp3.

で表される。 This operation is expressed as follows. The gate voltage at the moment when the output FET 12 is turned off is Vgate1, the voltage Vdd of the power supply line 23 is Vdd1, the voltage of the data line 21 is Vdata1, and after the output FET 12 is turned off, the gate voltage is Vgatet2. If Vdd is changed to Vdd2 and the data signal voltage is changed to Vdata2, the potential VEL of the organic EL electrode 10 at that time is expressed by the following equation (1) by capacitive coupling.

It is represented by

  Hereinafter, a defect inspection example of a TFT in such a circuit will be shown. FIG. 6 shows an example of applied signal patterns of the scan signal line 22, the data line 21, and the power supply line 23, and the gate voltage of the output FET 12 and the potential VEL of the organic EL electrode at that time in the defect inspection in the present invention. is there. In addition, the code | symbol of A-I in () has shown the code | symbol shown in FIG.

  When a pulse signal is applied to the gate of the TFT (B in FIG. 6A) with the data signal on the data line at the L level (A in FIG. 6B), the FET 13a is turned on at the pulse timing. The gate voltage of the output FET 12 becomes L level (C in FIG. 6A). As a result, the output FET 12 is turned on, and the potential VEL of the organic EL electrode 10 becomes equal to the power supply voltage Vdd ((D) in FIG. 6E).

  Thereafter, when a pulse is applied to the gate of the TFT with the data line at the H level ((E) in FIG. 6B) ((F) in FIG. 6B), the gate voltage of the output FET 12 is It becomes H level ((G) in FIG. 6B). At this time, since the output FET 12 is turned off at Vgate1, when the gate of the output FET 12 rises to the H level from the voltage, VEL slightly rises due to the parasitic capacitance Cp1 ((H) in FIG. 6E). ).

  Thereafter, when Vdd is changed from the H level to the L level while the output FET 12 is in the OFF state ((I) in FIG. 6D), VEL decreases due to capacitive coupling with the parasitic capacitance Cp3, and the Vdd H level and L It becomes an intermediate potential of the level ((J) in FIG. 6D).

  As described above, in the TFT circuit of a normal pixel, the VEL of the organic EL electrode 10 becomes an intermediate potential between the H level and the L level by applying the input pulse signal as described above to each wiring. On the other hand, when there is a defect, VEL becomes a potential different from the intermediate potential. For example, if there is a defect that is always in the On state due to a malfunction of the output FET, VEL becomes L level at the timing (J) in FIG. Will show different potentials. 7A and 7B are diagrams showing voltage waveforms of the organic EL electrodes. FIG. 7A shows a voltage waveform in the case of a normal pixel, and FIG. 7B shows a voltage waveform in the case of a defective pixel. Show. Such a constant On defect is a defect that occurs in the case of a short circuit between the source and drain of the output FET, a short circuit with the ground of the gate of the output FET, a short circuit with the ground line of the data line, or the like.

  Further, when the drain of the output FET is short-circuited with the ground line or the data line, VEL is equal to the voltage of the ground line or the data line, and is different from the intermediate potential of the normal pixel.

  Further, in a defect in which the output FET 12 is always in the OFF state, the VEL potential is determined by the ratio of the parasitic capacitances of Cp1 to Cp3, the application pattern of the Vdd voltage, the source-drain leakage current of the output FET, and the like. become. That is, as shown in FIG. 8, VEL gradually approaches Vdd if there is a slight leak even when the output FET is in the OFF state. The potential of VEL is determined by the time of H level and L level of Vdd and the parasitic capacitance ratio of Cp1 to Cp3. In this case, by applying a Vdd voltage pattern having an appropriate ratio between the H level time and the L level time, it is possible to make the VEL by the normal pixel and the VEL by the defective pixel different from each other. The defect can be detected from the difference in potential.

  As for other defects, those having a VEL potential different from that of a normal pixel can be detected.

  The example shown in FIG. 6 shows an example of changing the voltage Vdd of the output FET to L level after holding the H level signal in the organic EL electrode as the pulse voltage application pattern. Contrary to this example, the organic EL electrode is held at the L level and the voltage Vdd of the output FET is changed to the H level, or the organic EL electrode is intermediate between the L level and the H level. The applied pattern may be such that the potential is held and Vdd of the output FET is changed to a potential higher or lower than the intermediate potential.

  FIG. 9 is a signal diagram of an aspect in which the organic EL electrode is held at the L level and the voltage Vdd of the output FET is changed to the H level. By controlling the power supply voltage of the power supply line, the voltage of the organic EL electrode is held at L level ((K) in FIG. 9E), and the output FET gate is set to H level by setting the gate of the output FET to H level. When the voltage Vdd is changed from the L level to the H level while the output FET is in the off state, VEL is increased by the parasitic capacitance Cp1 by setting the voltage to the off state ((L) in FIG. 9E). VEL increases due to capacitive coupling with the capacitor Cp3, and becomes an intermediate potential between the H level and L level of Vdd ((M) in FIG. 9E).

  FIG. 10 is a signal diagram of a mode in which the organic EL electrode holds an intermediate potential between the L level and the H level, and the voltage Vdd of the output FET is changed to the L level. By controlling the power supply voltage of the power supply line, the voltage of the organic EL electrode is held at an intermediate potential between the L level and the H level ((N) in FIG. 10E), and the gate of the output FET is set to the H level. As a result, the output FET is turned off to raise VEL by the parasitic capacitance Cp1 ((O) in FIG. 10E). Thereafter, the output FET is turned off and the voltage Vdd is changed from the intermediate potential to the L level. VEL drops due to capacitive coupling with the parasitic capacitance Cp3, and becomes a potential lower than the intermediate potential between the H level and L level of Vdd ((P) in FIG. 10E).

  FIG. 11 is a signal diagram of an aspect in which the organic EL electrode holds an intermediate potential between the L level and the H level, and the voltage Vdd of the output FET is changed to the H level. By controlling the power supply voltage of the power supply line, the voltage of the organic EL electrode is held at an intermediate potential between the L level and the H level ((Q) in FIG. 11E), and the gate of the output FET is set to the H level. As a result, the output FET is turned off to raise VEL by the parasitic capacitance Cp1 ((R) in FIG. 11E), and then the output FET is turned off and the voltage Vdd is changed from the intermediate potential to the L level. VEL rises due to capacitive coupling with the parasitic capacitance Cp3, and becomes higher than the intermediate potential between the H level and L level of Vdd ((S) in FIG. 11E).

  FIG. 12 is a diagram for explaining a configuration example of the TFT array inspection apparatus of the present invention. The TFT array inspection apparatus 1 includes a measurement probe source 6 that irradiates a TFT substrate 2 to be inspected with a measurement probe such as an electron beam or light, a detector 7 that detects the potential of the TFT substrate 2, and inspection control. Means 3 are provided. The inspection control unit 3 controls an inspection signal forming unit 4 that applies an inspection signal to the TFT substrate 2 and an analysis unit 5 that performs defect inspection based on the measurement voltage.

  The TFT substrate 2 is an organic EL TFT including an organic EL electrode, a TFT substrate driving circuit, and a wiring including a power supply line, and the inspection signal forming means 4 includes a data line and a scan signal line in addition to the power supply line. An inspection signal having a predetermined pattern corresponding to the defect inspection item is applied to the wiring. The inspection signal pattern to be applied is selected by the inspection control means 3 according to the defect inspection item.

  The analysis unit 5 inspects the TFT array for defects by comparing the voltage acquired from the detector 7 with a voltage set in advance according to the defect inspection item.

  The TFT array inspection according to the present invention can also be applied to organic EL driving circuits using other driving methods. FIG. 13 is a diagram for explaining application of the TFT array inspection of the present invention to another driving method.

  FIG. 13A is a schematic example of an organic EL drive circuit based on a current programming method. In FIG. 13A, a voltage is generated in the organic EL electrode 10 by controlling the ON / OFF state of the output FET (T2) by the FETs T1, T3, and T4 and the power supply line, and the organic EL electrode An organic TFT array can be inspected by measuring 10 potentials.

  FIG. 13B is a schematic example of an organic EL drive circuit based on a voltage program method. In FIG. 13B, a voltage is generated in the organic EL electrode 10 by controlling the on / off state of the output FETs (T2, T4, etc.) by the FETs T1 and T3 and the power supply line (VDD). The organic TFT array can be inspected by measuring the potential of the organic EL electrode 10.

  FIG. 13C is a schematic example of an organic EL drive circuit based on a time division method. In FIG. 13C, a voltage is generated in the organic EL electrode 10 by controlling the on / off state of the output FETs (T1, T2) and the organic EL voltage supply line, and the potential of the organic EL electrode 10 is increased. The organic TFT array can be inspected by measuring.

It is a figure which shows the example of the top view of the pixel in the TFT array for organic EL of this invention. It is a figure for demonstrating the parasitic capacitance of the TFT array for organic EL of this invention. It is a figure which shows the structural example of the drive circuit for organic EL which considered the parasitic capacitance. It is an equivalent circuit diagram of the periphery of the output FET of the organic EL drive circuit. FIG. 6 is an operation characteristic diagram of an enhancement type p-channel MOSFET. It is a figure which shows the relationship between the applied signal pattern and generated voltage of the 1st aspect of this invention. . In this invention, it is a figure which shows the voltage waveform of the electrode for organic EL in a normal pixel and a defective pixel. In this invention, it is a figure which shows the voltage waveform of the FET for output by the always OFF defect. It is a figure which shows the relationship between the applied signal pattern and generated voltage of the 2nd aspect of this invention. It is a figure which shows the relationship between the applied signal pattern and generated voltage of the 3rd aspect of this invention. It is a figure which shows the relationship between the applied signal pattern and generated voltage of the 4th aspect of this invention. It is a figure for demonstrating one structural example of the TFT array test | inspection apparatus of this invention. It is a figure for demonstrating the application to the other drive system of the TFT array test | inspection of this invention. It is an example of a structure of the drive circuit of the conventional TFT array for active matrix system liquid crystals. It is an example of the applied voltage pattern to the scan signal line and data line of the TFT array for liquid crystal. It is a figure for demonstrating the voltage drive circuit of the TFT array for liquid crystals. It is a structural example of the drive circuit for organic EL. It is an example of a circuit of TFT array for organic EL.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... TFT array inspection apparatus, 2 ... TFT array, 3 ... Inspection control apparatus, 4 ... Inspection drive circuit, 5 ... Analysis means, 6 ... Inspection probe source, 7 ... Detector, 10 ... Electrode for organic EL, 11 ... Drive circuit, 12 ... output FET, 12a ... gate electrode, 13 ... control circuit, 13a ... FET, 13b ... holding capacitor, 14 ... organic EL element, 20 ... wiring, 21 ... data line, 22 ... scan signal line, 23 DESCRIPTION OF SYMBOLS ... Power supply line, 30 ... Parasitic capacitance, 100 ... Electrode for liquid crystal, 101 ... Drive circuit, 102 ... Output FET, 103 ... Holding capacitor, 121 ... Data line, 122 ... Scan signal line, 123 ... Power supply line.

Claims (8)

An inspection method for performing an array inspection of an organic EL TFT,
The parasitic capacitance between the organic EL electrode of the TFT substrate and the wiring arranged around the organic EL electrode, or the parasitic capacitance and the parasitic capacitance between the organic EL electrode and the driving circuit of the TFT substrate A TFT array inspection method comprising: inspecting a defect of an array by generating a voltage on an organic EL electrode through the electrode and measuring the potential. An inspection method for performing an array inspection of an organic EL TFT including an organic EL electrode, a TFT substrate driving circuit, and a wiring including a power supply line that supplies the TFT for current driving the organic EL,
(A) applying a voltage from the power supply line to the organic EL electrode to bring the organic EL electrode into a first potential state;
(B) A step of stopping the application of voltage from the power supply line to the organic EL electrode, and bringing the organic EL electrode into the second potential state by the parasitic capacitance between the organic EL electrode, the wiring, and the drive circuit. When,
Changing the voltage of the power line to bring the organic EL electrode into a third potential state by the parasitic capacitance;
(C) A TFT array inspection method comprising a step of measuring the second potential state and / or the third potential state, and performing a defect inspection of the organic EL TFT array using the potential. Measure the potential of the organic EL electrode by applying an inspection signal of a predetermined pattern according to the defect inspection item to each line of the wiring for applying a signal or voltage to the TFT array, generating a voltage according to the parasitic capacitance 3. The TFT array inspection method according to claim 1, wherein a defect inspection is performed. The inspection signal is
(A) holding the first potential state of the organic EL electrode at an H level;
(B) The output FET that controls the application of voltage from the power supply line to the organic EL electrode is turned off, the voltage application to the organic EL electrode is stopped, and the organic EL electrode is set to the second potential state.
4. The signal pattern according to claim 3, wherein the signal pattern is such that the voltage of the power line of the output FET is changed to a voltage level lower than the H level, and the organic EL electrode is in a third potential state. TFT array inspection method. The inspection signal is
(A) holding the first potential state of the organic EL electrode at an L level;
(B) The output FET that controls the application of voltage from the power supply line to the organic EL electrode is turned off, the voltage application to the organic EL electrode is stopped, and the organic EL electrode is set to the second potential state.
(C) The signal pattern of changing the voltage of the power line of the output FET to a voltage level higher than the L level to bring the organic EL electrode into a third potential state. TFT array inspection method. The inspection signal is
(A) holding the first potential state of the organic EL electrode at an intermediate level between the H level and the L level;
(B) The output FET that controls the application of voltage from the power supply line to the organic EL electrode is turned off, the voltage application to the organic EL electrode is stopped, and the organic EL electrode is set to the second potential state.
4. The signal pattern according to claim 3, wherein the signal pattern is such that the voltage of the power line of the output FET is changed to a voltage level lower than the intermediate level, and the organic EL electrode is in a third potential state. TFT array inspection method. The inspection signal is
(A) holding the first potential state of the organic EL electrode at an intermediate level between the H level and the L level;
(B) The output FET that controls the application of voltage from the power supply line to the organic EL electrode is turned off, the voltage application to the organic EL electrode is stopped, and the organic EL electrode is set to the second potential state.
(C) The signal pattern of changing the voltage of the power line of the output FET to a voltage level higher than the intermediate level and setting the organic EL electrode in a third potential state. TFT array inspection method. An inspection apparatus for performing an array inspection of an organic EL TFT comprising an organic EL electrode, a driving circuit for the TFT substrate, and a wiring including a power supply line,
Voltage measuring means for measuring the potential of the organic EL electrode;
Analysis means for performing defect analysis using the measurement voltage;
An inspection signal forming means for outputting an inspection signal to the wiring;
The inspection signal forming means applies an inspection signal of a predetermined pattern according to a defect inspection item to each line of the wiring, and parasitic between the organic EL electrode and the wiring and between the organic EL electrode and the drive circuit. A TFT array inspection apparatus characterized in that a voltage corresponding to a capacitance is generated on an organic EL electrode, and a defect inspection is performed by measuring a potential of the organic EL electrode.

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