JP2005142960A - Image reading device - Google Patents

Abstract

The present invention provides an image reading apparatus that appropriately secures a cross point of a clock to a photoelectric conversion means that photoelectrically converts reflected light from a document to improve image quality.
A composite apparatus 1 irradiates a document with reading light from a light source and introduces reflected light from the document into a three-line CCD sensor 16 by a scanning optical system. The image data is transferred by being driven by at least the shift drive clock, the final stage drive clock and the reset clock from 159, each clock is supplied from the timing circuit 153 to the CCD drive driver 159, and the final stage drive clock of the timing circuit 153 is supplied. The phase is adjusted by the CPU 150. At this time, the composite apparatus 1 checks the transfer efficiency of the image data, and the CPU 150 adjusts the phase of the final stage drive clock based on the transfer efficiency check result.
[Selection] FIG.

Description

  The present invention relates to an image reading apparatus, and more particularly to an image reading apparatus that appropriately secures a clock cross point to a photoelectric conversion unit that photoelectrically converts reflected light from a document to improve image quality.

  In general, an image reading apparatus irradiates a document from a light source, reflects light reflected by the document into a photoelectric conversion element such as a CCD (Charge Coupled Device), and performs photoelectric conversion by the photoelectric conversion element. The original image is being scanned.

  The CCD, which is a photoelectric conversion element, is driven by transfer clocks PH1 (φ1), PH2 (φ2), and PH2B (φ2B) from a drive circuit (driver), transfer clock φ1, transfer clock φ2, and final stage transfer clock φ2B. Are in opposite phase to each other, but the cross points of the transfer clock PH1 ↓ and the transfer clock PH2 ↑ and the transfer clock clock PH1 ↑ and the transfer clock PH2 ↓ are 1.5V to 2V or more, although the voltage level differs depending on the CCD. It is necessary to secure it. In the CCD, if this cross point cannot be secured, transfer efficiency decreases and charge advancement phenomenon (PRNU (photo response non-uniformity) deterioration) occurs.

  In addition, at the cross point of the transfer clock φ1 and the transfer clock φ2, each driver can ensure a cross point by setting and inputting the transfer clock φ1 and the transfer clock φ2 on the same driver. Even if the delay time is different when driven by a driver, the transfer clocks φ1 and φ2 of a plurality of terminals are connected to each other inside the CCD, and a cross point is secured as a whole.

  Similarly, the transfer clock φ1 and the transfer clock φ2B are in opposite phases. Further, the cross point condition of the transfer clock PH1 ↓ and the final stage transfer clock PH2B ↑ is the same as the above, but there is a CCD which does not have the cross point condition of the transfer clock PH1 ↑ and the final stage transfer clock PH2B ↓. In the case of such a CCD, by making the final stage transfer clock PH2B ↓ faster, the duty ratio of the clock 50:50 is destroyed, the pulse width is adjusted, and the L level of the final stage transfer clock PH2B is adjusted. The area can be widened, and the CCD output feedback can be widened.

  Since there is a crosspoint condition between the transfer clock PH1 ↓ and the final stage transfer clock PH2B ↑, if this crosspoint condition cannot be ensured, an abnormality occurs in the transfer efficiency, resulting in a decrease in transfer efficiency or a charge forward phenomenon. (Deterioration of PRNU) occurs.

  Conventionally, it has a photoelectric conversion element that converts image light into an analog electric signal, and means for sample-holding the analog electric signal, and at least the photoelectric conversion element and the sample-hold means are mounted on the same substrate, and the photoelectric conversion element There has been proposed an image reading apparatus in which a clock and a sample hold signal for determining the output timing are supplied through the same element (see Patent Document 1).

Japanese Patent Application Laid-Open No. 11-177783

  However, in the above prior art, the clock for determining the output timing of the photoelectric conversion element and the sample hold signal are supplied through the same element, but the cross point of the transfer clock is ensured accurately. Therefore, there is a need for improvement in order to improve transfer efficiency and prevent the occurrence of a charge advance phenomenon.

  Accordingly, the invention described in claim 1 irradiates the original with reading light from the light source, introduces the reflected light from the original into the photoelectric conversion means by the scanning optical system, and connects the photoelectric conversion means from the drive means. At least the shift drive clock, the final stage drive clock, and the reset clock are used to transfer image data, supply each clock from the timing signal generation means to the drive means, and the phase of the final stage drive clock of the timing signal generation means Is adjusted by the adjusting means, the transfer efficiency of the image data is inspected, and the adjusting means adjusts the phase of the final stage drive clock based on the inspection result of the transfer efficiency, thereby transferring the transfer clock and the final stage transfer. Properly secure the zero cross point with the clock to maintain the transfer efficiency, reduce the transfer efficiency, and charge forward (the deterioration of PRNU) The generation by preventing, it is an object to provide an image reading apparatus to improve image quality.

  According to a second aspect of the present invention, the timing signal generating means includes a register for setting the phase of the clock, and the adjusting means controls the setting of the phase of the clock to the register and supplies it to the photoelectric conversion means. By adjusting the phase of the drive clock, the clock phase setting control is performed by a register according to the delay variation between packages, the phase is individually adjusted, the phase is controlled by a controller such as a CPU, and the CCD, etc. The phase of the final stage drive clock, including the amount of variation in transfer efficiency of the photoelectric conversion means itself and the amount of variation in other components (resistors, capacitors, etc.), is set and controlled by a register, adjusted individually, and the delay between packages Even if there is a variation, it is possible to appropriately secure the cross point, further reducing the transfer efficiency and the charge postponement phenomenon (PRNU deterioration). Sincerely to prevent, it is an object to provide an image reading apparatus to further improve the image quality.

  According to a third aspect of the present invention, the photoelectric conversion means determines the output timing of the image data based on the final stage transfer clock and the reset clock, and the driving means has a plurality of package IC drivers and supplies them to the photoelectric conversion means. By driving the final stage transfer clock and the reset clock with the same package IC driver, the delay variation between packages is eliminated, the timing of the reset clock is optimized, the reset failure between solids is reduced, and the image quality is further improved. An object of the present invention is to provide an image reading apparatus.

  According to a fourth aspect of the present invention, the output timing of the photoelectric conversion means is determined by the final stage transfer clock, the reset clock, and the clamp clock, and the drive means has a plurality of package IC drivers and supplies them to the photoelectric conversion means. The final stage transfer clock, reset clock, and clamp clock are driven by the same package IC driver to eliminate delay variation between packages, and the clamp clock output from the drive means to the photoelectric conversion means by the clamp clock from the timing signal generating means It is an object of the present invention to provide an image reading apparatus that optimizes the timing of the above, prevents an increase / decrease in the clamping area between solids, secures a stable SN, and further improves the image quality.

  According to the fifth aspect of the invention, the driving means drives the photoelectric conversion means by using the final stage transfer clock and the clamp clock generated by the timing signal generating means in common, and thereby the variation between the two signals at the generation source. As a result, compared with the case where the final stage transfer clock and the clamp clock are not used in common, the effective clamp area is widened, the random noise is reduced, and a good SN is secured. An object of the present invention is to provide an image reading apparatus that further improves the quality.

  According to a sixth aspect of the present invention, the timing signal generating means includes a register for setting the clock phase, and the adjusting means controls the setting of the clock phase to the register and supplies the reset clock supplied to the photoelectric conversion means. By adjusting the phase, the reset region of the reset clock is removed from the effective clamp region, the pulse width of the reset clock is narrowed, the effective clamp region is further increased, random noise is reduced, and good SN is secured. In addition, an object of the present invention is to provide an image reading apparatus capable of setting and controlling the pulse width of a reset clock with a register so that it can be individually adjusted and controlled by a controller such as a CPU to further improve the image quality. It is said.

  According to the seventh aspect of the present invention, by using a CCD as a photoelectric conversion means, it is possible to use a reduction optical system, and a focal depth can be obtained so that a document float and a certain amount of three-dimensional object are read out of focus. An object of the present invention is to provide an image reading apparatus with good image quality that can be performed without causing it.

  The invention described in claim 8 uses a multi-line CCD such as a 3-line color CCD as the photoelectric conversion means, so that a transfer clock is required for each of the plurality of lines and a large number of drivers are required. Even when using a multi-line CCD that also requires a driver, it prevents the reading quality from degrading due to the crossing point variation, reset clock variation, and clamp clock variation, respectively. An object is to provide a reader.

  According to the ninth aspect of the present invention, the driving means has a plurality of package IC drivers for supplying a two-phase driving clock supplied to the photoelectric conversion means for each phase, and the two-phase driving clocks are supplied by the same package IC driver. An object of the present invention is to provide an image reading apparatus that ensures a cross point more reliably and further improves image quality by driving.

  According to the tenth aspect of the present invention, the drive means equalizes the phase adjustment amount of the final stage phase clock supplied to the photoelectric conversion means with the phase adjustment amount of the reset clock and the clamp clock, so that each timing at the time of high-speed operation is obtained. It is an object of the present invention to provide an image reading apparatus that appropriately takes the above and secures the cross point more reliably and further improves the image quality.

  The image reading apparatus according to the first aspect of the present invention irradiates the original with reading light from a light source, introduces reflected light from the original into the photoelectric conversion means by a scanning optical system, and causes the photoelectric conversion means to be driven means. Is driven by at least the shift drive clock, the final stage drive clock, and the reset clock from the image data, and the respective clocks are supplied from the timing signal generation means to the drive means, and the final stage drive of the timing signal generation means is performed. In the image reading apparatus that adjusts the phase of the clock by the adjusting means, the transfer efficiency of the image data is inspected, and the adjusting means adjusts the phase of the final stage drive clock based on the inspection result of the transfer efficiency. The above-mentioned purpose is achieved.

  In this case, for example, as described in claim 2, the timing signal generating means includes a register for setting the phase of the clock, and the adjusting means performs control for setting the phase of the clock to the register. The phase of the final stage drive clock supplied to the photoelectric conversion means may be adjusted.

  Further, for example, as described in claim 3, the photoelectric conversion means determines the output timing of image data by the final stage transfer clock and the reset clock, and the driving means has a plurality of package IC drivers. The final stage transfer clock and the reset clock supplied to the photoelectric conversion means may be driven by the same package IC driver.

  Further, for example, as described in claim 4, the photoelectric conversion means has an output timing determined by the final stage transfer clock, the reset clock and the clamp clock, and the driving means has a plurality of package IC drivers. The final stage transfer clock, the reset clock, and the clamp clock supplied to the photoelectric conversion means may be driven by the same package IC driver.

  Further, for example, as described in claim 5, the driving means drives the photoelectric conversion means by using the final stage transfer clock generated by the timing signal generating means and the clamp clock in common. There may be.

  Further, for example, as described in claim 6, the timing signal generation unit includes a register that sets the phase of the clock, and the adjustment unit performs setting control of the phase of the clock to the register, The phase of the reset clock supplied to the photoelectric conversion means may be adjusted.

  For example, as described in claim 7, the photoelectric conversion means may be a CCD.

  Further, for example, as described in claim 8, the photoelectric conversion means may be a multi-line CCD such as a 3-line color CCD.

  Further, for example, as described in claim 9, the driving unit includes a plurality of package IC drivers that supply a two-phase driving clock supplied to the photoelectric conversion unit for each phase, and the two-phase driving clock May be driven by the same package IC driver.

  Further, for example, as described in claim 10, the driving unit sets a phase adjustment amount of the final phase clock supplied to the photoelectric conversion unit to be equal to a phase adjustment amount of the reset clock and the clamp clock. You may do.

  According to the image reading apparatus of the first aspect of the invention, the original is irradiated with reading light from a light source, reflected light from the original is introduced into the photoelectric conversion means by a scanning optical system, and the photoelectric conversion means is The image data is transferred by driving at least the shift drive clock, the final stage drive clock, and the reset clock from the drive means, each clock is supplied from the timing signal generation means to the drive means, and the final stage of the timing signal generation means When adjusting the phase of the driving clock by the adjusting means, the transfer efficiency of the image data is inspected, and the adjusting means adjusts the phase of the final stage driving clock based on the inspection result of the transfer efficiency. It is possible to properly secure the zero cross point with the final stage transfer clock to keep the transfer efficiency appropriate, and the transfer efficiency is reduced and the charge is advanced. To prevent the occurrence of deterioration of PRNU), it is possible to improve image quality.

  According to the image reading apparatus of the second aspect of the present invention, the timing signal generating means includes a register for setting the clock phase, and the adjusting means performs control of setting the clock phase to the register to perform photoelectric conversion. Since the phase of the final stage drive clock supplied to the means is adjusted, the clock phase setting control is performed by the register according to the delay variation between the packages, and the phase is individually adjusted, and the phase control is performed by a controller such as a CPU. In addition, the phase of the final stage drive clock including the amount of variation in transfer efficiency of photoelectric conversion means itself such as a CCD and the amount of variation of other components (resistors, capacitors, etc.) is controlled by a register, Even if there is a delay variation between packages, the crosspoint can be secured appropriately, reducing transfer efficiency and charge advancement. To prevent the occurrence of the phenomenon (worsening PRNU) even more appropriately, the image quality can be further improved.

  According to the image reading device of the invention of claim 3, the photoelectric conversion means determines the output timing of the image data with the final stage transfer clock and the reset clock, and the driving means has a plurality of package IC drivers, Since the final stage transfer clock and reset clock supplied to the photoelectric conversion means are driven by the same package IC driver, the delay variation between packages can be eliminated, the reset clock timing can be optimized, and the reset failure between solids can be reduced. Image quality can be further improved.

  According to the image reading apparatus of the invention described in claim 4, the photoelectric conversion means has an output timing determined by the final stage transfer clock, the reset clock and the clamp clock, and the driving means has a plurality of package IC drivers, Since the final stage transfer clock, reset clock and clamp clock supplied to the photoelectric conversion means are driven by the same package IC driver, there is no delay variation between the packages, and the drive means is driven by the clamp clock from the timing signal generation means. It is possible to optimize the timing of the clamp clock to be output to the image, thereby preventing the clamp area between the solids from being increased or decreased, ensuring a stable SN, and further improving the image quality.

  According to the image reading apparatus of the fifth aspect of the invention, the driving means drives the photoelectric conversion means by using the final stage transfer clock and the clamp clock generated by the timing signal generating means in common. Compared to the case where the final stage transfer clock and the clamp clock are not used in common, the effect of variation between the two signals is eliminated, and as a result, the effective clamp area can be widened and random noise can be reduced. As a result, the image quality can be further improved.

  According to the image reading apparatus of the sixth aspect of the invention, the timing signal generating means includes a register for setting the clock phase, and the adjusting means controls the setting of the clock phase to the register, and the photoelectric conversion means. Because the phase of the reset clock to be supplied to is adjusted, the reset area of the reset clock can be removed from the effective clamp area, and the pulse width of the reset clock can be narrowed, further increasing the effective clamp area and reducing random noise In addition to ensuring a good SN, the reset clock pulse width can be set and controlled by a register and can be individually adjusted, and can be controlled by a controller such as a CPU. The image quality can be further improved.

  According to the image reading apparatus of the seventh aspect of the invention, since the CCD is used as the photoelectric conversion means, the reduction optical system can be used, and the depth of focus can be obtained so that the original can be lifted. In addition, it is possible to read a solid object to some extent without causing out-of-focus blur, and to improve the image quality.

  According to the image reading apparatus of the eighth aspect of the invention, since a multi-line CCD such as a 3-line color CCD is used as the photoelectric conversion means, a transfer clock is required for every multiple lines, and a driver for driving is also provided. Even if a multi-line CCD that requires a large number and requires a multi-package IC driver is used, it prevents the reading quality from degrading due to the crossing point variation, reset clock variation, and clamp clock variation. Image quality can be improved.

  According to the image reading apparatus of the ninth aspect of the invention, the driving means has a plurality of package IC drivers for supplying the two-phase driving clock supplied to the photoelectric conversion means for each phase, and the two-phase driving clock is supplied. Since it is driven by the same package IC driver, the cross point can be secured more reliably and the image quality can be further improved.

  According to the image reading apparatus of the tenth aspect of the invention, since the driving means makes the phase adjustment amount of the final stage phase clock supplied to the photoelectric conversion means equal to the phase adjustment amounts of the reset clock and the clamp clock. Each timing at the time of high-speed operation can be appropriately taken, a cross point can be secured more reliably, and the image quality can be further improved.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The scope of the present invention limits this invention especially in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

  1 to 23 are diagrams showing an embodiment of an image reading apparatus of the present invention. FIG. 1 is a schematic configuration diagram of a composite apparatus 1 to which an embodiment of the image reading apparatus of the present invention is applied.

  In FIG. 1, a composite apparatus 1 is a color composite apparatus having various functions such as a copy function using an electrophotographic process, a scanner function, and a facsimile function, and includes an image reading unit 2, a writing unit 3, and an image forming unit. 4, a paper feed unit 5 and a manual feed unit 6 are provided.

  The image reading unit 2 presses the document set on the contact glass 11 with the pressure plate 12, irradiates the document with light from the light source on the first traveling body 13 disposed under the contact glass 11, and The reflected light reflected from the document is reflected by the mirror on the first traveling body 13 to the mirror on the second traveling body 14. The image reading unit 2 reflects the reflected light incident on the mirror on the second traveling body 14 from the mirror on the first traveling body 13 toward the lens 15 by the second traveling body 14, and passes the lens 15 through the three-line CCD. (Charge Coupled Device) is incident on the sensor 16 and photoelectrically converted by the 3-line CCD sensor 16 to read the image of the document. The image reading unit 2 sends image data of a document photoelectrically converted by the 3-line CCD sensor 16 to the writing unit 3. The mirror on the first traveling body 13, the mirror on the second traveling body 14, and the lens 15 constitute a scanning optical system as a whole.

  Then, in the image reading unit 2, the first traveling body 13 and the second traveling body 14 move in the sub-scanning direction while performing main scanning on the document as described above, and perform main scanning and sub-scanning on the document. Read the original image.

  The image forming unit (image forming unit) 4 is a part that forms a toner image and transfers the toner image onto a transfer sheet. Each image forming unit (image forming unit) 4 is arranged around the photosensitive member 21 on which an electrostatic latent image is written by the writing unit 3. It has a process part. That is, around the photosensitive member 21, a charger 22, a developing unit 23 that supplies toner of each color of black (Bk), cyan (C), magenta (M), and yellow (Y) to the photosensitive member 21 and develops it. The intermediate transfer unit 24, the cleaning unit 25 for cleaning the toner remaining on the photoconductor 21, and the charge removal unit 26 are arranged in this order, and further include a transfer unit 27, a fixing unit 28, and the like.

  The photosensitive member 21 is rotated counterclockwise as indicated by an arrow in FIG. 1, is uniformly charged by the charger 22, and is irradiated with laser light modulated by image data from the writing unit 3. An electrostatic latent image is formed.

  The developing unit 23 supplies toner to the photosensitive member 21 on which the electrostatic latent image is formed and develops it. The intermediate transfer unit 24 includes an intermediate transfer belt 29, and the toner image on the photosensitive member 21 is transferred. Transcribed. The transfer unit 27 transfers the toner image transferred from the photosensitive member 21 to the intermediate transfer belt 29 of the intermediate transfer unit 24 onto the transfer paper conveyed from the paper supply unit 5.

  When the image forming unit 4 forms an image in full color, the writing unit 3 causes the electrostatic latent image of each color of black (Bk), cyan (C), magenta (M), and yellow (Y) to be a photoreceptor. 21, the developing unit 23 develops the electrostatic latent image of each color with the toner of the color, and sequentially superimposes and transfers the toner image of each color on the intermediate transfer belt 29 of the intermediate transfer unit 24. The intermediate transfer unit 24 transfers the full-color toner image transferred by superimposing the toner images of the respective colors onto the transfer paper conveyed from the paper supply unit 5.

  The cleaning unit 25 removes the toner remaining on the photoconductor 21 that has been transferred, and the charge removal unit 26 removes the photoconductor 21 from which the residual toner has been removed by the cleaning unit 25.

  The fixing unit 27 heats and presses the transfer sheet on which the toner image has been transferred by a heated fixing roller and a pressure roller that is pressed by the fixing roller and rotates to transfer the toner image to the transfer sheet. Then, the transfer sheet having been fixed is discharged onto a paper discharge tray (not shown) attached to the side surface of the composite apparatus 1.

  The paper feed unit (paper feed unit) 5 includes three paper feed trays 31 to 33 on which a plurality of transfer sheets are placed, a transport mechanism unit 34, and the like. To 33, transfer sheets are conveyed one by one from the appropriately selected paper feed trays 31 to 33 between the transfer section 27 of the image forming unit 4 and the intermediate transfer belt 29 one by one.

  The manual feed unit 6 is configured such that a plurality of transfer sheets are manually placed, and the placed transfer sheets are adjusted one by one between the transfer unit 27 of the image forming unit 4 and the intermediate transfer belt 29 one by one. Transport.

  As shown in FIG. 2, the multifunction apparatus 1 is configured as a block, and includes a system control unit 41, an operation unit 42, an image display unit 43, a copier mechanism unit 44, an image processing unit 45, and the image reading unit. 2 and an image writing unit 3 and the like.

  The image reading unit 2 sends the image data of the read original to the image processing unit 45, and the image processing unit 45 performs scanner γ correction, color conversion, main scanning scaling, image separation, processing, area processing, gradation correction. The image data subjected to image processing such as processing is output to the image writing unit 3.

  The image writing unit 3 modulates the drive of an LD (laser diode) according to the image processed image data input from the image processing unit 45 and irradiates the photoconductor 21 with the modulated laser light.

  The copier mechanism 44 operates under the control of the system control unit 41 to drive various mechanisms such as document conveyance and transfer sheet conveyance.

  Further, in the multifunction apparatus 1, the system control unit 41 executes a facsimile control procedure with a partner terminal such as a partner facsimile apparatus connected via a line, and receives image data transmitted from the partner terminal by facsimile. In addition, the image data of the document read by the image reading unit 2 is transmitted by facsimile to the partner terminal.

  The image display unit 43 operates under the control of the system control unit 41 and illustrates an image of a document read by the image reading unit 2.

  That is, as shown in FIG. 3, the image display unit 43 includes an LCD (Liquid Crystal Display) panel 51. The LCD panel 51 displays a read image and a cursor 52. At the bottom of the LCD panel 51 of the image display unit 43, a reading key 53 for starting reading of an original, an entire key 54 for instructing display of the entire image, an enlargement key 55 for instructing enlargement of an image, and an instruction operation for moving the screen Screen move key 56 to move, cursor key 57 to move the cursor 52, point designation key 58 to designate the point indicated by the cursor 52, close key 59 to connect the start point and end point at the time of area designation, and cancel the last designated point A clear key 60, an all clear key 61 for canceling all designated points, a contrast adjustment knob 62 for adjusting the contrast of the LCD panel 51, a brightness adjustment knob 63 for adjusting the brightness of the LCD panel 51, and the like are provided.

  As shown in FIG. 4, the screen display unit 43 includes a VRAM (Video Random Access Memory) 71, an LCD controller 72, an LCD panel 51, a keyboard 73, a ROM (Read Only Memory) 74, a CPU (Central Processing Unit) 75, A serial communication driver 76, an SRAM (Static RAM) 77, a DRAM (Dynamic Random Access Memory) 78, a FIFO (First-In First-Out) 79, an image data signal buffer 80, and the like are provided. The contrast adjustment knob 62 and the brightness adjustment knob 63 are collectively referred to as a keyboard 73. The image display unit 43 stores image data that has been subjected to image processing by the image processing unit 45 by a DMAC (Direct Memory Access Controller: DMA controller) built in the CPU via the image data signal buffer 80 and the FIFO 79. The image data control signal is transmitted to the image display unit 43 from the system control unit 41 together with the image data. The DMAC built in the CPU 75 stores only the image data in the effective image area in the DRAM 78. take in. In the image display unit 43, the CPU 75 transfers the effective image data stored in the DRAM 78 to the VRAM 71. At this time, the CPU 75 performs an arbitrary part of the image data in the DRAM 78 in accordance with an instruction by a key operation from the keyboard 73. , And processes such as enlargement / reduction / decimation, and the LCD controller 72 displays an image on the LCD panel 51 under the control of the CPU 75 based on the image data transferred to the VRAM 71. Further, when the contrast adjustment knob 62 and the brightness adjustment knob 63 of the image display unit 73 are operated, the CPU 75 adjusts the contrast and brightness of the LCD panel 51 via the LCD controller 72 according to the operation. .

  As shown in FIG. 5, the operation unit 42 includes an LCD touch panel 81, a numeric keypad 82, a mode clear / preheat key 83, an interrupt key 84, an image quality adjustment key 85, a program key 86, a start key 87, a clear / stop key 88, An area processing key 89, a brightness adjustment knob 90, an initial setting key 91, and the like are provided.

  The LCD touch panel 81 displays and outputs various operations performed by the operation unit 42 and various information notified to the user from the multifunction apparatus 1, such as paper size, paper feed stage, magnification, and the like. The operation buttons corresponding to various modes such as the copy mode, the scanner mode, and the FAX mode are displayed, and various operations on the multifunction apparatus 1 can be performed by touching the operation buttons.

  The numeric keypad 82 is used to input numerical values such as the number of copies, and the mode clear / preheat key 83 is used to cancel the set mode and return to the initial setting, or to set the preheat state by continuously pressing for a predetermined time or longer. Do. The interrupt key 84 is used when interrupting during copying to copy another document, and the image quality adjustment key 85 is used when adjusting image quality. The program key 86 is used when registering or calling a frequently used mode, and the start key 87 is used to instruct to start copying. The clear / stop key 88 is used when clearing an input numerical value or when copying is interrupted during copying. The area processing key 89 is used when a mode such as area processing / editing is used on the screen of the image display unit 43, and the brightness adjustment knob 90 is used to adjust the brightness of the screen of the LCD touch panel 81. The The initial setting key 91 is used when the user can select an initial setting.

  The operation unit 42 is connected to the system control unit 41, notifies the system control unit 41 of the operation content of the operation unit 42, and displays data to be displayed on the LCD touch panel 81 under the control of the system control unit 41. Display is performed, and the operation result of the operation button on the LCD touch panel 81 is notified to the system control unit 41.

  The LCD touch panel 81 has, for example, modes such as a color mode, automatic density, manual density, image quality mode, automatic paper selection, paper tray, automatic paper scaling, equal magnification, sorting, stack, etc., as shown in FIG. Selection display is performed, and there are also sub-screen selection displays such as create, color processing, double-sided, and variable magnification. A key having the same size as each display is set on the touch panel.

  When the magnification key in FIG. 6 is pressed, the magnification setting screen is scrolled up from the lower portion of the screen as shown in FIG. 7, and the fixed magnification (preliminary magnification) is displayed on the magnification setting screen. The key for zooming mode) is set. For example, when a 71% touch panel key is pressed, a scaling factor of 71% is selected. Also, on this scaling setting screen, a zoom key, a dimension scaling key, and an independent scaling / enlarged continuous shooting key are set on the left side of the screen to select a scaling mode other than the standard scaling.

  The LCD touch panel 81 has a touch panel detection circuit 100 configured as shown in FIG. 8, and the touch panel detection circuit 100 has a controller 101 controlling the entire touch panel detection circuit 100. The touch panel detection circuit 100 converts analog detection signals in the X-axis direction and the Y-axis direction of the LCD touch panel 81 into digital signals by the A / D converter 102. Specifically, the touch panel detection circuit 100 sets the detection terminal to a high (high) state by the controller 101, and X1, X2, Y1, and Y2 are set based on the combination table shown in FIG. Is pulled up by a resistor R, Y1 becomes + 5V when the LCD touch panel 81 is off, and 0V when it is on. Therefore, the controller 101 can confirm the on / off state of the LCD touch panel 81 from the output of the A / D converter 102. When the controller 101 detects that the LCD touch panel 81 is on, the controller 101 switches to the measurement mode. In the X direction, X1 becomes + 5V, X2 becomes 0V, and the A / D converter converts the potential at the input position through Y1. The coordinates are calculated by inputting to 102. In addition, the controller 312 calculates the coordinates in the Y direction in the same manner by switching circuits, and detects the pressed position of the LCD touch panel 81.

  The operation unit 42 has a circuit configuration as shown in FIG. 10, and includes a CPU 110, an address latch 111, a ROM 112, a system reset 113, an address decoder 114, an LED (Light Emitting Diode) driver 115, a keyboard 116, and an LCD. A controller 117, an analog touch panel 118, an LCD module 119, a ROM 120, a RAM 121, an optical transceiver 122, and the like are provided.

  In addition to the address bus and data bus from the CPU 110, the LCD controller 117 is connected to an LED driver 115, a keyboard 116, an analog touch panel 118, an LCD module 119, a display data ROM 120, a RAM 121, and the like. Is connected to an optical transceiver 122 that performs serial communication with the outside.

  The operation unit 42 is controlled by the CPU 110 by controlling each unit of the operation unit 42 based on a program in the ROM 112, fetching an address signal from the CPU 110 into the address latch 111, and controlling by the signal from the CPU 110. A part of the signal output from the address latch 111 is input to the address decoder 114, where a chip select for each IC is created and used to create a memory map. The address enters a memory such as the ROMs 112 and 120 and the RAM 121 and the LCD controller 117 and is used for address designation. On the other hand, a data bus from the CPU 110 is connected to a memory and an LCD controller 117, and bidirectional data communication is executed. Further, the LCD controller 117 creates display data from the data stored in the ROM 120 and the RAM 121 by a signal from the keyboard 116 or a signal from the touch panel 118, and controls display on the LCD module 119. The system reset 113 is connected to the CPU 110 and resets the operation unit 42 as a system.

  The main part of the circuit block configuration diagram of the composite apparatus 1 is shown in FIG. 11, and the three-line CCD sensor 16, three emitter followers 131, 132, 133 for RGB, and three for RGB respectively. Analog processing circuits 134, 135, 136, three A / D converters 137, 138, 139 for RGB, shading correction circuit 140, inter-line correction memories 141, 142 for RG, dot correction circuit 143, scanner γ correction circuit 144, delay memory 145, RGB filter 146, printer gamma correction circuit 147, automatic document color determination circuit 148, automatic image separation circuit 149, CPU 150, ROM 151, RAM 152, timing circuit 153, motor driver 154, pulse motor 155, lamp regulator 156 ,Halo 12 includes a gen lamp 157, an I / O 158, the system control unit 41, an operation unit 42, an image display unit 43, and the like. Between the timing circuit 153 and the 3-line CCD sensor 16, a CCD driving driver shown in FIG. 159 is provided. Further, an external image evaluation device 200 is connected to the composite device 1.

  The CPU 150, the ROM 151, and the RAM 152 are mounted on a control unit of an image processing unit (IPU (Image Processing Unit)) 45, and the CPU 150 executes a program in the ROM 151 to read / write data in the RAM 152 and the like. Control is in progress. The CPU 150 is connected to the system control unit 41 by serial communication, and performs an operation instructed by transmission / reception of commands and data.

  The system control unit 41 is connected to the operation unit 42 by serial communication, and an operation mode and the like are instructed and set by a key input instruction from the operator at the operation unit unit 42.

  The CPU 150 is connected to an original detection sensor, an HP sensor, a pressure plate open / close sensor, a cooling fan, and the like, which are I / O 158, and performs detection of various sensors and ON / OFF control of the fan and the like.

  The scanner motor driver 154 is driven by a PWM (Pulse Wide mosulation) output from the CPU 150, generates an excitation pulse sequence, and drives a pulse motor 155 for scanning a document.

  The image reading unit 2 presses the original set on the contact glass 11 with the pressure plate 12, and emits light to the original from a halogen lamp 157 that is a light source on the first traveling body 13 disposed below the contact glass 11. The reflected light reflected from the document is reflected by the mirror on the first traveling body 13 to the mirror on the second traveling body 14. The image reading unit 2 reflects the reflected light incident on the mirror on the second traveling body 14 from the mirror on the first traveling body 13 toward the lens 15 by the second traveling body 14, and passes the lens 15 through the three-line CCD. The light enters the sensor (photoelectric conversion means) 16 and is photoelectrically converted by the 3-line CCD sensor 16 to read the image of the document. The CPU (adjusting means) 150 drives a halogen lamp 157 as a light source via a lamp regulator 156, and outputs a light signal of reflected light from the original of the light output of the halogen lamp 157 through a plurality of mirrors and lenses to a three-line CCD. An image is formed on the sensor 16.

  The 3-line CCD sensor 16 is supplied with respective drive clocks by a timing circuit (timing signal generating means) 153 on the control unit of the image processing unit 45, and converts the RGB odd and even analog image signals into emitter followers 131-133. The emitter followers 131 to 133 output image signals to the analog processing circuits 134 to 136. The analog processing circuits 134 to 136 execute a subtraction method CDS (correlated double sampling circuit) on the input analog image signal, perform line clamping in the optical black portion of the 3-line CCD sensor 16, and odd. And the even output are adjusted, and the respective amplifier gains are adjusted. The analog processing circuits 134 to 136 combine the image signals that have undergone gain adjustment with a multiplexer, and finally adjust the offset of the DC level, and then output them to the A / D converters 137 to 139.

  The A / D converters 137 to 139 digitize the analog signals input from the analog processing circuits 134 to 136 and output the analog signals to the shading correction circuit 140. The digital image data input to the shading correction circuit 140 is included in the digital image data. , Correction of uneven illumination amount and pixel output variation of the 3-line CCD sensor 16, output R image data and G image data to inter-line correction memories 141 and 142, respectively, and directly B image data Output to the correction circuit 143. The inter-line correction memories 141 and 142 respectively delay the image data of the number of lines B and G and B and R of the 3-line CCD sensor 16 to align one or more lines of the read image of BGR, and perform dot correction. Output to the circuit 143.

  The dot correction circuit 143 corrects the deviation of dots within one line of RGB data from the image data output from the interline correction memories 141 and 142, and outputs the corrected data to the scanner γ correction circuit 144. The scanner γ correction circuit 144 Then, the reflectance linear data is corrected by the look-up table method, and is output to the RGB filter 146 via the delay memory 145, and is also output to the automatic document color determination circuit 148, the automatic image separation circuit 149, and the external image evaluation apparatus 200. .

  The automatic document color determination circuit 148 performs ACS (chromatic / achromatic determination) processing on the image data input from the scanner γ correction circuit 144, and performs black and gray determination in this ACS processing.

  The automatic image separation circuit 149 performs image area separation (character / halftone dot) processing on the image data input from the scanner γ correction circuit 144. In this image area separation processing, edge determination (continuity between white pixels and black pixels) is performed. Determination), halftone dot determination (determined by the repetitive pattern of peak / valley peak pixels in the image), photo determination (when there is image data outside the character / halftone dot), character and print (halftone dot) portion, The area of the photograph part is determined.

  The processing results of the automatic document color determination circuit 148 and automatic image separation circuit 149 are transmitted to the CPU 150 for color conversion of the RGB filter 146 at the subsequent stage, switching of parameters and coefficients in the YMCK filter of the printer γ correction 147 and gradation processing. used.

  The RGB filter 146 includes a filter, a color conversion unit, a scaling unit, and a creation unit. The filter is a filter such as RGB MTF correction, smoothing, edge enhancement, and through on the image data input from the delay memory 145. The filter process is executed by switching the coefficient according to the previous determination area. The RGB filter 146 performs YMCK conversion, UCR (under color removal), and UCA processing from RGB data in the color conversion processing, and performs enlargement / reduction processing on the main scan image data in the scaling processing. To do. Further, the RGB filter 146 is connected to the image display unit 43 via the I / F, and branches to the image display unit 43 after this processing. In addition, the RGB filter 146 performs create editing and color processing in the create, and in the create editing, italics, mirrors, shadowing, outline processing, and the like are executed. In the color processing, color conversion, designated color deletion, undercolor Etc.

  The printer γ correction circuit 147 performs printer γ conversion and filter coefficient setting based on the previous determination region, executes dither processing in gradation processing, and sets write timing, image region, and white region in video control. And the test pattern generation such as gray scale and color patch is performed, and the final image data is processed so that it can be output to the LD (laser diode) by the writing process, and is output to the LD.

  Each function process of each unit is connected to the CPU 150, and the CPU 150 executes setting and operation of each process according to an instruction from the system control unit 41 based on a program stored in the ROM 151.

  The composite apparatus 1 is connected to the external image evaluation apparatus 200 as an external output, and outputs RGB image data after the scanner γ correction. The external image evaluation apparatus 200 calculates the transfer efficiency from the image data, determines the PH2B phase adjustment delay advance direction and the phase shift amount from the result of the transfer efficiency drop and the charge advance phenomenon, and the system control unit by serial communication It is input to the CPU 150 of the composite apparatus 1 via 41 so that adjustment can be performed.

  The timing circuit 153 and the CCD drive driver (drive means) 159 are arranged as shown in FIG. 12, and the timing circuit 153 is a register setting unit including a clock generation circuit 161, a bus I / F 162, and a control circuit. 163, a PLL (Phase Locked Loop) circuit 164, a CCD clock generation circuit 165, a pulse adjustment circuit 166, and the like. The PLL circuit 164 includes a phase frequency detector 171, a charge pump 172, a voltage control oscillator 173, and a frequency divider 174. The clock is input from the oscillator 200 to the phase frequency detection circuit 171 of the PLL circuit 164.

  The timing circuit 153 uses the clock from the oscillator 180 as an input to the PLL circuit 164, sets the frequency divider 174 by setting the register 163 via the CPU bus I / F 162, generates a quadruple clock, and generates this clock. Various clocks are generated as a source. The timing circuit 153 includes a first phase transfer clock PH1, a second phase transfer clock PH2, a final stage transfer clock PH2B, a reset clock RS, a clamp clock CP, and a shift gate clock that drive the 3-line CCD sensor 16 from the CCD clock generation circuit 165. SH is generated and input to the pulse adjustment circuit 166 in the subsequent stage, and the phase shift amount and the pulse width increase / decrease amount of each clock pulse are adjusted according to the control of the register setting unit 163, and output to the CCD driver 159. This pulse phase shift amount has a function of adjusting the shift amount in half cycle units of the quadruple clock, and the pulse width increase / decrease amount also increases / decreases the pulse width amount in half cycle units of the quadruple clock. It has a function to do.

  As shown in FIG. 13, the CCD drive driver 159 includes drive elements 181a to 181i, and the drive elements 181a to 181i with respect to one terminal of the first and second phase transfer clocks PH1 and PH2 of the three-line CCD sensor 16. Are connected in parallel. As shown in FIG. 13, the first and second phase transfer clocks PH1 and PH2 of the three-line CCD sensor 16 have eight terminals each having an input capacity of MAX150pF and TYP100pF, and the input capacity of each drive element 181a to 181i. As for MAX10pF, when driven by one terminal, the input capacitance of the timing circuit 153 is MAX10 × 16 + 47 = 207pF including the capacitor 47pF for waveform shaping and timing fine adjustment. FIG. 13 shows a case where ACT04 is used as the drive elements 181a to 181i.

  In the allocation of packaging of the drive elements 181a to 181i of the CCD driver 159, when the first phase transfer clock φ1A (PH1) and the second phase transfer clock φ2A (PH2) are allocated for packaging of the same signals, Due to variations in packaging of the drive elements 181a to 181i, the phase shift between the first phase transfer clock PH1 and the second phase transfer clock PH2 becomes large, and it becomes difficult to secure a cross point. Actually, when ACT04 as shown in FIG. 14 is used as a driver IC of the CCD drive driver 159, the propagation delay time varies depending on the lots A, B, and C depending on the temperature, and a variation of about 4 ns occurs. Variation of ACT04, that is, variation of the package of the drive elements 181a to 181i.

  On the other hand, in the allocation of the packaging of the CCD drive driver 159 of the composite apparatus 1 of the present embodiment, as shown in FIG. 13, the paired first and second phase transfer clocks PH1 and PH2 are made the same package. Thus, the delay variation between the packages is eliminated, and a cross point between the first phase transfer clock PH1 and the second phase transfer clock PH2 is secured.

  The input / output timing chart in the driver section of FIG. 13 is shown in FIG. 15, and as shown in FIG. 15A, the first phase transfer clock XPH1, which is the driver input (output of the timing circuit 153), The two-phase transfer clock XPH2 and the final-stage transfer clock XPH2B are equal to T1: T1 with a clock duty (Duty) ratio of 50:50. As shown in FIG. 15B, this signal is input to the drive elements 181a to 181i configured by ACT04, and is inverted to drive the 3-line CCD sensor 16 as a driver output. Similarly, the first phase transfer clock PH1, the second phase transfer clock PH2, and the final stage transfer clock PH2B of the CCD input transfer clock are equal to T1: T1 with a duty ratio of 50:50. At this time, as shown in FIG. 15C, the cross-points of the first phase transfer clock PH1 and the second phase transfer clock PH2 are both 2V or higher and the crossing point of the first phase transfer clock PH1 is a cross point. Satisfy the standard value of points. Similarly, the first phase transfer clock PH1 and the final stage transfer clock PH2B have cross points that are both 2 V or higher in the first phase transfer clock PH1 and satisfy the standard value of the cross point. .

  Note that the CCD drive driver 159 is not limited to the above configuration, and for example, as shown by a dashed circle in FIG. 16, the final stage transfer clock XPH2B may be used in common as the clamp clock XCP.

  That is, in the CCD drive driver 159 of FIG. 16, as shown by a round dotted line portion, the connection of the final stage transfer clock XPH2B and the clamp clock XCP is changed as compared with FIG. This circuit is used in common with XCP.

  In the CCD drive driver 159 having the circuit configuration of FIG. 16, the timing chart can be shown as shown in FIG. 17, and the effective clamp area by the clamp clock CP is from the reset clock RS ↓ to the final stage transfer clock PH2B ↓. Therefore, the maximum effective clamp width at the pulse width of the reset clock RS at that time can be obtained by commonly inputting the final stage transfer clock PH2B signal instead of the clamp clock CP of another pulse. The specification of the effective clamp width varies depending on the 3-line CCD sensor 16, but if the effective clamp width is not secured, the random noise of the 3-line CCD sensor 16 tends to increase.

  In this embodiment, the cross-point can be easily secured, the delay of the propagation delay time of the package of the driver IC of the CCD driver 159, and the final stage transfer clock even if there are other variations in the timing circuit 153, etc. The cross-point between the final stage transfer clock PH2B ↑ and the first phase transfer clock PH1 ↓ can be secured by adjusting the phase shift amount of the clock pulse of XPH2B.

  Next, the pulse adjustment function including the phase shift amount adjustment will be described with reference to FIGS.

  FIG. 18 is a diagram illustrating adjustment of the pulse phase shift amount. The phase shift amounts of the final stage transfer clock XPH2B, the reset clock XRS, and the clamp clock XCP are shown in the timing chart of FIG. It is said. Although the composite apparatus 1 of the present embodiment has a phase shift amount in a range of −4 to +4, it can cope with any timing by adopting a configuration capable of phase shift for one period.

  In FIG. 18, the phase shift amount indicates the phase shift 0 by a solid line on the basis of the falling edge of the half-clock unit of the quadruple clock generated by the PLL circuit 164, and the dotted line indicates the phase shift −2, −1, +1 , +2. Phase shifts of −4, −3, +3, and +4 are similarly phase-shifted, but are omitted in FIG. Further, FIG. 18 shows a phase shift example for the final transfer clock XPH2B and the reset clock XRS, but the clamp clock XCP is the same and is omitted.

  FIG. 19 is a diagram showing adjustment of the pulse width increase / decrease amount. The pulse width increase / decrease amounts of the final stage transfer clock XPH2B, the reset clock XRS, and the clamp clock XCP are the same as the timing chart shown in FIG. Default.

  In the composite apparatus 1 of this embodiment, the pulse width increase / decrease amount is set to −3 to +3. However, the final stage transfer clock XPH2B, the reset clock XRS, and the clamp clock XCP are divided into 16 when the unit is a half clock of 4 times. Therefore, it is possible to cope with any timing by adopting a configuration in which a pulse width of a minimum of 1 division to a maximum of 15 divisions can be obtained.

  In FIG. 19, the pulse width increase / decrease amount of the final stage transfer clock XPH2B and the reset clock XRS shows an example of −1, +1, and the pulse width increase / decrease is performed on the rising edge basis. The pulse width increase / decrease amounts of -3, -2, +2, and +3 increase and decrease in the same manner, but are omitted in FIG. Further, in FIG. 19, the clamp clock XCP is the same, and thus is omitted.

  Next, the pulse adjustment function register will be described with reference to FIG. As shown in FIG. 20 (a), the phase shift amount adjustment function register has a 16-bit register configuration in which the default is set to 0 in 4 bits, and can be set up to ± 4. As shown in FIG. 20B, the pulse width increase / decrease amount adjustment function register has a 16-bit register configuration in which 3 bits can be set up to ± 3.

  First, the case where the phase shift amount is not adjusted will be described with reference to FIG. FIG. 21 shows a case where the propagation delay time of the package of the CCD drive driver 159 which is a driver IC including the final stage transfer clock PH2B is large, or a plurality of driver ICs (CCDs) of the first phase transfer clock PH1 and the second phase transfer clock PH2. FIG. 22 is a timing chart of a driver input (FIG. 21A), a driver output (FIG. 21B), and a cross point when the propagation delay time as a sum of the drive drivers 159 is small. Due to this difference in propagation delay time, a skew Td occurs, and the cross point between the first-phase transfer clock PH1 ↓ and the final-stage transfer clock PH2B ↑ due to the occurrence of this skew is a standard value 2V as shown in FIG. It becomes 2V or less which cannot ensure the above.

  Therefore, there is a risk that transfer efficiency is lowered and PRNU is deteriorated.

  Also in the case of FIG. 22, the same signal as the final stage transfer clock XPH2B is input to the clamp clock XCP, and the same problem may occur during high-speed operation. 22A shows the driver input when the same signal as the final stage transfer clock XPH2B is input to the clamp clock XCP, FIG. 22B shows the driver output, and FIG. 22C shows the crosspoint. It is a timing chart.

  FIG. 23 shows a case where the same signal as the final stage transfer clock XPH2B is input to the clamp clock XCP and the phase shift adjustment function is performed on the final stage transfer clock XPH2B.

  In the case of FIG. 23, the cross point cannot be secured due to the skew Td in the case of FIG. 22, but the phase shift amount adjustment function register of the final stage transfer clock XPH2B is set as shown in the driver input of FIG. By subtracting -1 from the normal state, the phase of the PLL clock can be shifted by half a clock. The phase shift amount is adjusted to an appropriate value according to the skew amount of the skew Td. In the example of FIG. 23, as shown in FIGS. 23B and 23C, the skew is reduced to (Td-PLL half clock), and a cross point can be secured. Further, the timing of each signal is obtained by adding the same phase shift amount as that of the final stage transfer clock XPH2B to the reset clock XRS and clamp clock XCP input to the same package of the final stage transfer clock XPH2B and the CCD driver 159. Can be secured.

  Then, the adjustment of the appropriate value of the phase shift amount is to output the image data after the scanner γ correction shown in FIG. 11 to the outside and capture the RGB image data by the external image evaluation device 160 to reduce the influence of noise and the like. After performing the averaging process, the transfer efficiency is calculated by the following equation (1).

Transfer efficiency = (output value of the last pixel) / ((output value of the last + 1 pixel) + output value of the last pixel) × 100% (1)
The external image evaluation device 160 transmits the calculated transfer efficiency to the CPU 150 as the adjustment means via the system control unit 41 by serial communication, and the CPU 150 adjusts the phase shift amount again. By adjusting the reading efficiency of the image data and calculating the transfer efficiency, the skew between the packages of the driver IC (CCD drive driver 159) is canceled by putting the transfer efficiency within the standard value, and the high reliability and high Stable image reading can be performed.

  Further, as the package configuration of the CCD drive driver 159, the final stage transfer clock PH2B, the reset clock RS, and the clamp clock CP are included in the same package, so that the skew in the final stage transfer clock can be minimized. Further, in accordance with the phase shift of the final stage transfer clock PH2B, the phase shift of the reset clock RS and the clamp clock CP needs to be performed because there is no margin at each timing during high-speed operation. In this embodiment, the reset clock RS, Since the clamp clock CP also has a phase shift adjustment function, it can be easily adjusted.

  Furthermore, the composite apparatus 1 of this embodiment has a great effect on a multi-line CCD having a large CCD driving capacity.

  In addition, when the CCD output period is not sufficiently ensured in high-speed reading, the influence of variations between packages can be reduced, so that highly reliable and highly stable reading can be realized.

  Finally, as an example of the present invention, the case where ACT04 with six circuits is used as the CCD drive driver 159 has been shown, but it can also be realized by using ACT240 or the like with eight circuits.

  As described above, the composite apparatus 1 of the present embodiment irradiates the original with reading light from the halogen lamp 157 as a light source, and the reflected light from the original is scanned by a three-line CCD sensor 16 as photoelectric conversion means. The 3-line CCD sensor 16 is driven by at least the shift drive clock, the final stage drive clock, and the reset clock from the CCD drive driver 159 to transfer image data, and the CCD drive driver 159 is supplied from the timing circuit 153. When the CPU 150 adjusts the phase of the final stage drive clock of the timing circuit 153 by supplying each clock, the CPU 150 checks the transfer efficiency of the image data, and the CPU 150 determines the final stage drive clock based on the transfer efficiency test result. The phase is adjusted.

  Therefore, the zero cross point between the transfer clock and the final stage transfer clock can be appropriately secured to maintain the transfer efficiency properly, and the transfer efficiency is reduced and the charge forward transfer phenomenon (PRNU deterioration) is prevented. , Image quality can be improved.

  In the composite apparatus 1 of this embodiment, the timing circuit 153 includes a register for setting the clock phase, and the CPU 150 controls the setting of the clock phase to the register and supplies it to the 3-line CCD sensor 16. The phase of the final stage drive clock is adjusted.

  Therefore, the clock phase setting control is performed by the register according to the delay variation amount between the packages, the phase can be individually adjusted, and the phase can be controlled by the controller such as the CPU 150, or the 3-line CCD sensor 16 itself. Even if there is a delay variation between packages, the phase of the final stage drive clock is set and controlled by a register, including variations in transfer efficiency and variations in other components (resistors, capacitors, etc.). The cross point can be appropriately secured, and the image quality can be further improved by more appropriately preventing the transfer efficiency from being lowered and the charge advancement phenomenon (PRNU deterioration).

  Further, in the composite apparatus 1 of this embodiment, the 3-line CCD sensor 16 determines the output timing of the image data by the final stage transfer clock and the reset clock, and the CCD drive driver 159 is a drive element that is a plurality of package IC drivers. The final stage transfer clock and reset clock supplied to the 3-line CCD sensor 16 are driven by the same drive elements 181a to 181i.

  Therefore, the delay variation between packages can be eliminated, the timing of the reset clock can be optimized, the reset failure between the individual can be reduced, and the image quality can be further improved.

  In the composite apparatus 1 of this embodiment, the output timing of the 3-line CCD sensor 16 is determined by the final stage transfer clock, the reset clock, and the clamp clock, and the CCD drive driver 159 is a drive element that is a plurality of package IC drivers. The final stage transfer clock, reset clock, and clamp clock supplied to the three-line CCD sensor 16 are driven by the same drive elements 181a-181i.

  Therefore, the delay variation between packages is eliminated, the timing of the clamp clock output from the CCD drive driver 159 to the 3-line CCD sensor 16 by the clamp clock from the timing circuit 153 is optimized, and the clamp area between the solids is increased or decreased. Can be prevented, stable SN can be secured, and the image quality can be further improved.

  Furthermore, in the composite apparatus 1 of this embodiment, the CCD drive driver 159 drives the 3-line CCD sensor 16 using the final stage transfer clock and the clamp clock generated by the timing circuit 153 in common.

  Therefore, the effect of variation between the two signals at the source is eliminated, and as a result, the effective clamp area is widened and random noise is reduced compared to when the final stage transfer clock and clamp clock are not used in common. Therefore, good SN can be secured and the image quality can be further improved.

  In the composite apparatus 1 of this embodiment, the timing circuit 153 includes a register for setting the clock phase, and the CPU 150 controls the setting of the clock phase to the register and supplies it to the 3-line CCD sensor 16. The reset clock phase is adjusted.

  Accordingly, the reset area of the reset clock can be removed from the effective clamp area, and the pulse width of the reset clock can be narrowed. The effective clamp area can be further increased to reduce random noise and ensure good SN. In addition, the pulse width of the reset clock can be set and controlled by a register and can be individually adjusted, and can be controlled by a controller such as a CPU, so that the image quality can be further improved.

  Furthermore, the composite apparatus 1 of this embodiment uses a CCD as the photoelectric conversion means. Therefore, the reduction optical system can be used, and the depth of focus can be obtained, and the document floating and reading of a certain amount of three-dimensional object can be performed without causing defocusing, thereby improving the image quality. Can do.

  Further, the composite apparatus 1 of this embodiment uses a multi-line CCD such as a 3-line color CCD 16 as a photoelectric conversion means.

  Therefore, even if a transfer clock is required for each of the plurality of lines, a large number of drivers are required, and a multi-line CCD that also requires a multi-package IC driver is used, there are cross-point variations, reset clock variations, clamp clock It is possible to prevent the reading quality from deteriorating due to the variation in the image quality, and to improve the image quality.

  Furthermore, the composite apparatus 1 of the present embodiment includes drive elements 181a to 181i which are a plurality of package IC drivers that supply a two-phase drive clock supplied to the 3-line CCD sensor 16 by the CCD drive driver 159 for each phase. The two-phase drive clock is driven by the same drive elements 181a to 181i.

  Therefore, the cross point can be secured more reliably and the image quality can be further improved.

  In the composite apparatus 1 of this embodiment, the phase adjustment amount of the final stage phase clock supplied to the three-line CCD sensor 16 by the CCD drive driver 159 is made equal to the phase adjustment amounts of the reset clock and the clamp clock. .

  Therefore, each timing at the time of high-speed operation can be appropriately taken, a cross point can be secured more reliably, and the image quality can be further improved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Applicable to image readers such as scanners, digital copiers, digital color copiers, facsimile machines, and color facsimile machines that scan the image while ensuring the clock cross point to the photoelectric conversion means that photoelectrically converts the reflected light from the original can do.

1 is a schematic front view of a composite apparatus to which an embodiment of an image forming apparatus of the present invention is applied. The principal part block block diagram of the compound apparatus of FIG. The top view of the image display unit of FIG. The circuit block block diagram of the image display unit of FIG. The top view of the operation part unit of the operation part unit of FIG. The figure which shows the example of a screen display of the LED touch panel of FIG. The figure which shows an example of a screen expansion | deployment when the magnification key is pressed by the screen display of FIG. The circuit diagram of the touch-panel detection circuit of the LCD touch panel of FIG.6 and FIG.7. The figure which shows the combination of the detection signal of the touchscreen detection circuit of FIG. The circuit block diagram of the operation part unit of FIG. FIG. 2 is a main part circuit block configuration diagram of the composite apparatus of FIG. 1. FIG. 12 is a detailed circuit diagram of the timing circuit of FIG. 11 and a circuit block diagram in which a CCD drive driver is added. FIG. 13 is a circuit configuration diagram of the CCD drive driver and the 3-line CCD sensor of FIG. 12. FIG. 14 is a diagram showing variations in propagation delay time of drive elements of the CCD drive driver of FIG. 13. FIG. 14 is a timing chart of driver input (a), driver output (b), and cross points of the CCD drive driver of FIG. 13. FIG. 14 is a circuit configuration diagram of a CCD drive driver and a 3-line CCD sensor in which XPH2B of the CCD drive driver of FIG. 13 is shared by XCP. FIG. 17 is a timing chart of driver input (a), driver output (b), and cross points of the CCD drive driver of FIG. 16. Explanatory drawing of a pulse phase shift amount adjustment process. Explanatory drawing of a pulse width increase / decrease amount adjustment process. Explanatory drawing of the phase shift amount adjustment function register (a) and pulse width increase / decrease amount adjustment function register (b) of a pulse adjustment function register. 6 is a timing chart of a driver input (a), a driver output (b), and a cross point of a CCD driver when there is no phase shift amount adjustment. The timing chart of a driver input (a), a driver output (b), and a cross point when the same signal as XPH2B is input to XCP of a CCD drive driver. FIG. 6 is a timing chart of driver input (a), driver output (b), and cross points when a phase shift adjustment function is performed by inputting the same signal as XPH2B to XCP of a CCD drive driver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Compound apparatus 2 Image reading unit 3 Writing unit 4 Image forming unit 5 Paper feed unit 6 Manual feed unit 11 Contact glass 12 Pressure plate 13 First traveling body 14 Second traveling body 15 Lens 16 3 line CCD sensor 21 Photoconductor 22 Charger DESCRIPTION OF SYMBOLS 23 Developing part 24 Intermediate transfer part 25 Cleaning part 26 Electric discharge part 27 Transfer part 28 Fixing part 29 Intermediate transfer belt 31-33 Paper feed tray 34 Conveyance mechanism part 41 System control unit 42 Operation part unit 43 Image display unit 44 Copying machine mechanism part 45 Image processing unit 51 LCD panel 52 Cursor 53 Reading key 54 Whole key 55 Zoom key 56 Screen movement key 57 Cursor key 58 Point designation key 59 Close key 60 Clear key 61 All clear key 62 Contrast adjustment knob 63 Brightness Adjustment knob 71 VRAM
72 LCD controller 73 Keyboard 74 ROM
75 CPU
76 Serial communication driver 77 SRAM
78 DRAM
79 FIFO
80 Image Data Signal Buffer 81 LCD Touch Panel 82 Numeric Keypad 83 Mode Clear / Preheat Key 84 Interrupt Key 85 Image Quality Adjustment Key 86 Program Key 87 Start Key 88 Clear / Stop Key 89 Area Processing Key 90 Brightness Adjustment Knob 91 Initial Setting Key 100 Touch Panel Detection Circuit 101 controller 102 A / D converter 110 CPU
111 Address latch 112 ROM
113 System Reset 114 Address Decoder 115 LED Driver 116 Keyboard 117 LCD Controller 118 Touch Panel 119 LCD Module 120 ROM
121 RAM
122 Optical transceiver 131, 132, 133 Emitter follower 134, 135, 136 Analog processing circuit 137, 138, 139 A / D converter 140 Shading correction circuit 141, 142 Interline correction memory 143 Dot correction circuit 144 Scanner gamma correction circuit 145 Delay memory 146 RGB filter 147 Printer γ correction circuit 148 Automatic document color determination circuit 149 Automatic image separation circuit 150 CPU
151 ROM
152 RAM
153 Timing circuit 154 Motor driver 155 Pulse motor 156 Lamp regulator 157 Halogen lamp 158 I / O
200 External Image Evaluation Device 159 CCD Drive Driver 161 Clock Generation Circuit 162 Bus I / F
163 Register setting unit 164 PLL circuit 165 CCD clock generation circuit 166 Pulse adjustment circuit 171 Phase frequency detector 172 Charge pump 173 Voltage control oscillator 174 Frequency divider 180 Oscillator 181a to 181i Driving element

Claims (10)

  The original is irradiated with reading light from the light source, the reflected light from the original is introduced into the photoelectric conversion means by the scanning optical system, and the photoelectric conversion means includes at least a shift drive clock, a final stage drive clock, and a drive means. An image reading apparatus that transfers image data by driving with a reset clock, supplies the clocks to the driving means from the timing signal generating means, and adjusts the phase of the final stage driving clock of the timing signal generating means with the adjusting means The image reading apparatus according to claim 1, wherein the transfer efficiency of the image data is inspected, and the adjusting unit adjusts the phase of the final stage drive clock based on the inspection result of the transfer efficiency.   The timing signal generating means includes a register for setting the phase of the clock, and the adjusting means controls the setting of the phase of the clock to the register and supplies the final stage drive clock to be supplied to the photoelectric conversion means. The image reading apparatus according to claim 1, wherein the phase is adjusted.   The photoelectric conversion means determines the output timing of the image data by the final stage transfer clock and the reset clock, and the driving means has a plurality of package IC drivers and supplies the final stage transfer supplied to the photoelectric conversion means 3. The image reading apparatus according to claim 1, wherein the clock and the reset clock are driven by the same package IC driver.   The photoelectric conversion means has an output timing determined by the final stage transfer clock, the reset clock and the clamp clock, and the driving means has a plurality of package IC drivers, and the final stage transfer supplied to the photoelectric conversion means 3. The image reading apparatus according to claim 1, wherein the clock, the reset clock, and the clamp clock are driven by the same package IC driver.   5. The image reading apparatus according to claim 4, wherein the driving unit drives the photoelectric conversion unit by using the final stage transfer clock generated by the timing signal generating unit and the clamp clock in common.   The timing signal generation means includes a register for setting the phase of the clock, and the adjustment means controls the setting of the phase of the clock to the register and sets the phase of the reset clock supplied to the photoelectric conversion means. The image reading apparatus according to claim 1, wherein adjustment is performed.   7. The image reading apparatus according to claim 1, wherein the photoelectric conversion unit is a CCD.   7. The image reading apparatus according to claim 1, wherein the photoelectric conversion means is a multi-line CCD such as a 3-line color CCD.   The driving means includes a plurality of package IC drivers that supply a two-phase driving clock supplied to the photoelectric conversion means for each phase, and the two-phase driving clocks are driven by the same package IC driver. An image reading apparatus according to any one of claims 1 to 8.   10. The drive unit according to claim 1, wherein a phase adjustment amount of the final stage phase clock supplied to the photoelectric conversion unit is made equal to a phase adjustment amount of the reset clock and the clamp clock. The image reading apparatus according to any one of the above.

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