JP2005025290A - Electronic control device - Google Patents

Abstract

By diagnosing a watchdog timer without switching a reset signal to a port, even if a CPU runs out of control during diagnosis, it can be restored if the watchdog timer is operating normally. It is to provide an electronic control device.
When a P-RUN signal supplied from a CPU 2 to a watchdog timer 3 is stopped, the CPU 2 determines whether the watchdog timer 3 has reset the CPU 2 or not. A failure diagnosis of the timer 3 is performed. During the reset operation, the CPU 2 writes an etaner to the EEPROM 5 before the P-RUN signal is stopped. Therefore, the CPU 2 determines whether or not the watchdog timer 3 has performed the reset operation using the data written to the EEPROM 5.
[Selection] Figure 1

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic control device that detects CPU runaway by inputting a P-RUN signal output from a CPU to a watchdog timer.
[0002]
[Prior art]
As a conventional electronic control device, for example, as described in JP-A-5-216711, in order to diagnose a watchdog timer, a reset signal to the CPU is switched to a port only at the time of diagnosis, and diagnosis is performed. Things are known.
[0003]
[Patent Document 1]
JP-A-5-216711 [0004]
[Problems to be solved by the invention]
However, in the method described in Japanese Patent Laid-Open No. 5-216711, if a CPU runaway occurs when the reset signal is switched to the port side, the reset terminal of the CPU cannot be operated. There was a problem that would be impossible.
[0005]
The object of the present invention is to perform a diagnosis of the watchdog timer without switching the reset signal to the port, so that even if the CPU runs out of control during the diagnosis, if the watchdog timer is operating normally, the recovery is possible. An object of the present invention is to provide an electronic control device that can be used.
[0006]
[Means for Solving the Problems]
(1) In order to achieve the above object, the present invention provides an electronic control device having a microcomputer and a watchdog timer for detecting an abnormal state of the microcomputer based on a program running signal from the microcomputer. When the program running signal supplied from the microcomputer to the watchdog timer is stopped, the microcomputer determines whether or not the watchdog timer has reset the microcomputer. It is designed to diagnose the failure of the dog timer.
With this configuration, by diagnosing the watchdog timer without switching the reset signal to the port, it is possible to recover if the watchdog timer is operating normally even during a CPU runaway during diagnosis. Become.
[0007]
(2) In the above (1), preferably, the microcomputer uses the data written in the storage device to determine whether or not the watchdog timer has performed a reset operation. .
[0008]
(3) In the above (2), preferably, the data written to the storage device is written to the storage device before the program running signal is stopped.
[0009]
(4) In the above (1), preferably, the microcomputer determines whether or not the watchdog timer has performed a reset operation, and resets the microcomputer during a specified period after the program running signal is stopped. Judgment is based on not taking it.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and operation of an electronic control device according to an embodiment of the present invention will be described with reference to FIGS.
First, the system configuration of the electronic control device according to the present embodiment will be described with reference to FIG.
FIG. 1 is a system configuration diagram showing the configuration of an electronic control device according to an embodiment of the present invention.
[0011]
The electronic control device 1 includes a microcomputer (CPU) 2, a watchdog timer 3, a power supply circuit 4, an EEPROM 5, and a warning lamp driving driver 6. A power source 9, a power switch 8, and a warning lamp 7 are connected to the outside of the electronic control device 1.
[0012]
When the power switch 8 is turned on, a constant voltage is generated by the regulator of the power supply circuit 4 based on the voltage from the power supply 9 and supplied to the CPU 2, the watchdog timer 3, and the EEPROM 5. A reset signal RES output from the watchdog timer 3 is input to the CPU 2. A program running (P-RUN) signal output from the CPU 2 is input to the watchdog timer 3.
[0013]
Next, the normal operation of the watchdog timer in the electronic control apparatus according to the embodiment of the present invention will be described with reference to FIG.
FIG. 2 is a time chart showing the normal operation of the watchdog timer in the electronic control apparatus according to the embodiment of the present invention. In FIG. 2, the horizontal axis indicates time. FIG. 2A shows the output voltage of the power supply circuit 4. FIG. 2B shows the reset signal RES output from the watchdog timer 3. FIG. 2C shows a P-RUN signal output from the watchdog timer 3. FIG. 2D shows the operating state of the warning lamp 7. FIG. 2E shows the contents of ROM data inside the CPU 2. FIG. 2F shows the data stored in the EEPROM 5.
[0014]
As shown in FIG. 2A, when the power switch 8 is turned on, the power supply circuit 4 supplies a constant power supply voltage for control to the CPU 2, the watchdog timer 3, and the EEPROM 5 by a regulator. As shown in FIG. 2B, the watchdog timer 3 is in a period from the time when the control constant power supply voltage value exceeds a predetermined value until the oscillator output to the CPU is stabilized (before time t1). Reset signal low level is output.
[0015]
Next, at time t1, as shown in FIG. 2B, when the reset signal rises, the CPU 2 starts normally and continues to output the P-RUN signal to the watchdog timer 3.
[0016]
At time t2, as shown in FIGS. 2E and 2F, the CPU 2 writes the data (in this example, data “$ 55”) stored in the ROM inside the CPU 2 into the EEPROM 5. .
[0017]
When the writing ends, at time t3, the CPU 2 stops the P-RUN signal as shown in FIG. Thereby, at time t4, the watchdog timer 3 outputs a reset signal low level as shown in FIG. 2B, and the CPU 2 is in a reset state.
[0018]
At time t5, when the reset signal rises again as shown in FIG. 2 (B), the CPU 2 returns to normal again and starts outputting the P-RUN signal as shown in FIG. 2 (C).
[0019]
At time t6, the CPU 2 reads the data stored in the EEPROM 5 written before the reset, and compares it with the ROM data that is the writing source in the CPU 2. As a result of the comparison, when the data match, at time t7, as shown in FIG. 2F, the write data in the EEPROM 5 is cleared (set to $ FF), and the operation diagnosis of the watchdog timer 3 is finished. Thus, it can be diagnosed that the watchdog timer 3 is operating normally.
[0020]
Next, the operation at the time of abnormality of the watchdog timer in the electronic control device according to the embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a time chart showing the operation when the watchdog timer is abnormal in the electronic control device according to the embodiment of the present invention. The vertical and horizontal axes in FIG. 3 are the same as those in FIG.
[0021]
As shown in FIG. 3A, when the power switch 8 is turned on, the power supply circuit 4 supplies a constant power supply voltage for control to the CPU 2, the watchdog timer 3, and the EEPROM 5 by a regulator. As shown in FIG. 3 (B), the watchdog timer 3 is in a period from when the constant power supply voltage for control exceeds a predetermined value until the oscillator output to the CPU is stabilized (before time t1). Reset signal low level is output.
[0022]
Next, at time t1, as shown in FIG. 3B, when the reset signal rises, the CPU 2 starts normally and continues to output the P-RUN signal to the watchdog timer 3.
[0023]
At time t2, the CPU 2 writes the data stored in the ROM inside the CPU 2 to the EEPROM 5, as shown in FIGS. 3 (E) and 2 (F).
[0024]
When the writing is completed, at time t3, the CPU 2 stops the P-RUN signal as shown in FIG. The operation so far is the same as the normal operation. When the P-RUN signal is stopped, if the watchdog timer 3 is normal, the watchdog timer 3 outputs a reset signal low level as shown in FIG. 2B, and the CPU 2 enters a reset state. .
[0025]
However, since the watchdog timer 3 is out of order, the watchdog timer 3 does not output a reset signal at time t4 as shown in FIG. As indicated by 3 (C), since the rising edge of the reset signal is not output, the output stop of the P-RUN signal is continued.
[0026]
Then, as shown in FIG. 3D, when a specified time or more has elapsed since the P-RUN signal stopped (time t6), the CPU 2 outputs an ON signal high level to the warning lamp driving driver 6, and the warning lamp By illuminating 7, it is possible to inform that the watchdog timer has failed.
[0027]
Next, the control operation of the electronic control device according to the embodiment of the present invention will be described with reference to FIG.
FIG. 4 is a flowchart showing a control operation of the electronic control device according to the embodiment of the present invention.
[0028]
When power is turned on by the power switch 8 and the rising edge of the reset signal is detected, in step s10, the CPU 2 executes an initial setting program as a reset routine.
[0029]
In step s20, the CPU 2 starts outputting a P-RUN signal with a constant period.
[0030]
Next, in step s30, the CPU 2 reads data from a predetermined address of the EEPROM 5, and in step s40, the CPU 2 determines whether the value is, for example, $ 55. If the read data is $ 55, the process proceeds to step s100, and if it is not $ 55, the process proceeds to step s50.
[0031]
Since the data initial value of the EEPROM 5 is $ FF at time t2 in FIG. 2, the CPU 2 writes $ 55 to a predetermined address of the EEPROM 5 in step s50.
[0032]
Next, in step s60, the CPU 2 stops the P-RUN signal and waits for a reset by the watchdog timer to occur during a specified time. In order to monitor the generation of the reset signal, a timer is started, and in step s70, the CPU 2 adds +1 to the timer. In step s70, the CPU 2 determines whether or not the timer value has exceeded a specified value. When it does not exceed, the process returns to step s70, and when it exceeds, the process proceeds to step s90.
[0033]
Here, as a normal operation, when a reset by the watchdog timer occurs within a specified time, as shown by a broken line, the process returns to step s10, and the CPU 2 is initialized again (step s10), and the P-RUN signal output (step s20), predetermined data reading from the EEPROM 5 (step s30), and data comparison (step s40) are executed.
[0034]
In the determination of step s40, since the EEPROM 5 read data is $ 55 here, the process proceeds to step s100, where the CPU 2 clears the predetermined data in the EEPROM 5 and the watchdog timer failure diagnosis determination control ends. It should be noted that the CPU 2 is configured to be able to detect a watchdog timer reset signal at any point in the flow so far when the CPU runs away.
[0035]
On the other hand, when the watchdog timer fails, since no reset occurs after the P-RUN signal is stopped in step s60, the addition of the timer in step s70 is repeated, and when the prescribed value is exceeded by the determination in step s80, step s90 Then, the CPU 2 turns on the warning lamp 7 to notify the failure of the watchdog timer and the process is ended.
[0036]
In the above description, an EEPROM is used as a storage device for writing data, but a RAM can also be used.
[0037]
Moreover, although the result of failure diagnosis is displayed by the warning lamp 7, it may be output to another control device or display device, and the result of failure diagnosis can be communicated to another control device or display device. Can communicate. Moreover, the result of failure diagnosis can be stored in the storage device.
[0038]
As described above, according to this embodiment, since the watchdog timer can be diagnosed without switching the reset signal, even if the CPU runs out of control during the diagnosis, the watchdog timer should be normal. If it is, it can return reliably.
[0039]
【The invention's effect】
According to the present invention, the diagnosis of the watchdog timer is performed without switching the reset signal to the port, so that even if the CPU runs out of control during the diagnosis, the watchdog timer can be restored if it is operating normally. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram illustrating a configuration of an electronic control device according to an embodiment of the present invention.
FIG. 2 is a time chart showing an operation of the watchdog timer in a normal state in the electronic control device according to the embodiment of the present invention.
FIG. 3 is a time chart showing an operation when the watchdog timer is abnormal in the electronic control device according to the embodiment of the present invention;
FIG. 4 is a flowchart showing a control operation of the electronic control device according to the embodiment of the present invention.
[Explanation of symbols]
1 ... Electronic control unit 2 ... CPU
3 ... Watchdog timer 4 ... Power supply circuit 5 ... EEPROM
6 ... Warning lamp driver 7 ... Warning lamp 8 ... Power switch 9 ... Power supply

Claims (4)

In an electronic control device having a microcomputer and a watchdog timer for detecting an abnormal state of the microcomputer based on a program running signal from the microcomputer,
When the program running signal supplied from the microcomputer to the watchdog timer is stopped, the microcomputer determines whether or not the watchdog timer has reset the microcomputer. An electronic control device characterized by performing failure diagnosis of a dog timer. The electronic control device according to claim 1,
The electronic control device, wherein the microcomputer determines whether or not the watchdog timer has performed a reset operation using data written in a storage device. The electronic control device according to claim 2,
The electronic control device, wherein the data written to the storage device is written to the storage device before the program running signal is stopped. The electronic control device according to claim 1,
The microcomputer determines whether or not the watchdog timer has performed a reset operation by determining that the microcomputer does not reset during a specified period after the stop of the program running signal. apparatus.

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