JP2005019584A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device capable of providing an extension region with good positional accuracy in a trench gate structure and a method for manufacturing the same are provided.
A side wall 5 is provided on a side wall of a groove 3a formed in a semiconductor substrate 3, and a gate insulating film 9 is provided at the bottom of the groove 3a exposed from the side wall 5 in the groove 3a. A gate electrode 11 is embedded. The surface layer of the semiconductor substrate 3 is provided with a source S / drain D disposed opposite to the gate electrode 11 via the sidewall 5, and a channel forming portion below the source S / drain D and the gate insulating film 9. A low-concentration diffusion layer 15 formed by impurity diffusion from the side wall 5 to the semiconductor substrate 3 is provided between A and A.
[Selection] Figure 1

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a trench gate type MOS transistor in which a buried gate electrode is provided in a trench on a substrate surface and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the demand for higher integration and higher functionality of semiconductor devices, element structures have been miniaturized. Under such circumstances, in a semiconductor device having a conventional structure (so-called MOS transistor) in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, a short channel effect (for example, a punch-through phenomenon) that becomes conspicuous by miniaturization, Limitation by increasing the impurity concentration or reducing the thickness of the gate insulating film has become a limit.
[0003]
Therefore, a semiconductor device having a structure in which a gate electrode is embedded in a groove formed in a surface layer of a semiconductor substrate to form a groove gate type has been proposed. Hereinafter, an example of a method for manufacturing a trench gate type semiconductor device will be described with reference to FIG. First, as shown in FIG. 5A, after forming a first diffusion layer 102 to be a source / drain on the surface layer of the semiconductor substrate 101, a groove 103 is formed on the surface side of the first diffusion layer 102. Next, as shown in FIG. 5B, after a through film 104 made of silicon oxide is formed on the inner wall of the groove 103, a second diffusion layer 105 serving as an extension region is formed at the bottom of the groove 103 by ion implantation. The first diffusion layer 102 is formed continuously at a position deeper than the diffusion layer 102. The second diffusion layer 105 has the same conductivity type as the first diffusion layer 102 and has a lower concentration than the first diffusion layer 102. Further, after the formation of the second diffusion layer 105, the through film 104 is removed. Next, as shown in FIG. 5 (3), an insulating side wall 106 is formed on the side wall of the groove 103, and then the bottom of the groove 103 exposed from the side wall 106 is about the same as the second diffusion layer 105. Delve into As a result, the first diffusion layer 102 and the second diffusion layer 105 are separated to form the source S / drain D, and an extension region 105a continuous to the source S / drain D is formed. Thereafter, as shown in FIG. 5D, the gate insulating film 107 is formed so as to cover the exposed surface of the trench 103 dug down, and then the conductive film is buried in the trench 103 to form the gate electrode 108.
[0004]
As described above, a semiconductor device in which the extension region 105a having a lower concentration than the source S / drain D is provided between the source S / drain D and the channel formation portion A under the gate insulating film 107 is obtained. In this semiconductor device, the short channel effect is suppressed by the extension region 105a.
[0005]
[Problems to be solved by the invention]
However, in the semiconductor device configured as described above, the second diffusion layer serving as the extension region is formed by ion implantation through the through film. For this reason, the formation position and depth of the extension region are affected by the thickness of the through film and the energy of ion implantation, and it is difficult to form the extension region at an accurate position and depth with respect to the design value. This is a factor that hinders high integration and high speed of the trench gate type semiconductor device.
[0006]
Accordingly, an object of the present invention is to provide a semiconductor device capable of providing an extension region with good positional accuracy in a trench gate structure and a manufacturing method thereof.
[0007]
[Means for Solving the Problems]
In order to achieve such an object, the semiconductor device of the present invention has a sidewall provided on a sidewall of a groove formed in a semiconductor substrate, and a gate insulating film provided on the bottom of the groove exposed from the sidewall. Thus, a gate electrode is embedded in the trench. The surface layer of the semiconductor substrate is provided with a source / drain disposed opposite to the gate electrode through the sidewall, and further between the source / drain and the channel formation portion below the gate insulating film, the sidewall is provided. A low concentration diffusion layer formed by impurity diffusion from the semiconductor substrate to the semiconductor substrate is provided.
[0008]
In the semiconductor device described above, the sidewall may be a conductive material. In this case, an insulating sidewall is provided on the sidewall of the groove via the sidewall.
[0009]
In the semiconductor device having such a configuration, the low-concentration diffusion layer is formed by impurity diffusion from the sidewall to the semiconductor substrate, so that the low-concentration diffusion layer has a degree of impurity diffusion from the sidewall. It is formed at the position and depth with only the factor as the factor.
[0010]
A method for manufacturing a semiconductor device is performed as follows. First, after forming a trench in the surface layer of the semiconductor substrate and forming a sidewall containing impurities on the sidewall of the trench, a gate insulating film is formed at the bottom of the trench, and a gate electrode is embedded in the trench. In such a process, a first diffusion layer serving as a source / drain is formed on the surface layer of the semiconductor substrate so as to be shallower than the formation position of the gate insulating film before the trench is formed or after the gate electrode is buried. . In addition, after forming the sidewall, a step of diffusing impurities in the sidewall into the semiconductor substrate to a position deeper than the first diffusion layer to form the second diffusion layer is performed.
[0011]
In the above manufacturing method, the sidewall may be made of a conductive material. In this case, after the sidewall is formed on the sidewall of the groove, the sidewall is insulated through the sidewall before the gate electrode is embedded. Forming a conductive sidewall.
[0012]
In such a manufacturing method, the second diffusion layer deeper than the first diffusion layer is formed by impurity diffusion from the sidewall formed on the sidewall of the groove. Here, since the first diffusion layer is formed at a depth not exceeding the gate insulating film at the bottom of the trench, the second diffusion layer is formed so as to be positioned between the first diffusion layer and the gate insulating film. Will be. The depth is adjusted only by the degree of impurity diffusion from the sidewall.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0014]
<Semiconductor device>
FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention. The semiconductor device 1 shown in this figure is a trench gate type semiconductor device, and a trench 3a is provided in a surface layer of a semiconductor substrate 3 made of, for example, p-type single crystal silicon. The groove 3a is provided with a width of about 20 nm to 100 nm corresponding to the gate length and a depth of about 50 nm to 150 nm which is the junction depth of the source / drain. Although not shown here, when the semiconductor device 1 is a p-channel type, an n-well diffusion layer is provided on the surface layer of the semiconductor substrate 3, and the groove 3a and the following description will be given. Each member to be provided is provided in the n-well diffusion layer.
[0015]
A sidewall 5 is provided on the inner wall of the groove 3a. The sidewall 5 may be conductive or insulative as long as the semiconductor substrate 3 contains a diffusible impurity. The impurities contained in the sidewall 5 are n-type impurities such as phosphorus (P) and arsenic (As) if the semiconductor device 1 is an n-channel type, and boron (B) if the semiconductor device 1 is a p-channel type. Such p-type impurities are used.
[0016]
When the sidewall 5 is insulative, PSG (phosphorous silicate glass) or AsSG (arsenic glass) is used as a material containing n-type impurities. Alternatively, BPSG (boron phosphorus silicate glass) may be used on condition that the content of phosphorus (P) as an n-type impurity is higher than the content of boron (B) as a p-type impurity. Similarly, when the sidewall 5 is insulative, BSG (boron silicate glass) is used as the material containing p-type impurities, and the content of boron (B) as p-type impurities is n-type impurities. BPSG (boron phosphorus silicate glass) may be used on condition that the content is higher than the content of certain phosphorus (P).
[0017]
On the other hand, when the sidewall 5 is conductive, the above-described silicon film or metal film containing the p-type impurity or the n-type impurity is used.
[0018]
When the sidewall 5 is made of a conductive material, it is assumed that the insulating sidewall 7 is further provided so as to cover the sidewall 5. When the insulating sidewall 7 is provided, it is preferable that the insulating sidewall 7 also contains an impurity that can be diffused in the semiconductor substrate 3. As a result, the formation position of the low-concentration diffusion layer 15 described below is prevented from varying due to variations in the film thickness of the insulating sidewall 7. In this case, the insulating side wall 7 is formed of the same material as the case where the side wall 5 described above is insulative. Further, the insulating sidewall 7 may not contain impurities. In this case, the insulating sidewall 7 is formed of any one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.
[0019]
Although the case where the insulating sidewall 7 is provided is illustrated in the drawings, as described above, it is not necessary to provide the insulating sidewall 7 when the sidewall 5 is insulating. Further, the sidewalls 5 and 7 are not limited to the one-layer or two-layer structure, and have a multilayer structure of three or more layers as long as the sidewall located at the center of the groove 3a is insulative. Also good. In the case of a multilayer structure of three or more layers, it is preferable that impurities are contained in each layer.
[0020]
A gate insulating film 9 is provided on the bottom surface of the trench 3a exposed from the sidewalls 5 and 7 described above. As the gate insulating film 9, any of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a high dielectric constant insulating film (so-called High-k film), or the like can be used. As the high dielectric constant insulating film, aluminum oxide, hafnium oxide, zirconium oxide or an oxide thereof, a laminated film thereof, or an oxide obtained by adding silicon to these alloys is used. .
[0021]
A gate electrode 11 is embedded in the trench 3 a whose inner wall is covered with the sidewalls 5 and 7 and the gate insulating film 9. This gate electrode 11 is formed by embedding a polysilicon film, a laminated film of a polysilicon film and a silicide film, a laminated film of a polysilicon film and a metal film, or a metal film.
[0022]
In addition, a source S / drain D is provided on the surface layer of the semiconductor substrate 3 so as to be opposed to the gate electrode via the side walls 5 and 7. The source S / drain D is a layer in which an n-type impurity is diffused if the semiconductor device 1 is an n-channel type, and a p-type impurity is diffused if the semiconductor device 1 is a p-channel type, and does not exceed the gate insulating film 9. It is assumed that the depth is provided, that is, a depth shallower than the depth of the groove 3a here.
[0023]
A low-concentration diffusion formed by impurity diffusion from the sidewall 5 between the source S / drain D and the channel formation portion A of the semiconductor device 1 formed below the gate insulating film 9. Layer 15 is provided. This low-concentration diffusion layer 15 is a so-called extension region, and it is assumed that impurities of the same conductivity type as the source S / drain D are diffused at a low concentration. When the insulating side wall 7 is provided and the insulating side wall 7 contains impurities, the low concentration diffusion layer 15 is diffused by impurity diffusion from the side walls 5 and 7. It may be formed. This prevents variations in the formation position of the low-concentration diffusion layer 15 with respect to the gate insulating film 9 due to variations in the film thickness of the insulating sidewall 7.
[0024]
In the case where the insulating sidewall 7 is provided and the insulating sidewall 7 does not contain impurities, the gate insulating film 9 is formed between the insulating sidewall 7 and the semiconductor substrate 3. It may be erected up to the middle. However, the portion that actually functions as the gate insulating film 9 is a portion sandwiched between the gate electrode 11 and the semiconductor substrate 30.
[0025]
In the semiconductor device 1 having such a configuration, an inversion layer region (so-called channel) is formed in the channel formation portion A under the gate insulating film 9 by applying a voltage to the gate electrode 11. Since this channel is in contact with the low-concentration diffusion layer 15 formed as an extension region, it operates exactly the same as a conventional transistor. The current path is as follows: source D → source D low concentration diffusion layer 15 → channel forming portion A → drain D low concentration diffusion layer 15 → drain D. In this case, if the sidewall 5 is conductive, the source S → the side wall 5 on the source S side → the low concentration diffusion layer 15 on the source S side → the channel formation portion A → the low concentration diffusion layer 15 on the drain D. → The side wall 5 on the drain D side → the current path of the drain D is also created.
[0026]
In the semiconductor device 1 having the above-described configuration, the low concentration diffusion layer 15 is formed by impurity diffusion from the sidewalls 5 and 7 to the semiconductor substrate 3. It can be formed at a position and a depth based only on the degree of diffusion of impurities from the side walls 5 and 7. Therefore, the semiconductor device 1 including the low concentration diffusion layer 15 with better positional accuracy can be obtained.
[0027]
<Semiconductor device-2>
FIG. 2 shows a modification of the semiconductor device of the present invention. The difference between the semiconductor device 20 shown in this figure and the semiconductor device 1 shown in FIG. 1 is provided with a recess 21 in which the bottom of the groove 3a provided with the sidewalls 5 and 7 is further deeply cut. The gate insulating film 9 is provided so as to cover the inner wall of the substrate 21, and the other configurations are the same.
[0028]
Even in the semiconductor device 20 having such a configuration, the low concentration diffusion layer 15 between the source S / drain D and the channel formation portion A is formed by impurity diffusion from the sidewalls 5 and 7 to the semiconductor substrate 3. Therefore, like the semiconductor device 1 shown in FIG. 1, the semiconductor device 1 including the low concentration diffusion layer 15 with better positional accuracy can be obtained.
[0029]
Even in the semiconductor device 20 having such a configuration, the depth of the source S / drain D may be a depth that does not exceed the gate insulating film 9, for example, as indicated by a two-dot chain line in the figure. Further, the source S / drain D may reach a position deeper than the sidewalls 5 and 7.
[0030]
<Semiconductor Device Manufacturing Method-1>
Next, a method for manufacturing a semiconductor device according to the present invention will be described by taking an example of manufacturing a semiconductor device having the structure described with reference to FIG.
[0031]
First, as shown in FIG. 3A, a groove 3a is formed in a surface layer of a semiconductor substrate 3 made of, for example, p-type single crystal silicon. The groove 3a is formed in the predetermined shape described above using a lithography technique and an anisotropic etching technique.
[0032]
Next, as shown in FIG. 3B, the sidewall 5 containing the above-described impurities is formed on the sidewall of the groove 3a. At this time, first, after forming a material film containing an impurity having a film thickness of about 5 nm to 30 nm so as to cover the inner wall of the groove 3a, the material film is etched back so that the material film is formed only on the side wall of the groove 3a. The material film on the surface of the semiconductor substrate 3 and the bottom surface of the groove 3a is removed. Thereby, the sidewall 5 made of the material film is formed. The impurities contained in the sidewall 5 may be contained in the material film at the same time as the film formation by adding impurities to the film forming gas of the material film. On the other hand, a procedure for diffusing impurities later may be used. In the case where impurities are diffused later on the material film, it is preferable to prevent the impurities from diffusing into the semiconductor substrate 3 by diffusing the impurities before etching back the material film.
[0033]
Next, a process of forming the insulating sidewall 7 is performed as necessary. The insulating sidewalls 7 are formed in the same manner as the sidewalls 5 are formed.
[0034]
Subsequently, as shown in FIG. 3C, a gate insulating film 9 having a thickness of, for example, about 1 nm is formed so as to cover the lower portion of the groove 3a in which the sidewalls 5 and 7 are formed. Here, the gate insulating film 9 may be formed on the bottom surface of the groove 3a by thermal oxidation, or the gate insulating film 9 integrated into a shape covering the entire inner wall of the groove 3a may be formed.
[0035]
Next, a gate electrode 11 is embedded in the trench 3a. At this time, first, a single-layer or multilayer gate electrode material film is formed on the semiconductor substrate 3 until the inside of the groove 3a is buried, and then the gate electrode material film is formed only in the groove 3a by CMP, dry etching, wet etching, or the like. And the gate electrode material film on the semiconductor substrate 3 is removed. Thereby, the gate electrode 11 is formed by leaving the gate electrode material film in the trench 3a.
[0036]
Thereafter, as shown in FIG. 3 (4), impurities of a predetermined conductivity type are introduced into the surface layer of the semiconductor substrate 3 to form the first diffusion layer 13 that becomes the source S / drain D. Here, ion implantation with adjusted acceleration voltage is performed so that impurities are introduced at a depth not exceeding the depth of the gate insulating film 9 to form the first diffusion layer 13.
[0037]
Thereafter, as shown in FIG. 3 (5), by performing the heat treatment at a high temperature of about 1000 ° C., the impurities in the sidewalls 5 are diffused into the semiconductor substrate 3 to form a low concentration diffusion layer (so-called extension region). The second diffusion layer 15 is formed. At this time, in the case where the insulating sidewall 7 is provided, and the impurity is contained in the insulating sidewall 7, the impurity is diffused also from the insulating sidewall 7 and the first side wall is diffused. Two diffusion layers 15 are formed. At this time, impurities in the source S / drain D may diffuse under the side walls 5 and 7 through the side walls 5 and 7.
[0038]
Further, by this heat treatment, the impurities in the second diffusion layer 15 in the first diffusion layer 13 are activated, and the source S / drain D and the low concentration diffusion layer 15 made of the first diffusion layer 13 are formed.
[0039]
As described above, the semiconductor device 1 having the configuration described with reference to FIG. 1 can be obtained.
[0040]
In such a manufacturing method, the low concentration diffusion layer 15 between the source S / drain D and the channel forming part A is formed by impurity diffusion from the side walls 5 and 7 formed on the side wall of the groove 3a. Therefore, the low-concentration diffusion layer 15 can be formed to a predetermined depth with good control depending on the degree of impurity diffusion from the sidewalls 5 and 7. Further, when the insulating sidewall 7 is provided and the insulating sidewall 7 contains impurities, the low concentration diffusion layer 15 is formed by impurity diffusion from the sidewalls 5 and 7. It becomes. Thereby, even when the insulating sidewall 7 is provided, it is possible to prevent the formation position of the low-concentration diffusion layer 15 with respect to the gate insulating film 9 from being varied due to the variation in the film thickness.
[0041]
In the manufacturing method described above, the impurity diffusion for forming the low-concentration diffusion layer 15 is performed by using the sidewall 5 (or the insulating sidewall 7 in some cases) as described with reference to FIG. After the formation, it may be before the gate insulating film 9 is formed or before the gate electrode 11 is formed.
[0042]
Further, in the case where the insulating sidewall 7 is provided and it is not necessary to diffuse impurities from the insulating sidewall 7 to the semiconductor substrate 3, after the sidewall 5 is formed, the above-described operation is performed. The procedure of forming the gate insulating film 9 and then forming the insulating sidewall 7 may be used.
[0043]
In the case of forming the semiconductor device having the structure described with reference to FIG. 2, after the sidewall 5 is formed as described with reference to FIG. 3B, before the gate insulating film 9 is formed. Further, a step of further dug down the exposed bottom portion of the groove 3a to form a recess is added. When the first diffusion layer 13 is formed, the first diffusion layer 13 may be formed deeper than the groove 13a as long as it is shallower than the gate insulating film 9 formed at the bottom of the recess. However, in this case, before the ion implantation for forming the first diffusion layer 13 is performed, the low-concentration diffusion layer (second diffusion layer) 15 is formed by impurity diffusion from the sidewall 5 to thereby form the first diffusion layer 13. It is important to form the low concentration diffusion layer 15 deeper than the diffusion layer 13.
[0044]
<Semiconductor Device Manufacturing Method-2>
Next, a second example of the method for manufacturing a semiconductor device according to the present invention will be described by taking an example of manufacturing a semiconductor device having the configuration described with reference to FIG.
[0045]
First, as shown in FIG. 4A, a first conductivity impurity is introduced into the entire surface layer of a semiconductor substrate 3 made of, for example, p-type single crystal silicon, thereby forming a source S / drain D. The diffusion layer 13 is formed. Here, ion implantation with adjusted acceleration voltage is performed so that impurities are introduced at a depth not exceeding the depth of a gate insulating film to be formed later to form the first diffusion layer 13.
[0046]
Next, as shown in FIG. 4 (2), a groove 3 a is formed in the semiconductor substrate 3. The groove 3a is formed in the predetermined shape described above using a lithography technique and an anisotropic etching technique. Further, a groove 3a having a depth equal to or greater than that of the first diffusion layer 13 is formed.
[0047]
Next, as shown in FIG. 4 (3), the sidewall 5 containing the above-mentioned impurities is formed on the sidewall of the groove 3a, and the insulating sidewall 7 is further formed as necessary. This step is performed in the same manner as described with reference to FIG. 3B in the first example of the previous manufacturing method.
[0048]
Subsequently, as shown in FIG. 4D, a gate insulating film 9 and a gate electrode 11 are formed. This step is performed in the same manner as described in the first example of the previous manufacturing method with reference to FIG.
[0049]
Thereafter, as shown in FIG. 4 (5), the second diffusion layer to be the low concentration diffusion layer 15 is formed by diffusing impurities in the sidewall 5 and further the insulating sidewall into the semiconductor substrate 3. A source S / drain D in which impurities in the first diffusion layer 13 are activated is formed. This step is performed in the same manner as described with reference to FIG. 3C in the first example of the previous manufacturing method.
[0050]
As described above, the semiconductor device 1 having the configuration described with reference to FIG. 1 can be obtained.
[0051]
Even in such a manufacturing method, the low concentration diffusion layer 15 between the source S / drain D and the channel forming portion A is formed by impurity diffusion from the side walls 5 and 7 formed on the side wall of the groove 3a. The Therefore, the low-concentration diffusion layer 15 can be formed to a predetermined depth with good control depending on the degree of impurity diffusion from the sidewalls 5 and 7.
[0052]
In the manufacturing method described above, the impurity diffusion for forming the low-concentration diffusion layer 15 is performed using the sidewall 5 (or the insulating sidewall 7 in some cases) as described with reference to FIG. After the formation, it may be before the gate insulating film 9 is formed or before the gate electrode 11 is formed.
[0053]
Further, in the case where the insulating sidewall 7 is provided and it is not necessary to diffuse impurities from the insulating sidewall 7 to the semiconductor substrate 3, after the sidewall 5 is formed, the above-described operation is performed. The procedure of forming the gate insulating film 9 and then forming the insulating sidewall 7 may be used.
[0054]
In the case of forming the semiconductor device having the structure described with reference to FIG. 2, after the sidewall 5 is formed as described with reference to FIG. 4 (3), before the gate insulating film 9 is formed. Further, a step of further dug down the exposed bottom portion of the groove 3a to form a recess is added. However, even in this case, by forming the first diffusion layer 13 so as to be shallower than the groove 3a, the sidewalls 5 and 7 formed on the side wall of the groove 3a are deeper than the first diffusion layer 13. It is important that the low-concentration diffusion layer 15 due to impurity diffusion from the sidewall 5 is deeper than the first diffusion layer 13.
[0055]
【The invention's effect】
As described above, according to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, in the semiconductor device having the trench gate structure, the low-concentration diffusion layer disposed between the source / drain and the channel forming portion is disposed on the sidewall of the trench. Thus, it is possible to provide a low-concentration diffusion layer serving as an extension region with good positional accuracy in the trench gate structure. As a result, it is possible to achieve high integration and high speed of the trench gate type semiconductor device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view showing another configuration of the semiconductor device of the present invention.
FIG. 3 is a cross-sectional process diagram illustrating a first example of a method of manufacturing a semiconductor device according to the present invention.
FIG. 4 is a cross-sectional process diagram illustrating a second example of a method of manufacturing a semiconductor device according to the present invention.
FIG. 5 is a manufacturing process diagram of a conventional semiconductor device having a trench gate structure;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,20 ... Semiconductor device, 3 ... Semiconductor substrate, 3a ... Groove, 5 ... Side wall, 7 ... Insulating side wall, 9 ... Gate insulating film, 11 ... Gate electrode, 13 ... 1st diffused layer, 15 ... Low concentration Diffusion layer (second diffusion layer), A ... channel forming portion, S ... source, D ... drain

Claims (6)

A semiconductor substrate having grooves formed thereon;
A sidewall provided on the sidewall of the groove;
A gate insulating film provided at the bottom of the trench exposed from the sidewall, and a gate electrode embedded in the trench via the sidewall and the gate insulating film;
A source / drain disposed opposite to the gate electrode on the surface layer of the semiconductor substrate via the sidewall;
A low-concentration diffusion layer provided between the source / drain and a channel formation portion below the gate insulating film,
The semiconductor device, wherein the low-concentration diffusion layer is formed by impurity diffusion from the sidewall to the semiconductor substrate. The semiconductor device according to claim 1,
The sidewall is made of a conductive material,
An insulating sidewall is provided on the sidewall of the groove via the sidewall. The semiconductor device according to claim 2,
The semiconductor device, wherein the low concentration diffusion layer is formed by impurity diffusion from the sidewall and the insulating sidewall to the semiconductor substrate. A first step of forming grooves in the surface layer of the semiconductor substrate;
A second step of forming a side wall containing impurities on the side wall of the groove;
A third step of forming a gate insulating film at the bottom of the trench in which the sidewall is formed;
A fourth step of embedding and forming a gate electrode in the trench in which the gate insulating film is formed;
A fifth step of forming a first diffusion layer serving as a source / drain on the surface layer of the semiconductor substrate before the first step or after the fourth step so as to be shallower than the formation position of the gate insulating film; ,
And a sixth step of forming a second diffusion layer by diffusing impurities in the sidewall into the semiconductor substrate to a position deeper than the first diffusion layer after the second step. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 4,
The sidewall is made of a conductive material,
A method of manufacturing a semiconductor device, comprising performing a step of forming an insulating sidewall on the side wall of the groove via the sidewall after the second step and before the fourth step. In the manufacturing method of the semiconductor device according to claim 4,
Between the second step and the third step, performing a step of forming an insulating sidewall on the sidewall of the groove via the sidewall,
After the third step, the second diffusion layer is formed by diffusing impurities in the sidewall and the insulating sidewall to a position deeper than the first diffusion layer in the semiconductor substrate. A method for manufacturing a semiconductor device.

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