JP2005018187A - Recording medium for logic description data, development method for semiconductor device, and logic simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate the acquisition of logic description data capable of making a logic design reflect the control of supply/shutoff of operation power to a circuit block and substrate bias control. <P>SOLUTION: This recording medium (1) records the logic description data on a circuit module which a computer (2) can read and use for the logic design. The logic description data include the logic description of a substrate bias controller, logic description of a power switch, and logic description of a controlled block connected to them, as the circuit block constituting the circuit module. The logic description of the power switch includes first delay time information (d1), (d2) meaning a switch operation delay. The logic description of the substrate bias controller includes second delay time information (d3) meaning a delay by substrate bias. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention uses logic description data of a circuit module having a circuit block capable of selectively receiving power shutdown and substrate bias control, a semiconductor device development method using such logic description data, and logic description data. For example, the present invention relates to a technique effective when applied to the development of a semiconductor integrated circuit.
[0002]
[Prior art]
In today's semiconductor device field, where low power consumption is important, it is a good idea to consider the power supply system circuit at the logic design stage of the semiconductor device. From this point of view, there is provided a simulation method capable of controlling output delay and output high impedance according to on / off control of a power switch of a circuit block (Patent Document 1). From the same point of view, a logic simulation is performed on a circuit having a power supply terminal as a logic terminal in a standard cell, and having logic information or delay information in the function information of the power supply terminal, and having a power supply and supply stop control function. There is a technology that enables this (Patent Document 2).
[0003]
[Patent Document 1]
Japanese Patent Laying-Open No. 2002-259487 (FIG. 4)
[Patent Document 2]
JP 2000-305961 A (FIGS. 3 and 4)
[0004]
[Problems to be solved by the invention]
Substrate bias control can be employed to suppress wasteful power consumption due to subthreshold read. The present inventor has found that it is indispensable to improve the reliability of the simulation result to verify the influence of the operation power supply / shut-off control and the substrate bias control in the logic simulation stage. To that end, earnestly studying how to make it possible to handle and evaluate the effects of supply / shutdown control of the operating power supply and substrate bias control at the stage of logic design and logic simulation, leading to the present invention. did it.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a logical description data recording medium capable of facilitating the acquisition of logical description data capable of reflecting the supply / cutoff of operation power to the circuit block and the substrate bias control in the logical design. It is to provide.
[0006]
Another object of the present invention is to provide a simulation method capable of performing logic verification in consideration of control of supply / cutoff of operation power to a circuit block and substrate bias control.
[0007]
Another object of the present invention is to provide a semiconductor device development method that can contribute to improving the reliability of a semiconductor device oriented to low power consumption by controlling supply / cutoff of an operating power supply to a circuit block and substrate bias control. There is.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
[1] The recording medium (1) records logic description data of circuit modules that can be read by the computer (2) and used for logic design. The logic description data includes a logic description of a substrate bias controller (VBB), a logic description of a power switch (PSW), and a logic description of a controlled block (blk23) connected thereto as circuit blocks constituting the circuit module. . The logical description of the power switch includes first delay time information (d1, d2) that means a delay of the switch operation. The logical description of the substrate bias controller includes second delay time information (d3) indicating a delay due to the substrate bias.
[0011]
By adding delay information of operation due to power shutoff or substrate bias application by the power supply system to the logic description data, control of supply / shutoff of operation power to the circuit block and substrate bias control can be reflected in the logic design. . Since such logical description data is provided by being recorded on a recording medium, such logical design can be easily performed. In the logic design using the logic description data, a gate level logic circuit can be obtained by using a logic synthesis tool corresponding to the description language of the logic description data. Further, a logic simulation can be performed on a logic-designed circuit by using a net list and input pattern data of the logic circuit specified by the logic description data.
[0012]
As a specific form of the present invention, in such a logic design, the first delay time information is set to an indefinite value at the terminal of the controlled block that causes the computer that has read the logic description data to be turned off by the power switch. The delay time (d1) until the computer releases the indefinite value of the terminal of the controlled block that reaches the power supply by the power switch can be defined. Due to the delay time of the power shut-off operation, the logic state when the power is turned off can be easily realized including the transition, and an accurate logic simulation when the power is turned off becomes possible. Due to the delay time of the power supply restarting operation, a logic state can be accurately realized in consideration of a delay caused by a transition from a power-off state to an on-state, and such a logic simulation is also possible.
[0013]
Further, the second delay time information can define a delay time until the computer that has read the logic description data sets the terminal of the controlled block to which the substrate bias is applied by the substrate bias controller to an indefinite value. Further, the second delay time information can define an operation delay time when the computer reading the logic description data changes the internal signal state with respect to the controlled block in the substrate bias state by the substrate bias controller. . Substrate bias delay time allows the logic state to be realized for any state where the input to the controlled block in the substrate bias application state is valid or the input is ignored, and accurate logic considering such a state Simulation is also possible. Since the logic state in which the input by the event is valid in the substrate bias applied state and the logic state in which the input is ignored can be arbitrarily selected, it is possible to narrow down the detection of the faulty part of the logic due to the leak in the logic simulation.
[0014]
The controlled block is not limited to a logic circuit, and may be a memory circuit or both.
[0015]
[2] The recording medium can be applied to the development of semiconductor devices. That is, the logical description data is read from the recording medium. The logic design of the semiconductor device is performed using the read logic description data. The logic simulation of the semiconductor device logically designed is performed using the read logic description data.
[0016]
The process of performing the logic simulation includes adding a delay time of a power shut-off operation in the first delay time when an event for shutting off the power of the controlled block occurs, When the process for setting an indefinite value (S13, S12) and an event for restarting power supply to a controlled block that is powered off occur, the delay time of the power supply restart operation is added in the first delay time. Processing for canceling the indeterminate value of the terminal of the controlled block to be released from the power shutdown (S6, S7), and when the controlled block where the event has occurred is a substrate bias application target, the second delay time is included in the event When an input due to an event is ignored for the controlled block, an undefined value is further set to the terminal of the controlled block. S10, including S12 and), the.
[0017]
In the simulation process, it is desirable to be able to select whether to enable or ignore input by an event for the controlled block.
[0018]
By the above development method, logic design and logic verification can be performed in consideration of the control / supply cutoff of the operation power to the circuit block and the substrate bias control, and the low power consumption by the control / supply cutoff of the operation power and the substrate bias control. It can contribute to the improvement of the reliability of the semiconductor device oriented to electric power.
[0019]
[3] Another aspect of the present invention from the viewpoint of logic simulation is that a logic simulation is performed using the logic description data for a circuit block that can be selectively subjected to power shutdown and substrate bias control. It is. That is, when an event for shutting off the power of the circuit block occurs, a process for adding a delay time of the power shut-off operation and setting an indeterminate value to the terminal of the circuit block to be shut off, and a circuit block that is shut off When an event for resuming power supply occurs, a delay time of the power supply resuming operation is added to cancel the indeterminate value of the terminal of the circuit block that is released from the power shutoff, and the circuit block where the vent occurs is the substrate bias When it is an application target, a delay time for substrate bias is added to the event, and when an input due to the event is ignored for the controlled block, an undefined value is further set to the terminal of the controlled block. Including.
[0020]
Due to the delay time of the power shut-off operation, an accurate logic simulation when the power is turned off becomes possible. The logic simulation considering the delay due to the transition from the power-off state to the on-state becomes possible by the delay time of the power supply restart operation. The substrate bias delay time enables accurate logic simulation in consideration of the logic state when the substrate bias is applied. Since it is possible to realize a logic state that is indefinite with the state in which the internal node is held in the substrate bias application state, it is possible to narrow down detection of a logic defect due to a leak in the logic simulation.
[0021]
When input by an event is validated for a controlled block in a substrate bias application state, the substrate bias delay time is accumulated every time an input event occurs for the controlled block. The delay time of the power shutoff operation, the delay time of the power supply restart operation, and the delay time for substrate bias are information defined in the logic description data.
[0022]
According to the simulation method, logic verification can be performed in consideration of control of supply / cutoff of operation power to the circuit block and substrate bias control.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example of a recording medium for logical description data according to the present invention. The recording medium 1 records logic description data of circuit modules that can be read by the computer 2 and used for logic design.
[0024]
The recording medium 1 is, for example, a CD-ROM (compact disk-read only memory), CD-RW, DVD-ROM (digital video disk-ROM) optically readable by a disk drive 3 of a computer 2. DVD-RAM (digital video disk-random access memory). Alternatively, the magnetic disk or PC card of a hard disk device connected via an interface such as IDE (Integrated Disk Electronics) or ATAPI (AT Attachment Packet Interface) built in or externally attached to the computer 2 It may be a flash memory card of various standards, a flexible disk, a magnetic tape, or a memory device such as a ROM or a RAM mounted on a computer internal circuit.
[0025]
The logical description data is configured by a functional description such as RTL (register transfer level) using, for example, HDL (hardware description language).
[0026]
The description content of FIG. 1 corresponds to the circuit-like hierarchical structure of FIG. In FIG. 2, the highest layer is a chip CHP, that is, the entire semiconductor device (semiconductor integrated circuit). The chip CHP includes an input / output circuit I / O and three blocks blk0, blk1, and blk2. The block blk2 is hierarchized into lower-level blocks blk21 and blk22. The blocks blk1, blk21, and blk22 are operated by mutually inputting and outputting signals, and each constitutes a circuit module. The block blk0 is a constantly energized block having the power supply control circuit 4. The blocks blk1, blk21, and blk22 are circuits that receive power supply cutoff control and substrate bias control by the power supply control circuit 4. Although not particularly limited, the power cutoff control is individually performed for each of the blocks blk1, blk21, and blk22, and the substrate bias control is commonly performed for each of the blocks blk1, blk21, and blk22.
[0027]
The block blk22 includes a substrate bias controller VBB, a power switch PSW, and a vdd system block (controlled block blk23). The substrate bias controller VBB receives the substrate bias control signal BB supplied from the power supply control circuit 4 and controls the substrate bias of the controlled block blk23. The power switch PSW receives the power control signal CL supplied from the power control circuit 4 and performs power cutoff control of the controlled block blk23. The controlled block blk23 is connected to the blocks blk1 and blk21 and performs a logic operation or a memory operation.
[0028]
The controlled block blk23 has an inverter and an AND gate as shown representatively, performs a logical operation on the inputs i1 and i2, and obtains the result as an output o.
[0029]
The logical description data in FIG. 1 is a set of logical descriptions in units of a prefix module and a suffix endmodule, and the circuit structure in FIG. 2 is hierarchically defined according to HDL predetermined linguistic grammar. For example, a description part indicated by 5 in FIG. 1 is a logical description for the block blk22, and a description of the block blk23, the substrate bias controller VBB, and the power switch PSW follows the definition for the input input and the output output. In the description line of the substrate bias controller VBB, V2 is an identifier with respect to another substrate bias controller VBB, and indicates that the substrate bias control signal BB is input to the input terminal i. In the description line of the power switch PSW, V3 is an identifier with respect to the other power switch PSW, and indicates that the power control signal CL is input to the input terminal i.
[0030]
The description portion indicated by 6 in FIG. 1 is a logical description for the controlled block blk23 that is controlled by the substrate bias controller VBB and the power switch PSW. The description portion indicated by 7 in FIG. 1 is a logical description for the substrate bias controller VBB, and includes a description DEL1 = d3 regarding the second delay time information d3 which means a delay due to the substrate bias. The description portion indicated by 8 in FIG. 1 is a logical description for the power switch PSW, and includes descriptions DEL1 = d1 and d2 relating to first delay time information d1 and d2 that mean switch operation delay. d1 means an operation delay time when the power is cut off, and d2 means a delay time when the power supply is resumed.
[0031]
In FIG. 1, descriptions other than the delay time are omitted in the logic description portion 7 of the substrate bias controller VBB and the logic description portion 8 of the power switch PSW, but the omitted logic description contents are illustrated by the gate structure of FIG.
[0032]
In FIG. 3, a CMOS inverter including a p-channel MOS transistor Mp and an n-channel MOS transistor Mn is illustrated as the block blk23.
[0033]
In FIG. 3, the substrate bias controller VBB selects the substrate bias voltages vbp and vbn according to the logical value “1” of the substrate bias control signal BB, and the power supply voltages vdd and vss according to the logical value “0” of the substrate bias control signal BB. There are switch circuits SW1 and SW2 that select and apply the selected voltage to the base gates (well regions) of the MOS transistors Mp and Mn. The substrate bias voltage has a voltage level relationship of vpn>vdd>vss> vbn. When the substrate bias voltages Vbp and vbn are applied, the MOS transistors Mp and Mn are in the reverse substrate bias state, the threshold voltage is increased, and the subthreshold leakage current is reduced as compared with the state in which the substrate bias is not applied.
[0034]
In FIG. 3, the power switch PSW is turned off (the power is cut off to the block blk23) by the logical value “1” of the power control signal CL, and is turned on (the power to the block blk23 is turned on) by the logical value “0” of the power control signal CL. Switch circuits SW3 and SW4 to be in a power supply state).
[0035]
FIG. 4 illustrates how to recognize the delay times d1, d2, and d3 by the computer that has read the logical description data.
[0036]
In FIG. 4, the operation mode of the controlled block represented by the block blk23 is a normal mode, a low-speed operation mode with substrate bias control, and an indefinite mode with substrate bias control. The normal mode is an operation mode in which the power supply voltages vdd and vss are applied to the well region and the substrate bias voltages vbp and vbn are not applied. The low speed operation mode with the substrate bias control is an operation mode that allows the controlled block blk23 to which the substrate bias is applied to operate at a low speed. In short, this is an operation mode in which an input by an event is made valid for a controlled block in a substrate bias application state (a logic state in the controlled block corresponding to the input is maintained). In other words, each signal terminal of the controlled block is in a state of holding a signal corresponding to the internal state. On the other hand, the indeterminate mode with substrate bias control is an operation mode in which input due to an event is ignored for the controlled block in the substrate bias application state (the logic state in the controlled block is indefinite). In any of the operation modes, when the power control signal CL instructs to turn off the power, the delay time specified by the delay time information d1 elapses and the power supply is stopped. Further, when the power control signal CL instructs to turn on the power, the delay time specified by the delay time information d2 elapses therefrom, and the supply of power is resumed. In the low-speed operation mode, every time the operation of the controlled block blk23 is instructed in the substrate bias state, the operation delay corresponding to the delay time defined by the delay time information d3 is accumulated. In the undefined mode, when the substrate bias is instructed by the substrate bias control signal BB, the controlled block blk23 is disabled after the delay time specified by the delay time information d3 has elapsed.
[0037]
The recognition of the delay time illustrated in FIG. 4 is manifested in the logic structure in the logic design of the semiconductor integrated circuit using the logic description data, and also in the operation simulation process in the logic simulation. In short, the delay times d1, d2, and d3 by the computer are recognized using a logic synthesis tool corresponding to a logic description language in logic design, and are executed by executing a simulation program in simulation. The low speed mode and the indefinite mode can be selected in the logic simulation.
[0038]
FIG. 5 to FIG. 8 exemplify forms of control results by power-off control and substrate bias control by a computer that has read the logic description data.
[0039]
FIG. 5 shows a state where the power switch PSW is off and the presence or absence of substrate bias control is ignored. The internal node of the block blk23 that is the controlled block, that is, the terminal of the element and the terminal of the block are set to indefinite values (indicated by the symbol x in the figure). Here, the indefinite value is a state in which the logical value “1” or “0” is not determined. Such an indefinite state is a state in which a required logical state cannot be formed within the controlled block. For example, the logical value of the internal node becomes indefinite due to the occurrence of the subthreshold leakage current. This indefinite value state can be positioned as a state simulating an undesired state due to a subthreshold leak.
[0040]
FIG. 6 shows a state where the power switch is on and there is no substrate bias control. This corresponds to the normal mode of FIG. The internal node of the block blk23 that is the controlled block, that is, the terminal of the element and the terminal of the block take a logical value according to the external input. The state shown in FIG. 5 is positioned as an undesired state with respect to the normal state shown in FIG. 6. By simulating both states, it becomes possible to narrow down the logic faults due to subthreshold leakage.
[0041]
FIG. 7 shows a low-speed operation mode in which the power switch is turned on and there is substrate bias control. This corresponds to the low speed operation mode of FIG. The internal node of the block blk23 that is the controlled block, that is, the terminal of the element and the terminal of the block take a logical value according to the external input.
[0042]
FIG. 8 shows an indefinite operation mode with the substrate bias control when the power switch is on. This corresponds to the undefined operation mode of FIG. The internal node of the block blk23 that is the controlled block, that is, the element terminal and the block terminal are set to the indefinite values. The state of FIG. 8 is positioned as an undesired state with respect to the low-speed operation mode of FIG. 7, and by simulating both states, it becomes possible to narrow down the faulty parts of the logic due to the subthreshold leak in the substrate biased state.
[0043]
Similarly to the above, the control forms exemplified in FIGS. 5 to 8 are also manifested in the logic structure in the logic design of the semiconductor integrated circuit using the logic description data, and also in the operation simulation process in the logic simulation. .
[0044]
FIG. 9 illustrates a flowchart for developing a semiconductor device using logical description data recorded on the recording medium 1. The logical description data is read from the recording medium 1 (T1). The logic design of the semiconductor device is performed using the read logic description data (T2). In logic design, a logic synthesis tool corresponding to a logic description language can be used to make the logic description correspond to the logic circuit at the gate level and to proceed with the logic design. Using the read logic description data, a logic simulation of the semiconductor device logically designed is performed (T3). In the logic simulation, a netlist of the logically designed target circuit and pattern data are input and a simulation program is executed. The logic design is completed by modifying the logic configuration according to the evaluation result of the logic simulation. Thereafter, circuit design and layout design are performed (T4), and the development of the semiconductor device is completed.
[0045]
FIG. 10 illustrates a logic simulation by the computer 2 using the logic description data, in particular, details of its power supply system control flow. The simulation is performed in an event driven manner. First, the net list of the target circuit grasped from the logic description data is read (S1), and when it is detected that the value (signal) of the node of the target circuit has changed (event) according to the verification input pattern (S2), It is determined whether the block in which the change has occurred is a circuit block (power cutoff block) in which power cutoff control is enabled (S3). If the event occurrence block is a power cutoff block, the state of the power switch PSW of the power cutoff block is next determined (S4). If the power switch PSW is in the ON state, it is determined whether or not the signal of the power switch PSW has changed (change in power on) in the event (S5). When it is determined that the power switch PSW has changed, a delay value by switching the power switch (switching from the off state to the on state) is added (S6), and after the delay time has elapsed, the event target circuit block Cancels indefinite values for internal and external terminals. (S7). Thereafter, if a simulation (normal simulation) process other than the power supply system is required, it is performed (S8). The delay value added in step S6 is the delay time d2 in FIG.
[0046]
If it is determined in step S3 that the power supply block is not a block, or if it is determined in step S5 that there is no signal change of the power switch PSW, whether or not the substrate bias control is present (whether or not a substrate bias voltage is applied). Is determined (S9). If the substrate bias control is performed, the substrate bias delay value is added to the event (S10). This delay value is the delay time d3 in the indefinite mode of FIG. 4 or the delay time d3 accumulated in the low speed operation mode. After the delay value is added in step S9, it is determined whether or not it has been performed in the low-speed operation mode (S11). In short, the logic simulation is carried out using either the event input for the controlled block with substrate bias applied or the event input for the controlled block with substrate bias applied ignored. It is to say. The low-speed operation mode means that the former is adopted. If it is not the low-speed operation mode, then the indefinite value is set in the node of the event target circuit (S12), and the normal simulation step S8 is entered. If it is determined in step S11 that the operation mode is the low speed operation mode, and if the substrate bias is not controlled in step S9, the process enters step S8 of the normal simulation.
[0047]
When the power switch is off in step S4, an operation delay from the on state to the off state of the power switch PSW is added (S13), and the indefinite values are set in the internal and external nodes of the event target block after the lapse (S12). ) And enter the step of normal simulation S8. The operation delay in step S13 is the delay time d1 in FIG.
[0048]
The above process starting from detection of a signal change due to an event is repeated until the input pattern is completed.
[0049]
When the processing contents of the power supply system control performed in the simulation are arranged, when an event for shutting off the power supply of the circuit block occurs, a delay time d1 of the power shutoff operation is added to the terminal of the circuit block to be shut off. When the event of resuming the power supply occurs in the circuit block that is shut off, the circuit block that releases the power shutoff is added with a delay time d2 of the power supply resume operation When the circuit block in which the event has occurred is a substrate bias application target (S6, S7), the substrate bias delay time d3 is added to the event (S10). If the event is not a low-speed operation event, an undefined value is set to the terminal of the circuit block (S12).
[0050]
According to the embodiment of the invention described above, the following operational effects can be obtained.
[0051]
[1] Operation delay information d1, d2, and d3 due to power shut-off by the power supply system or substrate bias application is added to the logic description data, thereby controlling supply / shut-off of operation power to the circuit block and substrate bias control. It can be reflected in the logical design. Since such logical description data is recorded on the recording medium 1 and provided, such logical design can be easily performed. In the logic design using the logic description data, a gate level logic circuit can be obtained by using a logic synthesis tool corresponding to the description language of the logic description data. Further, a logic simulation can be performed on a logic-designed circuit by using a net list and input pattern data of the logic circuit specified by the logic description data.
[0052]
The first delay time information includes the delay time until the computer that has read the logic description data turns off the power by the power switch until the terminal of the controlled block becomes an indefinite value, and the computer reaches the power supply by the power switch. Defines the delay time until the terminal of the controlled block is released to an indefinite value. Due to the delay time of the power shut-off operation, the logic state when the power is turned off can be easily realized including the transition, and an accurate logic simulation when the power is turned off becomes possible. Due to the delay time of the power supply restarting operation, a logic state can be accurately realized in consideration of a delay caused by the transition from the power-off state to the on-state, and such a logic simulation is also possible.
[0053]
The second delay time information defines a delay time until the computer that has read the logic description data sets the terminal of the controlled block to which the substrate bias is applied by the substrate bias controller to an indefinite value. Further, the second delay time information defines an operation delay time when the computer that has read the logic description data validates the input by the event to the controlled block in the substrate bias state by the substrate bias controller. Depending on the substrate bias delay time, the internal signal state transition to the controlled block in the substrate bias application state is allowed (input by event is enabled) or prohibited (input by event is ignored) The logic state can be realized, and an accurate logic simulation in consideration of such a state is also possible. It is possible to select any logic state that enables input by event and logic state that ignores input in the substrate bias application state, so it is possible to narrow down the detection of logic faults due to leakage in logic simulation Become.
[0054]
[2] According to the logic simulation, an accurate logic simulation when the power is turned off becomes possible due to the delay time of the power shut-off operation. The logic simulation considering the delay due to the transition from the power-off state to the on-state becomes possible by the delay time of the power supply restart operation. The substrate bias delay time enables an accurate logic simulation considering the logic state when a substrate bias is applied. Since a logic state that is indefinite with respect to the state in which the internal node is held in the substrate bias application state can be realized, it is also possible to narrow down detection of a logic defect due to a leak in the logic simulation. According to the simulation method, logic verification can be performed in consideration of control of supply / cutoff of operation power to the circuit block and substrate bias control.
[0055]
[3] With the development of a semiconductor device, the recording medium can be designed and verified in consideration of the control / supply control of the operation power to the circuit block and the substrate bias control. Control and substrate bias control can contribute to improving the reliability of a semiconductor device oriented to low power consumption.
[0056]
Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0057]
For example, the low-speed operation mode is positioned as an internal state holding mode in the substrate bias application state. The internal configuration of the circuit module, the specific configuration of the substrate bias controller, and the power switch can be changed as appropriate. Further, the logical description language is not limited to Verilog-HDL or VHDL, and other logical description languages may be used. Further, although the circuit module is positioned as a component of the semiconductor device, it may mean a large-scale logic like the semiconductor device.
[0058]
In the above description, the case where the invention made mainly by the present inventor is applied to the development of a semiconductor device, which is the field of use behind it, has been described. However, the invention can be widely applied to the development of electronic circuits. .
[0059]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0060]
That is, according to the recording medium of the logic description data, it is possible to easily obtain the logic description data that can reflect the supply / cutoff of the operation power supply to the circuit block and the substrate bias control in the logic design.
[0061]
It is possible to realize a simulation method capable of performing logic verification in consideration of supply / cutoff of operation power supply to a circuit block and substrate bias control.
[0062]
It is possible to contribute to improving the reliability of a semiconductor device oriented to low power consumption by controlling supply / cutoff of operation power to a circuit block and substrate bias control.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an example of a recording medium for logical description data according to the present invention.
FIG. 2 is an explanatory diagram showing hierarchically the logical structure represented by the logical description data of FIG. 1;
FIG. 3 is a circuit diagram illustrating, by a gate structure, the contents of the logic description part of the substrate bias controller and the logic description part of the power switch PSW of FIG.
FIG. 4 is an explanatory diagram exemplifying how a delay time is recognized by a computer that has read logical description data;
FIG. 5 is an explanatory diagram showing a state where the power switch is off and the presence / absence of substrate bias control is ignored as a form of control results by power cutoff control and substrate bias control by a computer that has read logic description data.
FIG. 6 is an explanatory diagram showing a state in which the power switch is on and there is no substrate bias control as a form of control results by power cutoff control and substrate bias control by a computer that has read logic description data.
FIG. 7 is an explanatory diagram showing a state of a low-speed operation mode in which a power switch is on and a substrate bias control is present as a form of a control result by a power-off control and a substrate bias control by a computer having read logical description data. .
FIG. 8 is an explanatory diagram showing a state of an indefinite operation mode in which a power switch is on and a substrate bias control is present as a form of a control result by a power supply cutoff control and a substrate bias control by a computer that reads logical description data. .
FIG. 9 is a flowchart when developing a semiconductor device using logical description data recorded on a recording medium.
FIG. 10 is a flowchart illustrating the details of a logic simulation by a computer using logic description data, in particular, the power supply system control flow.
[Explanation of symbols]
1 Recording medium
2 Computer
VBB substrate bias controller
BB substrate bias control signal
PSW power switch
CL power control signal
d1 Delay information of power-off operation
d2 Delay time information of power supply restart operation
d3 Substrate bias delay time information
blk23 controlled block
blk22 module

Claims (12)

A recording medium that records logic description data of a circuit module that can be read by a computer and used for logic design,
The logic description data includes a logic description of a substrate bias controller, a logic description of a power supply switch, and a logic description of a controlled block connected thereto as circuit blocks constituting a circuit module,
The logical description of the power switch includes first delay time information indicating a delay of the switch operation,
The logical description data recording medium according to claim 1, wherein the logical description of the substrate bias controller includes second delay time information indicating a delay due to a substrate bias. The first delay time information includes the delay time until the computer that has read the logic description data turns off the power by the power switch until the terminal of the controlled block becomes an indefinite value, and the computer reaches the power supply by the power switch. 2. The logical description data recording medium according to claim 1, wherein a delay time until the indefinite value of the terminal of the controlled block is canceled is defined. The second delay time information defines a delay time until the computer that has read the logic description data sets the terminal of the controlled block that reaches the substrate bias application by the substrate bias controller to an indefinite value. A recording medium for logical description data according to 1 or 2. The second delay time information defines an operation delay time when the computer reading the logic description data changes the internal signal state with respect to the controlled block in the substrate bias state by the substrate bias controller. The recording medium for logical description data according to claim 1 or 2. 5. The logical description data recording medium according to claim 1, wherein the controlled block is one or both of a logic circuit and a memory circuit. A process of reading logical description data from the recording medium according to claim 1;
A process for logical design of a semiconductor device using the read logical description data;
And a process of performing a logic simulation of the semiconductor device logically designed using the read logic description data. The process of performing the logic simulation is as follows:
When an event for shutting off the power supply of the controlled block occurs, a delay time until the power shutoff as the first delay time information is added, and an indefinite value is set at the terminal of the controlled block to be powered off. Processing to
A terminal of the controlled block that is released from the power cutoff by adding a delay time of the power supply restart operation as the first delay time information when an event for restarting the power supply occurs in the controlled block that is powered off. Processing to cancel the indefinite value of
When the controlled block in which an event has occurred is a substrate bias application target, the second delay time is added to the event, and the input to the controlled block is ignored. 7. The method of developing a semiconductor device according to claim 6, further comprising: processing for setting an indefinite value at a terminal of the controlled block. 8. The method of developing a semiconductor device according to claim 7, wherein the simulation process can select to ignore or enable an input due to an event for the controlled block. A method of performing logic simulation using the logic description data for a circuit block that can be selectively subjected to power shutdown and substrate bias control,
When an event to shut off the power of the circuit block occurs, add a delay time of the power shut-off operation and set an indeterminate value to the terminal of the circuit block to be shut off,
When an event for restarting power supply occurs in a circuit block that is powered off, the delay time of the power supply restart operation is added to cancel the indeterminate value of the terminal of the circuit block that is released from the power shutdown,
When a circuit block where an event has occurred is a substrate bias application target, a delay time for substrate bias is added to the event, and if the selection to ignore the input due to the event is performed for the controlled block, Furthermore, an indefinite value is set at a terminal of the controlled block. 10. The logic simulation method according to claim 9, wherein for the controlled block in a substrate bias application state, it is possible to select ignoring input due to an event and validating the input. 10. The substrate bias delay time is accumulated every time an input event occurs for a controlled block when an input by an event is enabled for the controlled block in a substrate bias application state. Logic simulation method. 10. The logic simulation method according to claim 9, wherein the delay time of the power shutdown operation, the delay time of the power supply restart operation, and the delay time for substrate bias are information defined in the logic description data.

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