JP2005011019A - Information processor, printer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a mistake of data transfer in writing inputted data in a memory section in an information processor which controls power supply to each device responding to a driving condition of each device. <P>SOLUTION: An information processor 100 which restricts power supply to the memory 20 at the time of power saving control, is equipped with a buffer 32 which holds inputted processing object data temporarily, and a voltage monitoring section 50 which supervises voltage state of the memory 20. A DMA control section 33 which controls DMA transfer of processing object data suspends forwarding of the processing object data held temporarily in the buffer section 32 to the memory 20 until the voltage state of the memory 20 is determined to be stable by the voltage monitoring section 50. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing device, and more particularly, to an information processing device that controls power supply in each device in accordance with a driving state of each device.
[0002]
[Prior art]
Power supply to each device in order to reduce wasteful power consumption in an information processing device comprising a main storage device and a central processing unit that performs various information processing using data and programs stored in the main storage device The following techniques exist for controlling the above. In other words, each device can switch between a power saving mode that reduces power consumption in each device and a normal mode that supplies normal power to each device based on the drive status of the main storage device and central processing unit. It is a technology that suppresses unnecessary power consumption.
[0003]
[Patent Document 1]
JP-A-5-324494 [0004]
[Problems to be solved by the invention]
In the information processing apparatus having the power saving mode as described above, the following problems occur when performing direct memory access (DMA) transfer in which data or the like is directly written to the main memory without going through the central processing unit. Sometimes. That is, immediately after the power supply mode is switched from the power saving mode to the normal mode, the power supply to the main storage device is unstable, and it takes a while until the voltage state of the main storage device is stabilized. When such a main storage device voltage state is unstable, a DMA transfer in which data output from an input / output device or the like is directly written to the main storage device may cause a data transfer error or the like.
[0005]
The present invention has been made in view of the above problems, and in an information processing device that controls power supply to each device according to the driving state of each device, the data is written when the input data is written in the storage unit. The purpose is to prevent transfer mistakes.
[0006]
[Means for Solving the Problems]
The present invention is a storage unit that is activated based on a received activation signal and stores processing target data, and a control unit that transmits the activation signal to the storage unit based on the received activation command signal, and includes: A control unit that executes information processing and a DMA unit that directly writes input processing target data to the storage unit without going through the control unit. During power saving control, power supply to the storage unit and the control unit is restricted. In the information processing apparatus, when processing target data is input, a signal transmission unit that transmits a start command signal to the control unit, a buffer unit that temporarily stores the input processing target data, and a voltage state of the storage unit A voltage determination unit that determines whether or not is in a stable state, and the DMA unit is a processing target temporarily held in the buffer unit until the voltage determination unit determines that the voltage state of the storage unit is in a stable state data Characterized by holding the writing into the storage unit.
[0007]
According to the present invention, until the voltage determination unit determines that the voltage state of the storage unit is a stable state, the input processing target data is held in the buffer unit and writing to the storage unit is suspended. Thereby, in the information processing apparatus that controls the power supply to each apparatus according to the driving state of each apparatus, it is possible to prevent a data transfer error that occurs when the input data is written in the storage unit.
[0008]
In one aspect of the information processing apparatus according to the present invention, the buffer unit sequentially holds a plurality of input data to be processed until the power state of the storage unit becomes stable, and the DMA unit performs power determination. When the unit determines that the power state of the storage unit is a stable state, the plurality of pieces of processing target data temporarily stored in the buffer unit are sequentially written to the storage unit.
[0009]
According to the present invention, a plurality of pieces of processing target data are held in the buffer unit until the power determination unit determines that the power state of the storage unit is in a stable state. Are sequentially written to the storage unit. Thereby, even if a plurality of process target data is input until the power state of the storage unit becomes stable, all the process target data can be appropriately written in the storage unit without making a data transfer error.
[0010]
According to another aspect of the present invention, there are a storage unit that is activated based on a received activation signal and stores print target data, and a control unit that transmits the activation signal to the storage unit based on the received activation command signal. A control unit that executes a printing process of the print target data; and a DMA unit that directly writes the input processing target data to the storage unit without going through the control unit. During power saving control, the storage unit and the control unit In the printer device that restricts power supply to the printer, when print target data is input, a signal transmission unit that transmits a start command signal to the control unit, a buffer unit that temporarily holds the input print target data, A voltage determination unit that determines whether or not the voltage state of the storage unit is a stable state, and the DMA unit temporarily stores the voltage in the buffer unit until the voltage determination unit determines that the voltage state of the storage unit is a stable state. Retained Characterized by holding the writing into the storage unit of the print data.
[0011]
According to the present invention, until the voltage determination unit determines that the voltage state of the storage unit is a stable state, the input print target data is held in the buffer unit and writing to the storage unit is suspended. Thereby, in the printer device that controls the power supply to each device according to the driving state of each device, it is possible to prevent an error in data transfer that occurs when the input data is written in the storage unit.
[0012]
According to one aspect of the printer device of the present invention, the buffer unit sequentially holds a plurality of input print target data until the power state of the storage unit becomes stable, and the DMA unit When the determination unit determines that the power state of the storage unit is a stable state, a plurality of pieces of print target data temporarily held in the buffer unit are sequentially written in the storage unit.
[0013]
According to the present invention, a plurality of print target data is held in the buffer unit until the power determination unit determines that the power state of the storage unit is a stable state. Are sequentially written to the storage unit. Thereby, even if a plurality of process target data is input until the power state of the storage unit becomes stable, all the print target data can be appropriately written in the storage unit without causing a data transfer error.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. FIG. 1 is a diagram illustrating a system configuration of an information processing apparatus 100 according to the present embodiment. Here, the information processing apparatus is, for example, a printer apparatus that performs print processing as information processing. The CPU 10 is a central control device that controls each part of the information processing apparatus 100 and performs information processing of data to be processed. Give a switching instruction. The memory 20 is a storage device that stores data to be processed such as various programs and data, and a part or all of the memory 20 is configured by a nonvolatile memory. Here, the processing target data refers to print target data to be printed, such as document data read by a scanner or transmitted from a personal computer in the case of a printer device. If the information processing apparatus is a printer apparatus, the CPU 10 controls each unit and executes the printing process of the print target data.
[0015]
Further, the input / output interface control unit 30 directly stores the processing target data output from the input / output device (for example, a scanner (not shown) if the information processing device is a printer device) without using the CPU 10. So-called direct memory access (DMA) transfer is performed. The power control unit 40 supplies power to each unit. When the power supply control unit 40 receives an instruction to shift to the power saving mode from the CPU 10, the power supply control unit 40 restricts power supply to each unit. In addition, upon receiving an instruction to shift to the normal mode from the CPU 10, the power supply restriction to each unit is released. The voltage monitoring unit 50 monitors the voltage state of the memory 20, determines whether or not the voltage state of the memory 20 is stable, and notifies the input / output interface control unit 30 of the determination result. For example, the voltage monitoring unit 50 determines a stable state when the voltage of the memory 20 is equal to or higher than a predetermined reference voltage using a comparator or the like.
[0016]
What is characteristic in the present embodiment is that the input / output interface control unit 30 performs DMA transfer of the input processing target data to the memory 20 until the voltage monitoring unit 50 determines that the voltage state of the memory 20 is stable. To hold. As described above, the DMA transfer is suspended until the voltage state of the memory 20 is stabilized, thereby preventing a data transfer error due to the DMA transfer.
[0017]
Here, the input / output interface control unit 30 will be described with reference to FIG. When receiving data to be processed from the input / output device or the like via the I / O channel 60, the I / O channel control unit 31 outputs a signal indicating a request to shift to the normal mode to the CPU 10. The buffer unit 32 temporarily holds the processing target data transferred from the I / O channel control unit 31. The buffer unit 32 can hold a plurality of treatment target data until the writing to the memory 20 is completed, and the writing to the memory 20 is performed by, for example, the FIFO method. When the transfer of the processing target data to the buffer unit 32 is completed, the I / O channel control unit 31 outputs an end notification signal indicating that the transfer to the buffer unit 32 has been completed to the DMA control unit 33 described later. When the DMA control unit 33 receives the end notification signal from the I / O channel control unit 31, the DMA control unit 33 writes the fact to the register 0. Further, based on the determination result from the voltage monitoring unit 50, if the voltage state of the memory 20 is stable, the fact is written in the register 1 (331). Then, if the voltage state of the memory 20 is stable based on the contents of the registers 0 and 1 (331), the DMA control unit 33 sequentially transfers the processing target data that has been written to the buffer unit 32 by DMA transfer. To write to the memory 20.
[0018]
Here, an operation in which the input / output interface control unit 30 DMA-transfers the processing target data temporarily held in the buffer unit 32 to the memory 20 will be described with reference to the flowchart of FIG.
[0019]
First, the I / O channel control unit 31 receives processing target data from the input / output device via the I / O channel (S101). When the processing target data is received, the I / O channel control unit 31 outputs a signal indicating a request to shift to the normal mode to the CPU 10 (S102) (Here, the CPU 10 receives the transfer request and receives the shift request. On the other hand, the power supply control unit 40 switches to the normal mode on the basis of the instruction and releases the power supply restriction to the memory 20). Then, the I / O channel control unit 31 writes the received processing target data in the buffer unit 32 (S103), and when the writing is completed, outputs an end notification signal to the DMA control unit 33 (S104). The DMA control unit 33 determines whether or not the voltage state of the memory 20 is a stable state based on the contents of the registers 0 and 1 (S105). If the result of determination is that the state is not stable, DMA transfer to the memory 20 is suspended, and it is further determined whether or not there is data to be processed from the input / output device (S106). If there is further processing target data as a result of the determination, the processing target data is newly written into the buffer unit 32 in S103. On the other hand, if it is determined in S106 that there is no new data to be processed, the DMA control unit 33 holds the DMA transfer as it is and waits until the voltage state of the memory 20 becomes stable. If it is determined in S105 that the state is stable, the DMA control unit 33 sequentially writes the processing target data that has been written to the buffer unit 32 to the memory 20 by DMA transfer (S107).
[0020]
In this way, until the voltage monitoring unit 50 determines that the voltage state of the memory 20 is a stable state, the DMA control unit 33 suspends the DMA transfer of the input processing target data to the memory 20, thereby performing the DMA transfer. Data transfer mistakes can be prevented.
[0021]
【The invention's effect】
According to the present invention, until the voltage determination unit determines that the voltage state of the storage unit is a stable state, the input processing target data is held in the buffer unit and writing to the storage unit is suspended. Thereby, in the information processing apparatus that controls the power supply to each apparatus according to the driving state of each apparatus, it is possible to prevent a data transfer error that occurs when the input data is written in the storage unit.
[0022]
Furthermore, according to the present invention, a plurality of data to be processed is held in the buffer unit until the power determination unit determines that the power state of the storage unit is a stable state. The target data is sequentially written into the storage unit. Thereby, even if a plurality of process target data is input until the power state of the storage unit becomes stable, all the process target data can be appropriately written in the storage unit without making a data transfer error.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of an information processing apparatus according to a first embodiment.
FIG. 2 is a block diagram of the information processing apparatus according to the first embodiment, focusing on an input / output interface.
FIG. 3 is a flowchart showing a processing flow of DMA transfer in the first embodiment.
[Explanation of symbols]
10 CPU, 20 memory, 30 I / O interface control unit, 31 I / O channel control unit, 32 buffer unit, 33 DMA control unit, 40 power supply control unit, 50 voltage monitoring unit, 60 channels, 100 information processing device, 331 register .

Claims (4)

A storage unit that is activated based on the received activation signal and stores processing target data;
A control unit that transmits a start signal to the storage unit based on the received start command signal, and a control unit that performs information processing of the processing target data;
A DMA unit that directly writes input processing target data to a storage unit without going through a control unit;
In the information processing apparatus that restricts power supply to the storage unit and the control unit during power saving control,
When processing target data is input, a signal transmission unit that transmits an activation command signal to the control unit,
A buffer unit that temporarily holds input data to be processed;
A voltage determination unit that determines whether or not the voltage state of the storage unit is a stable state;
With
The DMA unit is
An information processing apparatus that suspends writing of data to be processed temporarily stored in a buffer unit to the storage unit until the voltage determination unit determines that the voltage state of the storage unit is a stable state. The information processing apparatus according to claim 1,
The buffer unit is
Until the power state of the storage unit becomes stable, a plurality of input processing target data is sequentially held,
The DMA unit is
An information processing apparatus, wherein when the power determination unit determines that the power state of the storage unit is a stable state, a plurality of pieces of processing target data temporarily stored in the buffer unit are sequentially written in the storage unit. A storage unit that is activated based on the received activation signal and stores print target data;
A control unit that transmits a start signal to the storage unit based on the received start command signal, and a control unit that executes a printing process of the print target data;
A DMA unit that directly writes input processing target data to a storage unit without going through a control unit;
In a printer device that restricts power supply to the storage unit and the control unit during power saving control,
When data to be printed is input, a signal transmission unit that transmits a start command signal to the control unit,
A buffer unit for temporarily storing the input print target data;
A voltage determination unit that determines whether or not the voltage state of the storage unit is a stable state;
With
The DMA unit is
A printer apparatus, wherein writing of data to be printed temporarily held in a buffer unit to the storage unit is suspended until the voltage determination unit determines that the voltage state of the storage unit is a stable state. The printer apparatus according to claim 3.
The buffer unit is
Until the power state of the storage unit becomes a stable state, a plurality of input print target data is sequentially held,
The DMA unit is
A printer apparatus, wherein when the power determination unit determines that the power state of the storage unit is a stable state, a plurality of print target data temporarily stored in the buffer unit is sequentially written in the storage unit.

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