JP2005005384A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

A semiconductor integrated circuit device having a read-only semiconductor memory capable of suppressing an increase in manufacturing cost and shortening a time required for correction.
A transistor Tr having a gate as a word line, interlayer insulating films 5 and 9, and an interlayer insulating film 5 and 9 positioned above one end of a current path of the transistor Tr are selected according to information to be programmed. Of the transistor Tr provided selectively according to the presence or absence of the stopper layer 11 in the interlayer insulating films 5 and 9 and the stopper layer 11 containing a material different from the interlayer insulating films 5 and 9. A conductive layer 12 connected to one end of the current path, the interlayer insulating films 5 and 9, the conductive layer 12, and a bit line BL provided on the stopper layer 11 are provided.
[Selection] Figure 2

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a read-only semiconductor memory.
[0002]
[Prior art]
In a microcontroller equipped with a non-volatile memory, a user program is stored in a mask ROM, an EPROM (Erasable and Programmable ROM), or a flash memory. Among these, the mask ROM is a device that programs stored information into an LSI manufacturing process, that is, an LSI mask pattern. Advantages of the mask ROM include the following.
[0003]
-Since a write operation is unnecessary, the peripheral circuit is simpler than that of EPROM or EEPROM.
[0004]
The memory cell can be a normal transistor, and no special manufacturing process is required. For this reason, an LSI chip can be manufactured at low cost.
[0005]
-Since data cannot be written or erased, there is no loss of data or erroneous rewriting due to mishandling by the user.
[0006]
On the other hand, the disadvantage is
-The so-called "Turn Around Time (TAT)" is a long period until the product is supplied from the producer to the end user.
[0007]
・ In addition to the mother body, only the user's ROM code type mask is required, so the cost is high for small-volume production.
[0008]
-Since data cannot be changed, for example, if there is a bug in the program, it needs to be corrected, resulting in risks for users and producers.
[0009]
As conventional examples, ROM cell plan views are shown in FIGS. 31 to 35, and the advantages and disadvantages of each memory cell are given. In the description of the conventional example, data “1” indicates that the cell current flows and the bit line potential decreases, and data “0” indicates that the cell current does not flow and the bit line potential does not change.
[0010]
FIG. 31 is a plan view of a cell (hereinafter referred to as LOCOS ROM) for programming data in accordance with the presence or absence of the diffusion layer pattern. The LOCOS ROM programs data depending on whether or not a diffusion layer (element region) pattern is formed under the gate electrode (word line WL) of the memory cell transistor Tr, that is, in the channel. In the Tr in which the diffusion layer pattern is formed, for example, the threshold value is set so that the cell current flows when the potential of the word line WL is set to the “HIGH” level. As a result, a current flows from the bit line BL toward the source S through the Tr channel (Tr = ON), and the programmed data becomes “1”. For example, in a Tr having no diffusion layer pattern in the channel and having an element isolation region (LOCOS) pattern, for example, no cell current flows even when the potential of the word line WL is set to the “HIGH” level (Tr = OFF). . Therefore, the programmed data is “0”. The circuit system of this type of cell is generally a NOR type, has a small resistance between the bit line BL and the source S, can obtain a large current gain, and can operate at high speed. However, the ROM is programmed in the element isolation region forming step, and a photomask for programming data (hereinafter referred to as ROM code mask) is commonly used, for example, as a photomask used for element isolation region formation. Become. Since the element isolation region forming step is performed at an early stage of the wafer process, a structure (hereinafter referred to as a parent body) common to each IC product is a structure before the element isolation region is formed. For this reason, TAT becomes long.
[0011]
FIG. 32 is a plan view of a cell (hereinafter referred to as “Contact ROM”) for programming data according to the presence or absence of a contact hole. In the contact ROM, the programmed data is “1” when the contact CC is between the bit line BL and the drain D, and the programmed data is “0” when there is no contact CC. In the contact ROM, data is programmed in a contact hole forming process closer to the final process than in the element isolation region forming process, so that TAT can be shortened as compared with the LOCOS ROM. As a known document of this type of cell, for example, there is Patent Document 1.
[0012]
FIG. 33 is a plan view of a cell (hereinafter referred to as an ion implantation ROM) for programming data in accordance with the presence or absence of ion implantation. In the ion implantation ROM, impurity ions are implanted into the channel so that the memory cell transistor Tr for programming data “1” is a depletion type, and impurity ions are implanted into the other memory cell transistors. First, the enhancement type is maintained and data “0” is programmed. The example shown in FIG. 33 is a NAND cell in which a plurality of memory cell transistors Tr are connected in series between a bit line BL and a source S. Since the NAND type cell does not need to form a contact hole for each bit as compared with the NOR type cell, the size per memory cell transistor can be reduced. However, since a plurality of transistors are directly connected between the bit line BL and the source S, a sufficient current gain cannot be obtained, and high-speed operation is difficult. In an ion implantation ROM, data is usually programmed using channel ion implantation for depletion type during a channel ion implantation step before a gate electrode forming step. In this method, in order to further shorten TAT, the ion implantation energy is increased, and after the gate electrode forming step, impurity ions for depletion type are implanted into the channel through the gate electrode. In addition, there is a method of implanting the impurity ions into the channel through the first layer interlayer insulating film and the gate electrode after forming the first layer interlayer insulating film. As a known document, for example, there is Patent Document 2.
[0013]
FIG. 34 is a plan view of a cell (hereinafter referred to as AL ROM) for programming data according to the presence or absence of wiring. The AL ROM programs data depending on whether or not the source and drain contacts of the memory cell transistors Tr connected in series are connected by the wiring WW. In the case of “with wiring”, data “1” is programmed, and in the case of “without wiring”, data “0” is programmed. In the AL ROM, data is usually programmed in the first layer metal wiring forming step after the first layer interlayer insulating film forming step. For this reason, TAT can be shortened. However, since it is necessary to arrange a contact for each bit as compared with the ion implantation type ROM, the occupied area per cell is increased.
[0014]
FIG. 35 is a plan view of a cell (hereinafter referred to as Via ROM) for programming data according to the presence or absence of a through hole. In the Via ROM, the local wiring LWW connected to the drain D of each memory cell transistor is formed using the first layer metal layer, and the bit line BL is formed using the second layer metal layer. If there is a through hole Via in the interlayer insulating film between the bit line BL and the local wiring, the programmed data is “1”, and if not, the programmed data is “0”. FIG. 36 shows a cross section of the Via ROM. A pattern to be a ROM code is determined by, for example, the presence or absence of an opening by using a photomask for forming a through hole Via. In ViaROM, data is programmed in the through-hole forming process after the first-layer metal wiring forming process and the second-layer interlayer insulating film forming process, so that any of the cells shown in FIGS. TAT can be shortened. As a known document, there is Patent Document 3.
[0015]
[Patent Document 1]
US Pat. No. 4,358,889
[0016]
[Patent Document 2]
US Pat. No. 4,649,629
[0017]
[Patent Document 3]
US Pat. No. 5,943,255
[0018]
[Problems to be solved by the invention]
In a microcontroller equipped with a mask ROM, the ROM code is drawn on a photomask for forming a diffusion layer pattern, contact hole pattern, channel ion implantation pattern, first layer metal wiring formation pattern, or through hole pattern. It is. These photomasks are common to the mask ROM and circuits other than the mask ROM.
[0019]
If a problem occurs in a circuit other than the mask ROM, it is necessary to correct the photomask including the ROM code. The ROM code is different for most IC products. If there is a problem in a circuit other than the mask ROM in a mother body with many compatible products, the number of photomasks that must be corrected increases. For this reason, the cost required for correction and verification of the photomask increases, and the period required for correction and verification is also long. Moreover, the verification must not only verify that the corrected part is correctly corrected, but also verify whether the ROM code is correctly reproduced for each IC product. The ROM code is different for each IC product, and its verification is complicated and not easy.
[0020]
Further, when the miniaturization of an integrated circuit progresses, the manufacturing time per photomask increases, and the time required for mask verification and verification becomes longer and costs further increase. In particular, when a special mask such as a phase shift mask is used, for example, the number of manufacturing steps is larger than that of a normal photomask, and the manufacturing cost is high. Further, in the pattern verification, it is necessary to separately verify the phase shift amount and the transmittance, and the verification time is longer than that of a normal photomask.
[0021]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit device having a read-only semiconductor memory capable of suppressing an increase in manufacturing cost and shortening a period required for correction, and a method for manufacturing the same. Is to provide.
[0022]
[Means for Solving the Problems]
To achieve the above object, a semiconductor integrated circuit device according to a first aspect of the present invention includes a transistor having a gate as a word line provided on a semiconductor substrate, and a semiconductor substrate provided with the transistor. The interlayer insulating film provided and the interlayer insulating film positioned above one end of the current path of the transistor include a material different from the interlayer insulating film selectively provided according to programmed information A stopper layer, a conductive layer selectively provided in the interlayer insulating film depending on the presence or absence of the stopper layer, connected to one end of a current path of the transistor, the interlayer insulating film, the conductive layer, And a bit line provided on the stopper layer.
[0023]
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device comprising: forming a transistor having a gate as a word line on a semiconductor substrate; and forming an interlayer insulating film on the semiconductor substrate on which the transistor is formed. And a stopper layer containing a material different from the interlayer insulating film is selectively formed on the interlayer insulating film located above one end of the current path of the transistor according to programmed information. A step of selectively forming a conductive layer connected to one end of the current path of the transistor in the interlayer insulating film according to the presence or absence of the stopper layer, the interlayer insulating film, the conductive layer, And a step of forming a bit line on the stopper layer.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.
[0025]
(First embodiment)
1 is a plan view showing an example of a plane pattern of a read-only semiconductor memory according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and FIG. 3 is III in FIG. FIG. 4 is an equivalent circuit diagram of the read-only semiconductor memory according to the first embodiment of the present invention.
[0026]
As shown in FIGS. 1 to 4, N-channel MOS transistors are arranged in an array on a semiconductor substrate, for example, a P-type silicon substrate 1. In the first embodiment, the N-channel MOS transistor functions as a memory cell. 1 to 4 show 16 memory cells Tr11 to Tr44 arranged at electrical intersections between the word lines WL1 to WL4 and the bit lines BL1 to BL4 in the memory cell array.
[0027]
The memory cells Tr11 to Tr44 of this example share the N-type source diffusion layer S between adjacent memory cells along the column direction (in this specification, the direction in which the bit line BL extends is defined as the column direction). For example, FIGS. 1 to 4 show Tr21 and Tr31, Tr22 and Tr32, Tr23 and Tr33, and Tr24 as memory cells that are adjacent along the column direction and share the source diffusion layer S. Further, the source diffusion layer S is shared by adjacent memory cells along the row direction (in this specification, the direction that intersects the column direction and the word line WL extends is defined as the row direction). For example, FIGS. 1 to 4 show Tr11 to Tr14, Tr21 to Tr24, Tr31 to Tr34, and Tr41 to Tr44 as memory cells sharing the source diffusion layer S along the row direction. Note that the source diffusion layer S of this example is shared between adjacent memory cells along the row direction. However, the source diffusion layer S is not limited to this structure. For example, the source diffusion layer S is separated for each column by the element isolation region 2, and the source diffusion layer S separated for each column is extended along the row direction and connected by a wiring to which a source potential is supplied. Also good.
[0028]
On the other hand, the N-type drain diffusion layer D is provided independently for each of the memory cells Tr11 to Tr44. 1 to 4, reference numerals D11 to D44 are assigned to the memory cells Tr11 to Tr44, respectively. The drain diffusion layers adjacent along the column direction, for example, D11 and D21, D31 and D41,..., D14 and D24, and D34 and D44 are separated by the element isolation region 2. Similarly, drain diffusion layers adjacent along the row direction, for example, D11 to D14,..., D41 to D44, are separated by the element isolation region 2.
[0029]
The element isolation region 2 is formed in the surface region of the substrate 1 and is made of an insulator, for example, silicon dioxide. Examples of silicon dioxide used for the element isolation region 2 include silicon dioxide deposited using tetraethoxysilane (TEOS) as a source gas, or a film obtained by oxidizing the silicon surface (thermal oxide film). The element isolation region 2 defines an element region on the surface of the substrate 1. The source diffusion layer S and the drain diffusion layers D11 to D44 are formed in the element region.
[0030]
A gate insulating film 3 is formed between the source diffusion layer S and the drain diffusion layers D11 to D44, that is, on the channel region. The gate insulating film 3 is made of a thin insulating film, for example, a silicon dioxide film having a thickness of about 5 to 15 nm. An example of silicon dioxide used for the gate insulating film 3 is a thermal oxide film.
[0031]
A gate electrode is formed on the gate insulating film 3. The gate electrode is a conductive film, for example, a conductive polycrystalline silicon film, a refractory metal film such as tungsten or cobalt, or a laminated structure film (polycide) including a polycrystalline silicon film and a silicided refractory metal film. Structure) or a laminated structure film (polymetal structure) including a polycrystalline silicon film and a refractory metal film. In this example, the gate electrode functions as the word lines WL1 to WL4.
[0032]
A first interlayer insulating film 5 is formed on the substrate 1 on which the gate electrode, the source diffusion layer S, the drain diffusion layers D11 to D44, and the element isolation region 2 are formed. The interlayer insulating film 5 is made of an insulator, for example, silicon dioxide. Silicon dioxide used for the interlayer insulating film 5 includes silicate glass (BPSG) containing boron and phosphorus, or silicon dioxide (CVD-SiO) formed by deposition. ₂ ).
[0033]
In the interlayer insulating film 5, contact holes 6 reaching the drain diffusion layers D11 to D44 are formed. The contact hole 6 is provided in each of the memory cells Tr11 to Tr44. A plug 7 is formed in the contact hole 6. The plug 7 is made of a conductive material such as aluminum.
[0034]
Local wirings 8 are formed on the surface of the plug 7 and the surface of the interlayer insulating film 5. The local wiring 8 is electrically connected to the plug 7 and connected to the drain diffusion layers D11 to D44. The local wiring 8 is provided for each of the memory cells Tr11 to Tr44. 1 to 4, reference numerals 8-11 to 8-44 are assigned to the memory cells Tr11 to Tr44. The local wiring 8 is formed using, for example, a first metal wiring layer, and is made of, for example, an alloy of aluminum and copper.
[0035]
A second layer interlayer insulating film 9 is formed on the first layer interlayer insulating film 5 and the local wiring 8. A through hole 10 reaching the local wiring 8 is formed in the interlayer insulating film 9, and a stopper layer 11 disposed above the local wiring 8 is formed on the interlayer insulating film 9.
[0036]
The stopper layer 11 suppresses the formation of the through hole 10. For this reason, the through hole 10 is not formed below the stopper layer 11. In this example, using this structure, data “1” or data “0” is stored depending on whether the through hole 10 or the stopper layer 11 is formed. In this example, as an example of data storage, the stopper layer 11 is provided for the memory cells Tr11, Tr24, Tr32, and Tr44, and the through hole 10 is provided for the other memory cells. The stopper layer 11 is made of, for example, a material capable of taking an etching selectivity with respect to the interlayer insulating film 9 for the purpose of suppressing the formation of the through hole 10. In order to obtain an etching selection ratio with respect to the interlayer insulating film 9, the stopper layer 11 only needs to contain a material different from that of the interlayer insulating film 9, for example. In addition, the stopper layer 11 may be either a conductive material or an insulating material as long as an etching selection ratio can be obtained with respect to the interlayer insulating film 9.
[0037]
A plug 12 is formed in the through hole 10. The plug 12 is made of a conductive material such as tungsten or aluminum.
[0038]
Bit lines BL1 to BL4 are formed on the surface of the plug 12, the surface of the interlayer insulating film 9, and the stopper layer 11. The bit lines BL1 to BL4 are electrically connected to the selected local wiring 8 among the local wirings 8-11 to 8-44 through the plug 12, and are selected from the drain diffusion layers D11 to D44. The drain diffusion layer D is electrically connected. Further, the bit lines BL1 to BL4 in this example are also formed in contact with the stopper layer 11 and have a width W along the row direction of the stopper layer 11. ₁₁ Is the width W of the bit lines BL1 to BL4 along the row direction. _BL (See FIG. 3). Advantages of this will be described later.
[0039]
Next, the reading operation will be described.
[0040]
(When memory cells with through holes are selected)
For example, assume that the memory cell Tr21 shown in FIG. 4 is selected.
[0041]
First, the bit line BL1 is charged to the read potential. Next, among the word lines WL1 to WL4, the potential of the word line WL2 is raised. The drain diffusion layer D21 of Tr21 is connected to the bit line BL1 through the plug 12 formed in the through hole 10. Therefore, the bit line BL1 is connected to, for example, the grounded source diffusion layer S via the channel below the drain diffusion layer D21 and the word line (gate electrode) WL2 of Tr21. As a result, a cell current flows through Tr21, and the potential of the bit line BL1 charged to the read potential decreases toward the ground potential. Thereby, the read data becomes, for example, “1”.
[0042]
(When a memory cell with a stopper layer is selected)
For example, assume that the memory cell Tr11 shown in FIG. 4 is selected.
[0043]
Similarly to the above, the bit line BL1 is charged to the read potential. Next, among the word lines WL1 to WL4, the potential of the word line WL1 is raised. Since there is the stopper layer 11 above the drain diffusion layer D11 of Tr11, there is no through hole 10. For this reason, the bit line BL1 is not connected to the drain diffusion layer D11 of Tr11. For this reason, the cell current does not flow, and the bit line BL1 is in an open state, for example, and maintains the read potential. Thereby, the read data becomes, for example, “0”.
[0044]
In this way, in the read-only semiconductor memory according to the first embodiment, it is possible to program a ROM code composed of information “1” and “0”.
[0045]
Next, an example of a manufacturing method of the read-only semiconductor memory according to the first embodiment will be described. 5 to 18 are cross-sectional views showing the read-only semiconductor memory according to the first embodiment of the present invention for each main manufacturing process. The cross section shown in FIGS. 5 to 18 corresponds to the cross section taken along the line III-III in FIG.
[0046]
First, as shown in FIG. 5, N-channel MOS transistors Tr11 to Tr44 (Tr31 to Tr34 are shown in FIG. 5) are formed in a P-type silicon substrate 1. In this example, the N-channel MOS transistors Tr11 to Tr44 serving as memory cells are formed in the P-type silicon substrate 1 using a general manufacturing method, and a detailed manufacturing method is omitted.
[0047]
Next, on the substrate 1 on which the N-channel MOS transistors Tr11 to Tr44 are formed, for example, BPSG or undoped SiO 2 is used by using LPCVD. ₂ Is deposited to form a first interlayer insulating film 5. The thickness of the interlayer insulating film 5 is, for example, about 1.0 μm. Further, there is a step due to the gate electrode (word line WL) on the substrate 1, and when the element isolation region 2 is formed using the LOCOS method, a step is formed between the element region and the element isolation region. Will occur. For this reason, the surface of the interlayer insulating film 5 is preferably planarized. An example of planarization is trichlorophosphoric acid (POCl ₃ ) In an atmosphere or a nitrogen (N) atmosphere, heat treatment is performed at a temperature of about 800 to 950 ° C., and then the surface of the interlayer insulating film 5 is flattened by using a CMP method (Chemical Mechanical Polishing). Next, a contact hole 6 reaching the drain diffusion layer D is formed in the interlayer insulating film 5. Next, a plug 7 is formed in the contact hole 6. The drain diffusion layer D, the contact hole 6 and the plug 7 are not shown in the cross section of FIG. 5 (however, they are shown in the cross section shown in FIG. 2). Next, a first metal wiring layer is formed on the interlayer insulating film 5 and the plug 7, and a local wiring 8 is formed. One example of the formation of the first layer metal wiring layer is that the barrier metal layer 21 is formed on the interlayer insulating film 5 and the plug 7, for example, a laminated film of a titanium film and a titanium nitride film, and the main conductive film 22 is made of, As the aluminum and copper alloy film and the antireflection film 23 in the lithography process, for example, a titanium nitride film is sequentially formed by sputtering. Next, the first metal wiring layer composed of the laminated film of the barrier metal layer 21, the main conductive film 22, and the antireflection film 23 is patterned using a lithography method, and the local wiring 8 electrically connected to the plug 7 is formed. Form. In FIG. 5, local wirings 8-31 to 8-34 are shown. Next, SiO 2 is deposited on the interlayer insulating film 5 and the local wiring 8 using a plasma CVD method. ₂ Is deposited to form a second interlayer insulating film 9. Here, in order to lower the dielectric constant of the interlayer insulating film 9, SiO 2 ₂ May be doped with fluorine (F). Then
The surface of the interlayer insulating film 9 is flattened using the CMP method. For the surface flattening, for example, a flattening technique similar to the surface flattening of the interlayer insulating film 5 can be used.
[0048]
Next, as shown in FIG. 6, a thin film 24 to be the stopper layer 11 is formed on the surface of the interlayer insulating film 9. The thin film 24 only needs to contain a substance capable of taking an etching selectivity with respect to the interlayer insulating film 9. In this example, as an example of the interlayer insulating film 9, SiO ₂ Is illustrated. Therefore, in this example, a laminated film including a titanium nitride film and a titanium film is used as one material example of the thin film 24. In one example of forming this laminated film, titanium is sputtered on the interlayer insulating film 9 to form a titanium film, and then titanium nitride is sputtered on the titanium film to form a titanium nitride film. The stacking order of titanium and titanium nitride may be reversed.
[0049]
Next, the thin film 24 is patterned to form the stopper layer 11. For the patterning, for example, a lithography technique is used. For the lithography technique, for example, a ROM code photomask 25 is used. In the ROM code photomask 25, the ROM code is programmed according to the presence or absence of the light shielding film 26, for example. The ROM code photomask 25 is prepared for each product having a different ROM code, for example. An example of forming the stopper layer 11 is as follows. First, as shown in FIG. 7, a photoresist is applied on the thin film 24 to form a photoresist film. Next, the photoresist film is exposed using the ROM code photomask 25, and the ROM code is transferred to the photoresist film. Next, the exposed photoresist film is developed to obtain a photoresist pattern 27 corresponding to the pattern of the stopper layer 11. Next, as shown in FIG. 8, the thin film 24 is dry processed using the photoresist pattern 27 as an etching mask to form the stopper layer 11. Here, for dry processing, RIE (Reactive Ion Etching) technology or CDE (Chemical Dry Etching) technology is used. Next, as shown in FIG. 9, the photoresist pattern 27 is peeled off by burning in an oxygen plasma atmosphere. In this way, the stopper layer 11 is formed.
[0050]
Next, a through hole 10 is formed in the interlayer insulating film 9. An example of formation of the through hole 10 is as follows. First, as shown in FIG. 10, a photoresist is applied on the interlayer insulating film 9 and the stopper layer 11 to form a photoresist film. Next, the photoresist film is exposed using a through-hole photomask 29 having a transmissive portion 28 corresponding to the through-hole pattern. Here, the transmission part 28 of the photomask 29 is formed for each of the memory cells Tr. For this reason, the pattern of the through hole 10 of the photomask 29 is common even if the products have different ROM codes. Next, the exposed photoresist film is developed to obtain a photoresist pattern 31 having an opening 30 corresponding to the pattern of the through hole 10. Next, as shown in FIG. 11, using the photoresist pattern 31 as an etching mask, the interlayer insulating film 9, the interlayer insulating film 9 can be easily etched, and the stopper layer 11 is difficult to etch. ₂ The interlayer insulating film 9 is easily etched, and the laminated film of titanium and titanium nitride (stopper layer 11) is etched using an RIE technique using an etchant that is difficult to etch to form a through hole 10 reaching the local wiring 8. To do. Here, in the region where the stopper layer 11 is present, the progress of etching is suppressed by the stopper layer 11, and thus the through hole 10 is not formed. Next, the photoresist pattern 31 is peeled off by burning in an oxygen plasma atmosphere. In this way, the through hole 10 is formed.
[0051]
Next, as shown in FIG. 12, the glue layer 32 is formed on the interlayer insulating film 9, in the through hole 10, and on the stopper layer 11. The glue layer 32 is a layer for improving the adhesion between the filling material of the through hole 10 and, for example, the interlayer insulating film 9. As an example of the glue layer 32, when the filling material of the through hole 10 is, for example, tungsten, titanium or a laminated film of titanium and titanium nitride can be used. The glue layer 32 is formed as necessary.
[0052]
Next, as shown in FIG. 13, tungsten is deposited on the glue layer 32 by using, for example, a CVD method to form a tungsten film 33. Next, as shown in FIG. 14, the tungsten film 33 is etched back by using, for example, an etch back method, leaving the tungsten film 33 in the through hole 10 and forming the plug 12.
[0053]
Next, as shown in FIG. 15, a barrier metal layer 34 is formed on the plug 12 and the glue layer 32. The barrier metal layer 34 is made of, for example, a laminated film of titanium and titanium nitride, and is formed on the plug 12 and the glue layer 32 by sequentially sputtering titanium and titanium nitride using, for example, a sputtering method. The
[0054]
Next, as shown in FIG. 16, the main conductive film 35 is formed on the barrier metal layer 34 by sputtering, for example, aluminum or an alloy of aluminum and copper by using a sputtering method, for example. Next, the antireflection film 36 is formed on the main conductive film 35 by sputtering, for example, using titanium nitride, for example. As a result, a second metal wiring layer 37 including the barrier metal layer 34, the main conductive film 35, and the antireflection film 36 is formed.
[0055]
Next, as shown in FIG. 17, a photoresist is applied on the second metal wiring layer 37 to form a photoresist film. Next, using a lithography technique, the photoresist film is exposed and developed to form a photoresist pattern 38 corresponding to the bit line pattern.
[0056]
Next, as shown in FIG. 18, the second-layer metal wiring layer 37 is patterned using the photoresist pattern 38 as a mask to form bit lines BL (BL1 to BL4). At this time, if the end portion of the stopper layer 11 protrudes from the bit line BL, the etching is performed simultaneously with the barrier metal layer 34. The stopper layer 11 in this example is a laminated film of titanium and titanium nitride. This laminated film is the same as the barrier metal layer 34. Further, this example is the same as the glue layer 32. Therefore, the stopper layer 11 is etched simultaneously with the barrier metal layer 34 and the glue layer 32, and the width of the stopper layer 11 along the row direction is the same as the width of the bit line BL along the row direction.
[0057]
According to the read-only semiconductor memory according to the first embodiment of the present invention, the ROM code is programmed depending on whether or not the stopper layer 11 is formed. The formation pattern of the stopper layer 11 is drawn on the ROM code photomask 25, for example. The ROM code photomask 25 can draw only the formation pattern of the stopper layer 11 and can be used only for the ROM code program. By using the ROM code photomask 25 only for the ROM code program, it is not necessary to correct the ROM code photomask 25 when a failure occurs in a circuit other than the read-only semiconductor memory. Therefore, when a problem occurs in a circuit other than the read-only semiconductor memory, it has been possible to eliminate the situation in which the photomask including the ROM code had to be corrected with all the products having different ROM codes. Can be suppressed. Of course, the period required for correction can also be shortened.
[0058]
The ROM code is programmed depending on whether or not the stopper layer 11 is formed. For this reason, the device up to the stage immediately before the formation of the stopper layer 11 can be a device commonly used in each IC product, so-called “matrix”. The “matrix” is a common structure for each IC product, and can be stocked, for example, in an IC production factory. Each IC product can be produced, for example, from a stocked “matrix”. For example, each IC product is produced from the “matrix” by changing the circuit connection state relative to the “matrix” and changing the ROM code.
[0059]
In the first embodiment, for example, the device at the stage where the second-layer interlayer insulating film 9 shown in FIG. 5 is formed, or the device at the stage where the thin film 24 serving as the stopper layer shown in FIG. Can be. The “matrix” shown in FIG. 5 or FIG. 6 is an apparatus at a stage close to the final process of IC manufacturing. For this reason, it is possible to reduce the manufacturing process after the “matrix”. The manufacturing process after the “matrix” determines the TAT of each IC product. If the manufacturing process after the “matrix” can be reduced, the advantage that TAT can be shortened can be obtained.
[0060]
FIG. 19 shows a comparison between the apparatus according to Patent Documents 1, 2, and 3 (Contact ROM, ion implantation ROM, Via ROM) and the apparatus according to the first embodiment. In FIG. 19, it is assumed that the manufacturing process of the device according to Patent Documents 1, 2, and 3 is combined with the manufacturing process of the device according to the first embodiment.
[0061]
As shown in FIG. 19, the “matrix” of the device according to the first embodiment is closer to the final process than the “matrix” of the device according to Patent Documents 1 and 2 (Contact ROM, ion-implanted ROM). Yes, it is the same stage as the apparatus according to Patent Document 3 (Via ROM). For this reason, the TAT of the device according to the first embodiment can be made equal to the TAT of the device according to Patent Document 3.
[0062]
Incidentally, the apparatus according to Patent Document 3 executes the ROM code program depending on whether or not to form a through hole. For this reason, when a failure occurs in a circuit other than the read-only semiconductor memory, the through-hole photomask must be corrected in all products having different ROM codes. Therefore, when a correction is required, a corresponding period and a corresponding cost are required for the correction. In this respect, as described above, in the apparatus according to the first embodiment, the pattern of the read-only semiconductor memory of the through-hole photomask 29 is common even for products having different ROM codes. For this reason, it is not necessary to verify the ROM code. For this reason, the apparatus according to the first embodiment is advantageous in shortening the time required for correction, for example, as compared with the apparatus according to Patent Document 3.
[0063]
Further, in the first embodiment, the width W of the stopper layer 11 along the row direction. ₁₁ Is the width W along the row direction of the bit line BL. _BL Is the same. But width W ₁₁ Is width W _BL For example, as shown in FIG. ₁₁ Is width W _BL It may be wider than. However, the stopper layer 11 is a conductive material and has a width W ₁₁ Width W _BL Same as or width W ₁₁ Width W _BL If it is narrower, there are the following advantages.
[0064]
For example, as shown in FIG. ₁₁ Width W _BL Wider than (W ₁₁ > W _BL ), In the portion where the stopper layer 11 exists, the parasitic capacitance (C _BL ) Is added with the parasitic capacitance of the stopper layer 11. Specifically, the parasitic capacitance (C _{11 LU} + C _{11 RU} ) And the parasitic capacitance (C _11LS + C _11RS ) Is the parasitic capacitance (C _BL ) For this reason, the parasitic capacitance of the bit line BL increases, and for example, the signal propagation speed of the bit line BL tends to decrease. Further, the number of stopper layers 11 connected to one bit line BL is usually different for each bit line BL. For this reason, the variation in parasitic capacitance for each bit line BL increases. Such a situation is disadvantageous in the case of a product that requires high speed operation.
[0065]
On the other hand, for example, as shown in FIG. ₁₁ Width W _BL Same as or width W ₁₁ Width W _BL Narrower than (W ₁₁ ≦ W _BL ), The parasitic capacitance (C11) of the exposed side surface of the stopper layer 11 to the parasitic capacitance (CBL) of the bit line BL itself. _LS + C11 _RS ) Just need to be added. For this reason, an increase in the parasitic capacitance of the bit line BL is suppressed as compared with the case shown in FIG. 21, which is advantageous, for example, in speeding up the operation.
[0066]
(Second Embodiment)
The second embodiment is an example of a microcontroller using the read-only semiconductor memory according to the first embodiment.
[0067]
FIG. 23 is a plan view showing an example of the layout of the microcontroller chip having the read-only semiconductor memory according to the first embodiment of the present invention, and FIG. 24 is a plan view showing an example of the stopper layer pattern.
[0068]
As shown in FIG. 23, the microcontroller chip 40 includes a CPU and various other circuits in addition to the read-only semiconductor memory (ROM area) according to the first embodiment. As shown in FIG. 24, the stopper layer 11 is formed on the ROM region where the read-only semiconductor memory is formed, and is not formed in any other region. Usually this pattern.
[0069]
However, when the stopper layer 11 is miniaturized, it becomes difficult to form a pattern of the stopper layer 11 gathered locally on a part of the chip. One reason for this is the difference in density of the pattern of the stopper layer 11. If the pattern of the stopper layer 11 includes a rough portion and a dense portion, for example, a microloading effect occurs in the pattern of the stopper layer 11. When the microloading effect occurs, the size of the stopper layer 11 changes, for example, between the outer peripheral portion and the inner portion of the read-only semiconductor memory. In order to suppress this phenomenon, in the second embodiment, a stopper layer (hereinafter referred to as a dummy stopper layer) is provided on an area other than the area of the read-only semiconductor memory.
[0070]
FIG. 25 is a plan view showing an example of a dummy stopper layer pattern of the microcontroller with a read-only semiconductor memory according to the first example of the second embodiment of the present invention.
[0071]
As shown in FIG. 25, in the device according to the first example, the stopper layer 11 is formed on the read-only semiconductor memory region (ROM region), and the stopper layer is formed on the region other than the read-only semiconductor memory region (ROM region). A dummy stopper layer 41 having the same island pattern as that of No. 11 is formed. By providing the dummy stopper layer 41, the stopper layers 11 and 41 are arranged almost evenly over the entire chip, and the difference in density of the patterns of the stopper layers 11 and 41 is compared with, for example, the apparatus shown in FIG. And relaxed. Therefore, for example, the microloading effect hardly occurs, and the stopper layer 11 is easily formed in the read-only semiconductor memory. For example, it is possible to suppress the size of the stopper layer 11 from changing between the outer peripheral portion and the inner portion of the read-only semiconductor memory, and the stopper layer 11 can be formed finely.
[0072]
FIG. 26 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller with a read-only semiconductor memory according to a second example of the second embodiment of the present invention.
[0073]
As shown in FIG. 26, in the apparatus according to the second example, the pattern of the dummy stopper layer 41 is changed from an island pattern to a hole pattern. The pattern of the dummy stopper layer 41 is not limited to an island pattern, and can be a hole pattern.
[0074]
When the dummy stopper layer 41 is a hole pattern, if the dummy stopper layer 41 is a conductive material, for example, the second metal wiring layers may be short-circuited via the dummy stopper layer 41. In this case, as described in the first embodiment, the dummy stopper layer 41 is etched using the mask for patterning the second metal wiring layer or the second metal wiring layer itself as a mask, The dummy stopper layer 41 may be confined under the second metal wiring layer.
[0075]
Further, regardless of whether the pattern of the dummy stopper layer 41 is an island pattern or a hole pattern, the dummy stopper layer 41 is, for example, a through hole connected to the first metal wiring layer in an area other than the read-only semiconductor memory. 10 is formed at a place where it is not formed. In other words, the dummy stopper layer 41 is formed in a region other than the read-only semiconductor memory other than where the through hole 10 is to be formed. For example, in the first example shown in FIG. 25, the dummy stopper layer 41 is formed in a region other than above the through hole 10, and in the second example shown in FIG. 26, the hole of the dummy stopper layer 41 is above the through hole 10. A pattern 42 is formed. Since the dummy stopper layer 41 is formed of a material that suppresses the formation of the through hole, the through hole 10 is not formed under the dummy stopper layer 41. If the through hole 10 is not formed at a location where the through hole 10 is to be formed, an erroneous wiring occurs.
[0076]
An example of a place where the through hole 10 is scheduled to be formed is above the conductor pattern in a layer below the dummy stopper layer 41, in this example, above the first metal wiring layer. Therefore, the dummy stopper layer 41 is preferably disposed, for example, avoiding the upper side of the first metal wiring layer.
[0077]
Furthermore, the through hole 10 does not pass through the layer where the first metal wiring layer is formed, but instead of the first metal wiring layer, toward the conductor pattern in a layer below the first metal wiring layer. Sometimes formed. For example, a gate electrode of a MOS transistor or a source / drain diffusion layer. Therefore, the dummy stopper layer 41 may be disposed so as to avoid further above the gate electrode of the MOS transistor or above the source / drain diffusion layer, that is, the active region.
[0078]
The dummy stopper layer 41 is not necessarily provided. For example, the pattern shown in FIG. 24 may be the pattern shown in FIG. 24 as long as the stopper layer 11 can be satisfactorily formed. The dummy stopper layer 41 may be provided as necessary.
[0079]
(Third embodiment)
The third embodiment is an example in which a dummy stopper layer is provided, as in the second embodiment. Although the formation position of the dummy stopper layer may be changed for each IC product, it is disadvantageous for a product (semi-custom) manufactured from a “matrix”. For example, it is necessary to change the formation position of the dummy stopper layer 41 for each IC product, and it takes time to manufacture the ROM code mask. This leads to a prolonged TAT.
[0080]
The third embodiment relates to a microcontroller with a read-only semiconductor memory having a dummy stopper layer that can suppress the lengthening of TAT.
[0081]
FIG. 27 is a plan view showing an example of a dummy stopper layer pattern of the microcontroller with a read only semiconductor memory according to the first example of the third embodiment of the present invention.
[0082]
As shown in FIG. 27, the device according to the first example is an IC in which a region (wiring track) for laying wiring is secured in advance. Such ICs are found in, for example, gate array ICs, SOG (Sea Of Gate) ICs, standard cell ICs, cell base ICs, and the like. In these devices, for example, a first metal wiring layer wiring track 50 and a second metal wiring layer wiring track 51 are secured in advance, and the wiring tracks 50 and 51 are used to A first metal wiring layer and a second metal wiring layer are laid. An intersection 52 between the first-layer metal wiring layer wiring track 50 and the second-layer metal wiring layer track 51 is a region where a through hole that connects the second-layer metal wiring layer to the first-layer metal wiring layer can be formed. . In other words, it is a place where the formation of a through hole is planned. Therefore, in the apparatus according to the example of the third embodiment, the dummy stopper layer 41 is disposed in a region other than the area above the intersection 52 while avoiding the area above the intersection 52. Thereby, the pattern of the dummy stopper layer 41 does not need to be changed even when the position of the through hole changes. Accordingly, it is possible to shorten the time required for manufacturing the ROM code mask, and to suppress the lengthening of the TAT.
[0083]
FIG. 28 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller with a read-only semiconductor memory according to a second example of the third embodiment of the present invention.
[0084]
As shown in FIG. 28, the device according to the second example is an example in which the dummy stopper layer 41 of the device according to the first example is a hole pattern. In this case, the hole pattern 42 of the dummy stopper layer 41 is disposed above the intersection 52. Thus, as in the first example, the pattern of the dummy stopper layer 41 does not need to be changed even when the position of the through hole changes. Accordingly, it is possible to shorten the time required for manufacturing the ROM code mask, and to suppress the lengthening of the TAT.
[0085]
FIG. 29 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller with a read-only semiconductor memory according to a third example of the third embodiment of the present invention.
[0086]
In the first and second examples, the intersection between the wiring tracks is regarded as a place where the formation of a through hole is planned, and the dummy stopper layer 41 is arranged avoiding the intersection.
[0087]
The third example is an IC in which a region 53 for forming a through hole is secured in advance. Such an IC is used when, for example, regions 53 for forming through holes are present at random. The second level metal wiring layer is arranged and connected so as to connect the regions 53 to each other. Such ICs are also found in, for example, gate array ICs, SOG (Sea Of Gate) ICs, standard cell ICs, cell base ICs, and the like, as in the first and second examples. The region 53 is a place where a through hole is to be formed. Therefore, the dummy stopper layer 41 is disposed in a region other than the region 53 and avoiding the region 53. There are several examples of determining whether or not it is the region 53, but representative examples are as follows.
[0088]
(1) Whether there is a wide portion (fringe) 54 in the conductor pattern in the layer below the dummy stopper layer 41, in this example, the first metal wiring layer and the gate electrode. A portion having the fringe 54 is a region 53 for forming a through hole.
[0089]
(2) Whether it is above the active area AA. The active region AA is a source / drain of the transistor, and is a region to which the first metal wiring layer and the second metal wiring layer are connected. The active area AA is an area 53 for forming a through hole.
[0090]
(3) When there is no fringe in the conductor pattern in the layer below the dummy stopper layer 41, in this example, the first metal wiring layer or the gate electrode, it is connected to another conductor pattern (plug or contact) Whether there is a hole or through hole) 55. Normally, a through hole is not formed in a portion where the connection point 55 is present. In other words, the portion without the connection point 55 is a region where a through hole can be formed. Therefore, a portion having no connection portion is regarded as a region 53 for forming a through hole.
[0091]
Of course, these are some typical examples, and the determination of the region 53 is not limited to these.
[0092]
As described above, by disposing the dummy stopper layer 41 in a region other than the region 53 above, avoiding the region 53 for forming the through-hole, the dummy stopper layer 41 is formed in the same manner as in the first and second examples. The pattern 41 does not need to be changed even when the position of the through hole changes. Accordingly, it is possible to shorten the time required for manufacturing the ROM code mask, and to suppress the lengthening of the TAT.
[0093]
FIG. 30 is a plan view showing a microcontroller with a read-only semiconductor memory according to a fourth example of the third embodiment of the present invention.
[0094]
As shown in FIG. 30, the device according to the fourth example is an example in which the dummy stopper layer 41 of the device according to the third example is a hole pattern. In this case, the hole pattern 42 of the dummy stopper layer 41 is disposed above the region 53 for forming a through hole. Thereby, like the first to third examples, the pattern of the dummy stopper layer 41 does not need to be changed even when the position of the through hole is changed. Accordingly, it is possible to shorten the time required for manufacturing the ROM code mask, and to suppress the lengthening of the TAT.
[0095]
As mentioned above, although this invention was demonstrated by 1st-4th embodiment, this invention is not limited to each of these embodiment, In the implementation, it changes variously in the range which does not deviate from the summary of invention. It is possible.
[0096]
In addition, each of the above embodiments can be carried out independently, but it is of course possible to carry out a combination of them as appropriate.
[0097]
The above embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.
[0098]
In each of the above embodiments, the present invention has been described based on the example in which the present invention is applied to the read-only semiconductor memory and the microcontroller including the read-only semiconductor memory. However, the semiconductor integrated circuit including the read-only semiconductor memory as described above. Circuit devices such as processors, system LSIs, and the like are also within the scope of the present invention.
[0099]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device having a read-only semiconductor memory capable of suppressing an increase in manufacturing cost and shortening a time required for correction, and a manufacturing method thereof.
[Brief description of the drawings]
FIG. 1 is a plan view showing a plane pattern example of a read-only semiconductor memory according to a first embodiment of the present invention;
FIG. 2 is a sectional view taken along line II-II in FIG.
3 is a cross-sectional view taken along line III-III in FIG.
FIG. 4 is an equivalent circuit diagram of the read-only semiconductor memory according to the first embodiment of the invention.
FIG. 5 is a sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 6 is a sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 7 is a cross-sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 8 is a cross-sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 9 is a sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 10 is a cross-sectional view showing the main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the invention.
FIG. 11 is a cross-sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 12 is a sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 13 is a cross-sectional view showing the main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the invention.
FIG. 14 is a cross-sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 15 is a cross-sectional view showing the main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 16 is a cross-sectional view showing the main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 17 is a cross-sectional view showing main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 18 is a cross-sectional view showing the main manufacturing steps of the read-only semiconductor memory according to the first embodiment of the invention.
FIG. 19 is a comparison diagram of an apparatus according to a known document and an apparatus according to the first embodiment.
FIG. 20 is a plan view showing a read-only semiconductor memory according to a modification of the first embodiment of the present invention.
FIG. 21 is a diagram showing parasitic capacitance of a read-only semiconductor memory according to a modification of the first embodiment of the present invention.
FIG. 22 is a diagram showing parasitic capacitance of the read-only semiconductor memory according to the first embodiment of the present invention.
FIG. 23 is a plan view showing an example of a layout of a microcontroller chip having a read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 24 is a plan view showing an example of a stopper layer pattern of a microcontroller chip having a read-only semiconductor memory according to the first embodiment of the present invention;
FIG. 25 is a plan view showing an example of a dummy stopper layer pattern of the microcontroller chip according to the first example of the second embodiment of the present invention;
FIG. 26 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller chip according to a second example of the second embodiment of the present invention;
FIG. 27 is a plan view showing an example of a dummy stopper layer pattern of the microcontroller according to the first example of the third embodiment of the present invention;
FIG. 28 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller according to a second example of the third embodiment of the present invention;
FIG. 29 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller according to a third example of the third embodiment of the present invention;
FIG. 30 is a plan view showing an example of a dummy stopper layer pattern of a microcontroller according to a fourth example of the third embodiment of the present invention;
FIG. 31 is a plan view of a LOCOS ROM.
FIG. 32 is a plan view of the Contact ROM.
FIG. 33 is a plan view of an ion implantation type ROM.
FIG. 34 is a plan view of an AL ROM.
FIG. 35 is a plan view of a Via ROM.
FIG. 36 is a sectional view of a Via ROM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... Element isolation region, 3 ... Gate insulating film, 5 ... 1st layer interlayer insulating film, 6 ... Contact hole, 7 ... Plug, 8 ... Local wiring, 9 ... 2nd layer interlayer insulating film DESCRIPTION OF SYMBOLS 10 ... Through hole, 11 ... Stopper layer, 12 ... Plug, 21 ... Barrier metal layer, 22 ... Main conductive film, 23 ... Antireflection film, 24 ... Thin film used as stopper layer, 25 ... Photomask for ROM code, 26 DESCRIPTION OF SYMBOLS ... Shading film | membrane, 27 ... Photoresist pattern, 28 ... Transmission part, 29 ... Photomask for through hole, 30 ... Opening, 31 ... Photoresist pattern, 32 ... Glue layer, 33 ... Tungsten film, 34 ... Barrier metal layer, 35 ... Main conductive film 36 ... Antireflection film 37 ... Second metal wiring layer 38 ... Photoresist pattern 40 ... Microcontroller chip 41 ... Dummy stopper layer 42 ... 50 ... 1st metal wiring layer wiring track, 51 ... 2nd metal wiring layer wiring track, 52 ... intersection of wiring tracks, 53 ... region for forming a through hole, 54 ... fringe, 55 ... connection point.

Claims (15)

A transistor provided on a semiconductor substrate and having a gate as a word line;
An interlayer insulating film provided on the semiconductor substrate provided with the transistor;
A stopper layer containing a substance different from the interlayer insulating film, selectively provided according to information to be programmed, on the interlayer insulating film located above one end of the current path of the transistor;
A conductive layer selectively provided in the interlayer insulating film depending on the presence or absence of the stopper layer and connected to one end of the current path of the transistor;
A semiconductor integrated circuit device comprising: the interlayer insulating film; the conductive layer; and a bit line provided on the stopper layer. 2. The semiconductor integrated circuit device according to claim 1, wherein one end of the current path of the transistor is connected to a wiring layer existing above the word line, and the wiring layer is below the bit line. 3. The semiconductor integrated circuit device according to claim 1, wherein the width of the stopper layer is the same as the width of the bit line. The bit line has a stacked structure of a barrier conductive layer and a main conductive layer stacked on the barrier conductive layer and including a conductive material different from the barrier conductive layer,
4. The semiconductor integrated circuit device according to claim 3, wherein the stopper layer is made of a conductive layer having the same conductive material as the barrier conductive layer. 5. The semiconductor integrated circuit device according to claim 4, wherein the stopper layer includes any one of titanium nitride and a laminated structure of titanium nitride and titanium. The semiconductor integrated circuit device is a microcontroller including a read-only semiconductor memory and an integrated circuit other than the read-only semiconductor memory,
The semiconductor integrated circuit device according to claim 1, wherein the transistor is integrated in the read-only semiconductor memory. The stopper layer is provided above the read-only semiconductor memory and above an integrated circuit other than the read-only semiconductor memory,
7. The semiconductor integrated circuit device according to claim 6, wherein a stopper layer provided above the integrated circuit other than the read-only semiconductor memory is provided at a place other than a place where the through hole is to be formed. . 8. The stopper layer provided above the integrated circuit other than the read-only semiconductor memory is provided other than above the conductor pattern in a layer below the stopper layer. Semiconductor integrated circuit device. 8. The semiconductor integrated circuit device according to claim 7, wherein the stopper layer provided above the integrated circuit other than the read-only semiconductor memory is provided other than above the intersection of the wiring tracks. The stopper layer provided above the integrated circuit other than the read-only semiconductor memory is provided above the portion other than the fringe portion of the conductor pattern in the layer below the stopper layer. A semiconductor integrated circuit device according to claim 7. 8. The semiconductor integrated circuit device according to claim 7, wherein the stopper layer provided above the integrated circuit other than the read-only semiconductor memory is provided above the active region. The stopper layer provided above the integrated circuit other than the read-only semiconductor memory is composed of a conductor pattern in a layer below the stopper layer and a conductor pattern in a layer below the conductor pattern. 8. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is provided above a portion other than a portion where there is no connection portion. Forming a transistor having a gate as a word line on a semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate on which the transistor is formed;
A step of selectively forming a stopper layer containing a material different from the interlayer insulating film on the interlayer insulating film located above one end of the current path of the transistor according to programmed information;
Selectively forming a conductive layer connected to one end of a current path of the transistor in the interlayer insulating film according to the presence or absence of the stopper layer;
Forming a bit line on the interlayer insulating film, the conductive layer, and the stopper layer. A method for manufacturing a semiconductor integrated circuit device, comprising: 14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein a mask dedicated to a program is used in the step of forming the stopper layer. 15. The mask dedicated to programming includes a stopper layer pattern corresponding to programmed information and a dummy stopper layer pattern unrelated to the programmed information. Of manufacturing a semiconductor integrated circuit device.

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