JP2005005368A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a fine shared contact used for a high-density semiconductor device to stably maintain electrical contact characteristics and, in addition, to prevent the occurrence of electrical junction leaks due to the contact. <P>SOLUTION: Firstly, the gate electrode-side overlapping amount of the shared contact having a length of ≤0.5 μm is adjusted to 0.02-0.10 μm. Secondly, the junction depth of the first diffusion layer of the shared contact is made deeper than that of the second diffusion layer of the contact. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-density semiconductor device, and more particularly to a contact structure in which simultaneous contacts are formed in different layers.
[0002]
[Prior art]
As the density of semiconductor devices increases, new contact structures have been developed along with miniaturization of wiring patterns. Hereinafter, a conventional semiconductor device will be described with reference to FIG. FIG. 6 shows a cross-sectional view of a conventional semiconductor device.
[0003]
As shown in FIG. 6, an isolation oxide film (1002) is formed on an N-type silicon substrate (1001). Next, a gate oxide film (1003) is formed, and a gate electrode (1004) is formed thereon. A P-type diffusion layer 1 (1006) is formed beside the gate electrode, and a sidewall insulating film (1005) is formed beside the gate electrode. A P-type diffusion layer 2 (1007) is formed on the side of the sidewall, and an interlayer insulating film (1008) is formed on the upper side thereof. The contact hole (1009) is formed by removing the interlayer insulating film (1008) by etching. At this time, since the gate electrode (1004) made of CoSi ₂ / polysilicon is not etched, it remains at the bottom of the contact hole (1009). Thus, the contact hole (1009) forms a so-called shared contact that connects the gate electrode (1004) and the P-type diffusion layer 2 (1007) (see, for example, Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 3-316308
[Problems to be solved by the invention]
However, in the above configuration, particularly when the contact size is a small opening diameter of 0.5 μm or less, first, it is difficult to obtain electrical contact characteristics, and second, etching with the sidewall insulating film at the time of contact opening. The contact has reached the P-type diffusion layer 1 without ensuring a sufficient selection ratio, and further, etching to the P-type diffusion layer 1 causes an electrical junction leak.
[0006]
In view of the above-mentioned problems, the present invention firstly maintains stable electrical contact characteristics in a fine shared contact used in a high-density semiconductor device, and secondly prevents electrical junction leakage caused by the contact. The purpose is to do.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the semiconductor device according to the present invention firstly sets the overlap amount on the gate electrode side to 0.02 μm or more and 0.10 μm or less in a shared contact having a long side of 0.5 μm or less, Secondly, the first diffusion layer is provided with a depth deeper than that of the second diffusion layer.
[0008]
As a result, it is possible to construct a high-density shared contact that firstly maintains stable electrical contact characteristics with respect to the diffusion layer and secondly does not cause electrical junction leakage.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0010]
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. In FIG. 1, an isolation oxide film (102) is formed on an N-type silicon substrate (101), and a gate insulating film (103) is further formed on the silicon substrate. A gate electrode (104) having a CoSi ₂ / polysilicon laminated structure is formed on the gate insulating film, and a sidewall insulating film (105) is formed beside the gate electrode. A P-type diffusion layer 1 (106) is formed under the sidewall insulating film, and a P-type diffusion layer 2 (107) having a CoSi ₂ layer on the surface is formed beside it. An interlayer insulating film (108) is formed on the gate electrode, the P-type diffusion layer 2, and the isolation oxide film, and a contact hole (109) is formed by opening the interlayer insulating film.
[0011]
Here, the size of the contact hole is a rectangle of 0.39 × 0.16 μm ² , the overlap amount 1 (Lg) between the gate electrode and the contact hole is 0.09 μm, and the P-type diffusion layer 2 And the contact hole overlap amount 2 (Ld) is 0.23 μm.
[0012]
FIG. 2 shows each overlap amount and electrical contact characteristics. FIG. 2A shows the contact resistance value with respect to the overlap amount 1 on the gate electrode side, and FIG. 2B shows the P-type diffusion layer 2. The contact resistance value with respect to the overlap amount 2 on the side is shown. From the figure, the overlap amount 1 shows a sufficiently low contact resistance value (about 15Ω) even at 0.06μm, but the overlap amount 2 has already reached 30Ω at the time of 0.12μm, and the variation is also compared with the gate electrode side. It can be seen that it is big.
[0013]
FIG. 2C shows the contact resistance value with respect to the overlap amount 1 on the gate electrode side when the contact hole diameter is 0.16 μmφ. From the drawing, it can be seen that the resistance value is sufficiently low even when the overlap amount 1 is 0.02 μm (lower limit value).
[0014]
Next, FIG. 3 is a plan view showing the layout of this embodiment. In FIG. 3, 301 is an isolation insulating film region, 302 is a sidewall insulating film region, 303 is a gate electrode region, 304 is a P-type diffusion layer 2 region, and 305 is a contact region.
[0015]
Here, since the mask alignment margin between the contact hole and the gate electrode determined by the exposure apparatus is 0.07 μm, the minimum design value of each overlap amount is obtained as follows from the above result.
[0016]
The minimum design value (upper limit value) of the overlap amount 1 is Lg = 0.02 μm + 0.07 μm = 0.09 μm. The minimum design value of the overlap amount 2 is Ld = 0.12 μm + 0.07 μm = 0.19 μm. The width of the sidewall insulating film is 0.07 μm.
[0017]
Thus, by setting the overlap amount 1 (Lg) on the gate electrode side to 0.02 μm or more and 0.10 μm or less, it is possible to form a high-density shared contact while maintaining electrical contact characteristics. it can.
[0018]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0019]
FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to this embodiment. In FIG. 4, an isolation oxide film (402) is formed on an N-type silicon substrate (401), and a gate insulating film (403) is formed on the silicon substrate. A gate electrode (404) having a CoSi ₂ / polysilicon laminated structure is formed on the gate insulating film, and a sidewall insulating film (405) is formed beside the gate electrode. A P-type diffusion layer 1 (406) is formed under the sidewall insulating film, and a P-type diffusion layer 2 (407) having a CoSi ₂ layer on the surface is formed beside it. An interlayer insulating film (408) is formed on the gate electrode, the P-type diffusion layer 2, and the isolation oxide film, and a contact hole (409) is formed by opening the interlayer insulating film. At this time, the diffusion depth of the P-type diffusion layer 1 is set deeper than the diffusion depth of the P-type diffusion layer 2.
[0020]
On the other hand, FIG. 5 shows a cross-sectional view when the sidewall insulating film has been etched during contact formation. In FIG. 5, an isolation oxide film (502) is formed on an N-type silicon substrate (501), and a gate insulating film (503) is formed on the silicon substrate. A gate electrode (504) having a CoSi ₂ / polysilicon laminated structure is formed on the gate insulating film, and a side wall insulating film (505) is formed beside the gate electrode. A P-type diffusion layer 1 (506) is formed under the sidewall insulating film, and a P-type diffusion layer 2 (507) having a CoSi ₂ layer on the surface is formed beside the P-type diffusion layer 1 (506). An interlayer insulating film (508) is formed on the gate electrode, the P-type diffusion layer 2, and the isolation oxide film, and a contact hole (509) is formed by opening the interlayer insulating film.
[0021]
Here, the diffusion depth of the P-type diffusion layer 1 is deeper than the diffusion depth of the P-type diffusion layer 2. Therefore, even when the sidewall insulating film (505) is completely etched during the processing of the contact hole (509), as shown in FIG. There is no cause of static junction leakage.
[0022]
In this way, by setting the diffusion depth of the P-type diffusion layer 1 deeper than the diffusion depth of the P-type diffusion layer 2, it is possible to form a high-density shared contact that does not cause electrical junction leakage.
[0023]
In addition, although 1st Embodiment and 2nd Embodiment may be implemented separately, it cannot be overemphasized that the synergistic effect by both will be acquired if it implements simultaneously.
[0024]
In the first embodiment and the second embodiment, the interlayer insulating film is formed of a single layer, but may be formed of a laminated film.
[0025]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, in a fine shared contact having a long side of 0.5 μm or less, first, the overlap amount on the gate electrode side is set to 0.02 μm or more and 0.10 μm or less. Second, by providing the junction depth of the first diffusion layer deeper than the junction depth of the second diffusion layer, first, stable electrical contact characteristics are maintained for the diffusion layer, and second, the electrical It is possible to configure a high-density shared contact that does not cause static junction leakage.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing electrical contact characteristics according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. Sectional view of the device [Explanation of symbols]
101, 401, 501 Silicon substrate 102, 402, 502 Isolation oxide film 103, 403, 503 Gate oxide film 104, 404, 504 Gate electrode 105, 405, 505 Side wall insulating film 106, 406, 506 P-type diffusion layer 1
107, 407, 507 P-type diffusion layer 2
108, 408, 508 Interlayer insulation film 109, 409, 509 Contact hole 301 Isolation insulation film region 302 Side wall insulation film region 303 Gate electrode region 304 P-type diffusion layer 2 region 305 Contact region 1001 Silicon substrate 1002 Isolation oxide film 1003 Gate oxidation Film 1004 Gate electrode 1005 Side wall insulating film 1006 P-type diffusion layer 1
1007 P-type diffusion layer 2
1008 Interlayer insulating film 1009 Contact hole

Claims (5)

A conductive layer formed on a semiconductor substrate via an insulating film;
A sidewall insulating film formed on a side surface of the conductor layer;
A first diffusion layer formed on the semiconductor substrate under the sidewall insulating film;
A second diffusion layer formed on the semiconductor substrate next to the first diffusion layer;
An interlayer insulating layer covering the conductor layer and formed on the semiconductor substrate;
A contact hole formed in the interlayer insulating layer, straddling the conductor layer, the sidewall insulating film, and the second diffusion layer, and having an opening having a long side of 0.5 μm or less;
An overlap between the conductor layer and the contact hole is 0.02 μm or more and 0.10 μm or less. A conductive layer formed on a semiconductor substrate via an insulating film;
A sidewall insulating film formed on a side surface of the conductor layer;
A first diffusion layer formed on the semiconductor substrate under the sidewall insulating film;
A second diffusion layer formed on the semiconductor substrate next to the first diffusion layer;
An interlayer insulating layer covering the conductor layer and formed on the semiconductor substrate;
A contact hole formed in the interlayer insulating layer, straddling the conductor layer, the sidewall insulating film, and the second diffusion layer, and having an opening having a long side of 0.5 μm or less;
The semiconductor device according to claim 1, wherein a junction depth of the first diffusion layer is deeper than a junction depth of the second diffusion layer. The semiconductor device according to claim 2, wherein an overlap between the conductor layer and the contact hole is 0.02 μm or more and 0.10 μm or less. The semiconductor device according to claim 1, further comprising a silicide layer formed on a surface of the conductor layer and the second diffusion layer. 5. The semiconductor device according to claim 1, wherein the first diffusion layer and the second diffusion layer have the same polarity.

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