JP2005091646A - Active matrix substrate, display device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage current of a multi-gate type pixel transistor. <P>SOLUTION: Capacitances (Cgd) between gate and drain lines of transistor steps on the side near to a data line are increased and those on the side near to a pixel electrode are decreased in the multi-gate type transistor. Thereby, gate reverse bias given to the pixel transistor can be relaxed by using a feedthrough. An appropriate capacitance Cgd is specified from a leakage amount of the transistor and an image refreshing rate. A structure for giving the further appropriate Cgd is provided. An element for charge is disposed at a conductive part between transistor steps. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix substrate using a multi-gate transistor, a liquid crystal display device, and a portable electronic device.

  In a liquid crystal display device using a thin film transistor (TFT) element as a pixel switching element, a leakage current of a TFT element during a non-writing period leads to a display quality deterioration such as flicker or a reliability problem such as burn-in. Various methods have been proposed. One of them is a multi-gate structure proposed in Patent Document 1, which reduces leakage current by dividing a source-drain voltage applied to one transistor by connecting a plurality of thin film transistors in series. It is to measure. Hereinafter, a conventional multi-gate transistor will be described with reference to FIGS.

  FIG. 1 is an enlarged schematic view of a pixel on an active matrix substrate using a top gate type multi-gate (triple gate) N-channel transistor as a pixel switching element. A pixel electrode (402) and a Si island (222) are arranged at each intersection of the scanning line (201) and the data line (202), and a first gate electrode (211a) connected to the scanning line (201), respectively. The second gate electrode (211b) and the third gate electrode (211c) are disposed so as to partially overlap the Si island (222). The data line (202) and the pixel electrode (402) are electrically connected to the Si island (222) through the contact holes, respectively, and the capacitor line (203) is arranged in parallel with the scanning line (201) to thereby form the Si island (222). Auxiliary capacitance (Cs) is formed by overlapping.

  FIG. 2 is a cross-sectional view taken along the line A-A 'of FIG. The first to third channel portions (221a, 221b, 221c) that overlap the first to third gate electrodes (211a, 211b, 211c) and the gate insulating film (240) are intrinsically not implanted with ions. It is made of a semiconductor and operates as a transistor channel. The data line junction (223) connected to the data line (202), the pixel electrode junction (224) connected to the pixel electrode, the first channel portion (221a) and the second channel portion (221b). A first inter-transistor conductive portion (222a) arranged in the middle and connecting each other, a second channel portion (221b) and a second channel portion (221c) arranged in the middle to connect each other The inter-transistor conductive portion (222b) is a conductive portion (n + layer) in which, for example, phosphorus ions are implanted at a high concentration.

FIG. 3 is a circuit diagram of a pixel portion in the case where a liquid crystal display device is formed using this active matrix substrate. The first transistor (205a), the second transistor (205b), and the third transistor (205c) are connected in series, one end is connected to the data line (202), and the opposite end is opposed to the liquid crystal. A substrate electrode and a capacitor (Clc) are formed, and an auxiliary capacitor (Cs) is formed in parallel with the capacitance line. The counter substrate electrode and the capacitor line are each connected to the same fixed potential (Vcom). On the other hand, as apparent from FIG. 1, since the scanning line (201) and the data line (202) form an intersection, a capacitance (Cgs) is formed here. As is clear from FIG. 2, the first inter-transistor conductive portion (222a) forms a capacitance (Cgd ₁ ) with the first gate electrode (211a) and the second gate electrode (211b), and the second The inter-transistor conductive portion (222b) forms a capacitor (Cgd ₂ ) with the second gate electrode (211b) and the third gate electrode (211c). The pixel electrode connection portion (224) also forms a capacitor (Cgd _pix ) with the third gate electrode (211c). Depending on the arrangement of the pixels, each capacitance between the scanning line (201) and the first inter-transistor conductive portion (222a), the second inter-transistor conductive portion (222b), and the pixel electrode connecting portion (224) cannot be ignored. Will be added to these.

Furthermore, when the channel length (L) of the transistor is sufficiently small (L ≦ 10 μm), the data line junction (223) and the first inter-transistor conductive portion (222a) form a capacitance (Csd ₁ ) in the horizontal direction. Similarly, the first transistor-to-transistor conductive part (222a) and the second transistor-to-transistor conductive part (222b) have a capacitance (Csd ₂ ), and the second transistor-to-transistor conductive part (222b) and the pixel electrode junction (224). Also forms a capacitance (Csd ₃ ). Further, depending on the pixel structure, the first inter-transistor conductive portion (222a) and the second inter-transistor conductive portion (222b) have a capacitance (C) with an electrode that can be regarded as a fixed potential, such as an adjacent pixel electrode, a capacitor line, or a counter electrode. _ex1 , _Cex2 ).

In the case of a liquid crystal display device using a general active matrix substrate, if each transistor stage is configured in the same manner, the value of each capacitance is Cs> Clc >>Cgs> Cgd ₁ ≈Cgd ₂ = 2 · Cgd _pix > In general, Csd ₁ ≈Csd ₂ ≈Csd ₃ . However, the magnitude relationship between Csd _{1 to 3} may vary greatly depending on the structure of the pixel transistor, and in some cases, _{one of} Csd _{1 to 3} may be larger than Cgd ₁ and Cgd ₂ . Although C _ex1 and C _{ex2 depend} on the film thickness and the pixel structure, they are almost equal _{to each other} less than Cgd _1-3 .

  In this way, by using a plurality of transistors connected in series, the source-drain voltage of each transistor is divided, and the leakage current that flows when a gate reverse bias (gate potential-source potential <0) is applied is reduced. Can do. Therefore, it is preferable that the number of transistor stages is as large as possible because the number of divisions increases. Such a countermeasure is particularly effective in the case of a transistor using a polysilicon thin film having a large leakage current when the gate reverse bias is high. In addition, since the voltage applied to the drain end is also divided in the multi-gate structure during the switching operation of the transistor, the multi-gate structure is also effective in preventing deterioration of transistor characteristics due to hot carriers.

  In this example, the self-alignment structure in which the gate electrode and the intrinsic semiconductor are equal in length and the high-concentration implantation region and the intrinsic semiconductor region are in direct contact is illustrated. However, as described in Patent Document 2, each transistor has an LDD structure. If so, the off-current is further reduced.

  Further, as in Patent Document 3, in order to minimize the pixel electrode voltage effect due to the leakage current while holding the TFT, a fixed potential is applied to the first inter-transistor conductive portion (222a) and the second inter-transistor conductive portion (222b). A configuration is also proposed in which another capacitor facing the electrode (Vcom or the like) is disposed.

Japanese Patent Publication No. 5-44195 Japanese Patent No. 3343160 Japanese Patent No. 3161668

  In the conventional multi-gate structure, the leakage current at the gate reverse bias can be reduced as the number of stages is increased. However, when the number of stages is increased, the circuit area increases and the aperture ratio decreases. In addition, a large storage capacitor is required to determine the storage capacitor assuming the worst case with respect to variations in the video signal and the transistor threshold voltage, which also reduces the aperture ratio.

  The present invention proposes a structure in which the leakage current is further reduced without increasing the number of stages, and the leakage amount is substantially constant regardless of the input video signal and the threshold value of the transistor.

In the present invention, when an n-stage multi-gate thin film transistor is used as a pixel switching element, the capacitance between the conductive portions between the transistors and the gate electrode is Cgd ₁ to _n-1 (however, the smaller number is closer to the data line) And when the electric capacitance between the pixel electrode junction and the gate electrode is Cgd _pix , at least one of Cgd _{1 to n-1} is configured to be larger than twice Cgd _pix. A matrix substrate is proposed. Thus, the inter-transistor conductive portion is sufficiently reduced by utilizing the feedthrough of the gate electrode, the gate reverse bias is reduced, and the leakage current is reduced.

Further, in the present invention, the number of transistor stages is set to 3 or more (n ≧ 3), and the capacitance (Cgd ₁ ) of the inter-transistor conductive portion closest to the data line is larger than twice the Cgd _pix , and further between the transistors closest to the pixel electrode It is proposed to make it larger than the capacitance (Cgd _n-1 ) of the conductive part. As a result, the leakage current can be reduced and the voltage drop due to the feedthrough of the pixel electrode can be minimized.

Further, in the present invention, as a more specific value of Cgd _{1 to n−1} , the maximum potential difference (Vmax) between the non-selection potential of the scanning line and the video signal potential applied to the data line is determined as the drain − when the source electrode between the respective currents _{I 1 (Vg) ~I n (} Vg) - when applied as source potential (Vds = Vmax), drain as parameters the potential (= Vg) to be applied to the gate electrode It is proposed that each minimum value is Imin _{1 to} Imin _n and the display refresh period is TR, which is larger than (Imin _m + Imin _{m + 1} ) × TR. As a result, no matter what video signal is input to the data line, the potential of the conductive portion between transistors moves only about 1 V from the minimum point during the period when the non-selection potential is applied to the gate, and the leakage current is reversed. The increase due to the bias can be suppressed.

Furthermore, the present invention proposes a structure in which a capacitor is formed by overlapping a part of the inter-transistor conductive portion closest to the data line with an electrode connected to the scanning line. Thereby, Cgd ₁ can be easily larger than twice the Cgd _pix and larger than Cgd _n−1 .

Furthermore, in the present invention, the source / drain portion connected to the pixel electrode of the transistor has an offset structure or LDD (Lightly Doped Drain) structure, and at least one of the source / drain portion connected to the inter-transistor conductive portion has an offset structure and an LDD structure. We propose to shorten the offset length and LDD length. As a result, Cgd ₁ to _n-1 can be easily made larger than twice the Cgd _pix .

Furthermore, in the present invention, at least one of the source / drain portions connected to the conductive portion between the transistors has a GOLDD (Gate Overlapped Lightly Doped Drain) structure or a GOD (Gate Overlapped Drain) structure, and the source / drain portion connected to the pixel electrode is GOLDD.・ We propose not to use GOD structure. Thereby, Cgd ₁ to _n-1 can be easily made larger than twice Cgd _pix .

Further, the present invention proposes that the channel width of the transistor stage closest to the pixel electrode is the smallest and the channel width of the transistor stage closest to the data line is the largest. As a result, Cgd ₁ to _n-1 can be easily larger than twice the Cgd _pix and larger than Cgd _n-1 .

  Further, in the present invention, when the thin film transistor is an n-channel type in the inter-transistor conductive portion closest to the data line during the holding period in which the pixel switching element is OFF, a potential lower than that of either the data line or the pixel electrode is set to p. In the case of the channel type, it is proposed to give a high potential. This prevents the gate reverse bias from being increased due to leakage during the holding period, thereby increasing the leakage current.

  Further, in the present invention, as means for applying the potential of the preceding paragraph, a transistor having a conductivity type opposite to that of the pixel switching element is arranged for each pixel, its gate and source electrode are connected to the scanning line, and its drain electrode is the first transistor. It is proposed to connect between the scanning line and the first inter-transistor conductive part, or connect a resistor having a resistance value intermediate between the ON resistance and the OFF resistance of the first transistor. Accordingly, the first conductive portion is kept at an appropriate potential while the non-selection potential is applied to the scanning line.

  Furthermore, the present invention proposes that the transistor of the pixel switching element is a polysilicon thin film transistor. The polysilicon thin film transistor is a device having a particularly large leakage current at the gate reverse bias, and the effect of the present invention becomes more remarkable.

  Furthermore, the present invention proposes a liquid crystal display device using the above active matrix substrate. According to this, since the leakage current during the holding period is minimized, the holding capacity (Cs) is reduced and the aperture ratio is improved without lowering the liquid crystal quality due to flicker or the like, and the display with higher luminance is achieved. Get the equipment. In addition, since the refresh period can be longer, a liquid crystal display device with low power consumption can be obtained.

  Furthermore, the present invention proposes an electroluminescence display device using the above active matrix substrate. Similarly, in an electroluminescence display device, switching control is performed by a plurality of transistors provided for each pixel. However, particularly when expressing low gradation, it is necessary to reduce leakage current, and the method of the present invention is similarly applied. It is valid.

  Furthermore, the present invention proposes an electronic apparatus using the liquid crystal display device or the electroluminescence display device. Electronic devices here include, for example, LCD TVs, LCD monitors, notebook computers, PDAs, digital cameras, video cameras, mobile phones, photo viewers, mobile video players, mobile DVD players, mobile audio players, car navigation systems, in-vehicle TVs, etc. is there. According to this, since it is possible to mount a liquid crystal display device having a higher aperture ratio or low power consumption, there are advantages such as an improvement in display quality over a conventional device and a longer battery driving time. When an electroluminescence display device is used, it has the same merit because it is excellent in gradation expression and has low current consumption.

[Example 1]
FIG. 4 is an enlarged schematic view of the pixel portion in the first embodiment for realizing the active matrix substrate for a liquid crystal display device according to the first, second, third, fourth and fifteenth aspects.

  Compared with the conventional example shown in FIG. 1, the capacitor electrode (212) connected to the scanning line (202) is disposed between the first gate electrode (211a) and the second gate electrode (211b). Is different.

FIG. 5 is a sectional view taken along the line BB ′ of FIG. The portion of the Si island that overlaps with the capacitor electrode (212) is the low-resistance first inter-transistor conductive portion (222a) and is not an intrinsic semiconductor. Accordingly, the capacitor electrode (212) and the first inter-transistor conductive portion (222a) form a capacitor, not a transistor. That is, the first inter-transistor conductive portion (222a) includes a capacitor (C11) with the first gate electrode (211a), a capacitor (C12) with the second gate electrode (211b), and a capacitor electrode (212). And the capacitance (C13) with the scanning line (202) as a capacitance (Cgd ₁ = C11 + C12 + C13). Similarly, the second inter-transistor conductive portion (222b) calculates the sum of the capacitance (C21) with the second gate electrode (211b) and the capacitance (C22) with the third gate electrode (211c) as a scanning line ( 202) (Cgd ₂ = C21 + C22). On the other hand, the pixel electrode connection portion (224) may consider only the capacitance (C31) with the third gate electrode (211c) as the capacitance (Cgd _pix ) with the scanning line (Cgd _pix = C31).

  Strictly speaking, each conductive portion has a capacitance between a farther electrode (for example, the first inter-transistor conductive portion (222a) and the third gate electrode (211c)) or the scanning line (201). However, since the distance is long, it is treated as negligible here.

Here, the equivalent circuit is as shown in FIG. When the transistors at each stage are manufactured symmetrically with the source and drain in the same structure, C11≈C12≈C21≈C22≈C31, so C11 + C12≈C21 + C22≈2 × C31, and clearly Cgd ₁ > Cgd ₂ ≈2 × Cgd _pix . Here, taking the case where the transistors at each stage are n-channel polysilicon thin film transistors as an example, the scanning line signal is different from the conventional example in which Cgd ₁ ≈Cgd _{2 ≈2} × Cgd _pix as shown in FIG. The behavior at the timing when the selection potential (ON) changes to the non-selection potential (OFF) will be described with reference to the timing chart of FIG. In FIG. 6, the solid line is a chart in this embodiment, and the dotted line is a chart in the conventional example.

  In FIG. 6, Vgate is the potential of the scanning line (201), each gate electrode (211a-c), and the capacitance electrode (212), Vvideo is the potential of the data line (202) and the data line junction (223), and V1 is The potential of the first inter-transistor conductive portion (222a), V2 is the potential of the second inter-transistor conductive portion (222b), and Vpixel is the potential of the pixel connecting portion (224) and the pixel electrode (402). Here, as an example, a liquid crystal having a voltage applied to the scanning line (201) of 12 to 0 V, a voltage applied to the data line to write to the pixel of 8 to 2 V, and the counter / capacitance electrode potential (VCOM) is a fixed potential of about 5 V. Assuming the display device, an OFF period in which the scanning line is set to the non-selection potential (= 0V) after the period (P1) in which the scanning line is set to the selection potential (= 12V) and Vvideo = 8V is written to the pixel electrode via the data line. P2), a holding period (P3) for a certain period, and a next line writing period (P4) in which the potential of the data line becomes Vvideo = 2V for writing to the next pixel is assumed.

  In the writing period (P1), Vgate is at a high potential (12V), and the TFT in each stage of the selected pixel is turned on. Since Vvideo is 8V, V1, V2, and Vpixel also approach 8V if a sufficient writing period is taken.

In the scanning line switching period (P2), the scanning line descends with an inclination due to a wiring delay or the like, and finally becomes 0V. At this time, since the source potential of the transistor is initially 8V, the transistor is turned off when Vgate becomes a potential obtained by adding the threshold voltage (Vth) of the TFT to 8V. After turning OFF, the potentials of Vvideo, V1, V2, and Vpixel drop due to capacitive coupling with the scanning lines. In Vvideo, the total capacity of data lines is relatively larger than Vgs × the number of scanning lines and Cgs, and the voltage drop can be almost ignored. If the voltage drop amounts of V1, V2 and Vpixel are ΔV1, ΔV2 and ΔVpixel, respectively, ΔV1 = {Cgd ₁ ÷ (Cgd ₁ + Csd ₁ + Csd ₂ + Cex ₁ )} × (Vth + 8) V, ΔV2 = {Cgd ₂ ÷ (Cgd ₂ + Csd ₂ + Csd ₃ + Cex ₂ )} × (Vth + 8) V, ΔVpixel = {Cgd _pix ÷ (Cgd _pix + Csd ₃ + Cs + Clc)} × (Vth + 8) V.

Actual liquid crystal using a triple-gate (L = 4 + 4 + 4) top-gate thin film transistor having a pixel definition of 150 pixels / inch, a pixel transistor channel width (W) of 4 μm (W = 4), and a channel length (L) of 4 μm. When the above capacitances are calculated using the panel as an example, C11 + C12 = C21 + C22 = Cgd ₂ = 2 × Cgd _pix = 5 fF, Csd ₁ = Csd ₂ = Csd ₃ = 0.3 fF, Cex ₁ = Cex ₂ = 2fF, Cs = 700 fF, Clc = 150 fF are obtained. If the overlapping area of the capacitor electrode (212) and the first transistor-to-transistor conductive portion (222a) is 16 square microns, C13 = 20 fF is obtained. Therefore, if Vth = 3V, ΔV1 = 10.0V in this embodiment, ΔV2 = 7.2V and ΔVpixel = 0.03V are obtained. In a conventional configuration, that is, a configuration in which the capacitor electrode (212) is not present, ΔV1 = ΔV2 = 7.2V and ΔVpixel = 0.03V.

  From the above results, when the scanning line switching period (P2) ends, the gate potential-source potential (Vgs) of the first transistor and the second transistor (205a, b in FIG. 3) is 0- {8. −10.0} = 2V, and the gate potential-source potential (Vgs) of the third transistor (205a, b in FIG. 3) is 0− {8−7.2V} = − 0.8V.

  FIG. 7 is a graph showing a schematic curve (5) of Vgs (gate-source potential) −Ids (drain-source current) when Vds (drain-source potential) of an n-channel thin film transistor is fixed. is there. Since the vertical axis represents the common logarithm, one scale corresponds to a current ratio of 10 times.

  According to FIG. 7, the first transistor and the second transistor (205a, b in FIG. 3) are in the state indicated by point 1 at the boundary between the switching period (P2) and the HOLD period (P3) in FIG. The third transistor (205c in FIG. 3) is in the state indicated by point 2. At this time, Vds (drain-source potential) of the first to third transistors (205a to 205c in FIG. 3) is 10V, 2.8V, and 7.2V, respectively. That is, at this time, the leakage current of the first transistor becomes the largest. Since the data line (202) or the pixel electrode (402) is at a higher potential of about 8V, the potentials of both V1 and V2 increase due to this leakage current during the HOLD period (P3) (= source potential increases). Vgs of the first to third transistors (205a to 205c in FIG. 3) move in the negative direction (direction of arrows (3, 4)). That is, the leakage current of the first transistor and the second transistor (205a, b in FIG. 3) gradually decreases, and conversely, the leakage current of the third transistor increases.

  As a result, the first transistor and the second transistor (205a and b in FIG. 3) relax toward the vicinity of the minimum point (6) of the curve (5) in FIG. Of course, if a sufficiently long period is passed, the leakage current starts to increase further toward the negative after passing the minimum point, but until the next selection period comes if W / L and the screen refresh rate are properly selected The minimum point is not greatly exceeded. For example, if the leakage current near the minimum is 1 pA and the refresh rate is 60 Hz (17 ms), the total capacitance of the first transistor-to-transistor conductive portion (222a) is 27.6 fF, so the voltage rise is calculated to be 0.6V. It does not move from near the minimum point (6), and hardly moves from around V1 ′ (≈0 V) with the initial fluctuation, as indicated by V1 in FIG. Considering a general condition for preventing movement of 1 V or more from the vicinity of the minimum point (6), the maximum difference between the video signal potential applied to the data line and the non-selection potential of the scanning line is expressed as the drain-source of the transistor. When the potential between electrodes (Vds) is used (for example, Vds = 8-0 = 8V in the present embodiment), the gate-source potential (vgs) is varied, and the minimum current value is expressed as Imin. When the interval for selecting one scanning line (display refresh period) is TR, it is sufficient that the inter-transistor conductive portion has a capacitance of Imin × TR or more, and the capacitance may be formed based on this.

  Next, it is assumed that the potential of Vvideo is inverted in the next line writing period (P4) and becomes 2 V, which is the lowest potential of the video signal. In this case, the source potentials of the first and second transistors (205a and b in FIG. 3) remain V1 ′ (≈0V), and Vgs of the first transistor (205a in FIG. 3) remains approximately 0V. , Vds decreases from about 8V to about 2V while being positive, the leakage current decreases with the same polarity, and the leakage currents of the second and third transistors (205b and c in FIG. 3) are almost the same. Absent. Therefore, V1 shows a very gradual increase as shown by the solid line in FIG. 6, and the potential hardly changes during the refresh period of about 60 Hz. In other words, Vpixel continues to decrease very gently during the holding period, but its fluctuation is small and constant regardless of the signal (Vvideo) waveform of the data line.

In the conventional configuration, that is, the configuration in which the capacitive electrode (212) does not exist, V1 and V2 show substantially the same curve as shown by the dotted line in FIG. That is, as shown by the point 2 in FIG. 7, the gate is reversely biased from the beginning, and the leakage current increases with time. As a result, V1 and V2 rise so as to approach Vpixel relatively quickly, and on the contrary, Vpixel falls slightly due to leakage current. In the next line writing period (P4), when the potential of Vvideo is inverted to 2V, the source potential of the first transistor is Vvideo (= 2V), so Vgs = -2V, which is a minimum point as shown by point 7 in FIG. A leakage current several times larger than that in the vicinity (6) occurs, and the capacitance (= Cgd ₁ + Csd ₁ + Csd ₂ + Cex ₁ ) of the first inter-transistor conductive portion (222a) is smaller than that of the present embodiment, so that the dotted line in FIG. As shown in FIG. 5, V1 rapidly decreases and approaches Vvideo (= 2V). As a result, the same phenomenon occurs with a slight delay time in the second transistor and the third transistor, and Vpixel is reduced by the leakage current from the data line.

  As described above, the active matrix substrate of this embodiment has less fluctuation due to the leakage current to the data line of the pixel electrode potential than the conventional method. Moreover, the fluctuation range of the pixel electrode potential is constant regardless of the signal waveform of the data line. Furthermore, since the capacitance of the first transistor-to-transistor conductive part near the data line is made larger than the capacity of the second transistor-to-transistor conductive part near the pixel electrode, most of the increase in feedthrough is released to the data line, There is little influence on the pixel electrode. Further, since the source potential of the transistor always becomes the potential of the conductive portion between the transistors, the feedthrough amount is also stabilized. Furthermore, since the holding capacity can be reduced, the aperture ratio is also improved.

  In addition, by using a polysilicon thin film for the transistor, the reverse bias leakage current, which is a weak point of the polysilicon thin film transistor, is suppressed to a minimum while making the transistor size much smaller than when using an amorphous silicon thin film, for example. .

  FIG. 8 is a perspective configuration view (partially sectional view) of a transmission type liquid crystal display device showing a first embodiment for realizing the liquid crystal display device according to claim 16. An active matrix substrate (101) and a counter substrate (901) on which a common electrode is formed by depositing ITO on a color filter substrate are bonded together by a sealing material (920), and a nematic liquid crystal material (910) is put therein. Is enclosed. Although not shown, an alignment material made of polyimide or the like is applied to the surfaces of the active matrix substrate (101) and the counter substrate (901) that are in contact with the liquid crystal material (910) and rubbed in directions orthogonal to each other. In addition, a conductive material is disposed on the opposing conductive portion on the active matrix substrate (101) and is short-circuited with the common electrode of the counter substrate (901) to be given the same potential (VCOM).

  Various signal / power supply terminals on the active matrix substrate (101) are connected to one or more external ICs (940) on the circuit board (935) through the mounted FPC (930), and necessary electric signals / potentials are supplied. Supplied.

  Furthermore, an upper deflection plate (951) is arranged outside the counter substrate (901), and a lower deflection plate (952) is arranged outside the active matrix substrate (101) so that their polarization directions are orthogonal to each other (crossed Nicols) ). Further, a backlight unit (960) is attached under the lower deflection plate (952) to complete. The backlight unit (960) may be a cold cathode tube with a light guide plate or a scattering plate attached thereto, or a unit that emits light by an EL element. Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached on the upper deflection plate, or an optical compensation film may be attached to improve the viewing angle. good.

  When the active matrix substrate of the present embodiment is used in such a liquid crystal display device, the potential fluctuation of the pixel electrode is small and stable, and therefore a phenomenon such as flicker and vertical crosstalk is caused by the conventional liquid crystal display device using the active matrix substrate. Since the aperture ratio is high, the surface brightness can be increased even when the same backlight is used, so that the display quality can be improved. Alternatively, the current consumption of the backlight can be reduced even with the same luminance. Further, since the leakage current is small, the display refresh period can be longer than that of the conventional liquid crystal display device, and in this case, the power consumption can be further reduced. If this is used in an electronic device, a display with higher display quality can be mounted and the current consumption of the backlight can be reduced, so that the battery driving time can be extended in the portable electronic device.

In this embodiment, the pixel transistor is an n-channel transistor. However, when a p-channel transistor is used, the potential change direction of the scanning line is reversed and the capacitive coupling variation polarity is similarly reversed. But the effect is similar. In addition, the self-alignment structure in which the gate electrode and the channel portion of the pixel transistor have the same width has been described, but part or all of each stage transistor has an offset structure in which the width of the intrinsic semiconductor is larger than the width of the gate electrode, or An LDD (Lightly Doped Drain) structure in which a low concentration region is provided between the channel portion and the source / drain electrodes may be employed. When these structures are adopted, the leakage current can be further reduced.
[Example 2]

  FIG. 9 is an enlarged schematic view of the pixel portion in the second embodiment for realizing the active matrix substrate according to claims 1, 2, 4, 10, 11 and 15. Although it is the same as that of the first embodiment that the capacitor electrode (212) is provided to reduce the leakage current, a p-channel type charging transistor (206) is further provided. FIG. 10 is an equivalent circuit diagram in which the gate terminal and the source terminal of the charging transistor (206) are connected to the scanning line (202). According to such a configuration, when the scanning line (202) is at a high potential (when the scanning line is selected), the charging thin film transistor (206) is turned off, so that the potential writing to the pixel electrode is not affected. On the other hand, when the scanning line (202) is at a low potential (when the scanning line is not selected), the charging transistor is turned on, and the first inter-transistor conductive portion approaches the scanning line non-selected potential + the transistor threshold value. .

  Thus, the first inter-transistor conductive portion is always close to the scanning line potential during the holding period, and becomes V1≈0V−Vth (the threshold voltage of the charging transistor). Therefore, when the refresh rate is long or the leakage current of the transistor is large, the leakage current can be reduced more reliably by adopting the configuration of this embodiment.

  In this embodiment, the pixel transistor is an n-channel type. However, when the pixel transistor is a p-channel type, the charging transistor (206) may be an n-channel type.

FIG. 11 is an equivalent circuit diagram showing a modification of the second embodiment for realizing the active matrix substrate according to claims 1, 2, 4, 14 and 15. A charging resistor (207) is provided instead of the charging transistor (206). In this case, the charging resistance (207) is between the on-resistance (channel resistance when Vgs> Vth) and the off-resistance (channel resistance when Vgs <Vth) of the first transistor (205a) (about 10M to 10GΩ). The same effect can be obtained by setting to (appropriate).
[Example 3]

  12 is a cross-sectional view taken along the line A-A 'in FIG. 1, showing a third embodiment for realizing the active matrix substrate according to claims 1, 2, 6 and 15. In FIG.

  In this embodiment, the first low-concentration implantation region (225a) is provided between the data line junction (223) and the first channel portion (221a), and the second inter-transistor conduction portion (222b) is connected to the third channel portion (221a). A second low concentration implantation region (225b) is provided between the channel portions (221c), and a third low concentration implantation region (225c) is provided between the third channel portions (221c) and the pixel electrode junction portion (224). Each is provided. The first to third low-concentration implantation regions (225a, b, c) are between the data line junction (223), the pixel electrode junction (224), the first inter-transistor conductive portion (222a), and the second transistor. A lower amount of ions are implanted than in the conductive portion (222b), and this region exhibits higher resistance.

Since the capacitance between the source / drain region and the gate electrode when the low concentration implantation region is sandwiched is smaller than when the region is not sandwiched, Cgd ₁ > Cgd ₂ > Cgd _pix × 2. Therefore, as described in the first embodiment, the leak current of the pixel electrode can be reduced. Furthermore, by sandwiching a low-concentration region having high resistance between the data line and the first channel portion, and the pixel electrode and the second channel portion, the concentration of the electric field at the drain end is alleviated and an LDD structure transistor that reduces leakage current is obtained. Can also be expected.

FIG. 13 is a cross-sectional view taken along the line AA ′ of FIG. 1 showing a modification of the third embodiment for realizing the active matrix substrate according to claims 1, 2, 6, 7, and 15. In this modification, a first low concentration implantation region (225a) is provided between the data line junction (223) and the first channel portion (221a), and the first channel portion (221a) and the first transistor are connected. A second low-concentration implantation region (225b) is provided between the conduction portions (222a), and a third low-concentration implantation region (225b) is provided between the second inter-transistor conduction portion (222b) and the third channel portion (221c). 225c), a fourth low-concentration implantation region (225d) is provided between the third channel portion (221c) and the pixel electrode junction portion (224), respectively, and the second channel portion (221b) is provided as the second channel portion (221b). A GOD (Gate Overlapped Drain) structure in which the width is narrower than the gate electrode (211b) and the center position is offset from the third transistor is adopted. With such a configuration, Cgd1>Cgd2> Cgdpix × 2 is obtained, and the same effect can be expected. The same effect can be obtained even if the second transistor has a GOLDD (Gate Overlapped Lightly Doped Drain) structure in which the low concentration implantation region and the gate electrode are overlapped instead of the inter-transistor conductive portion.
[Example 4]

  FIG. 14 is an enlarged schematic view of the pixel portion in the fourth embodiment for realizing the active matrix substrate according to the first, second, eighth, ninth and fifteenth aspects.

  In this embodiment, the channel width of the first transistor> the channel width of the second transistor> the channel width of the third transistor is employed.

Since the capacitance between the gate electrode and the drain portion is roughly proportional to the channel width, such a configuration results in Cgd ₁ > Cgd ₂ > Cgd _pix × 2, which is the same effect as in the first to third embodiments. I can expect.

  The present invention is not limited to the above-described embodiment, and may be an active matrix substrate using a thin film transistor having a bottom gate structure instead of a top gate structure or an amorphous silicon thin film transistor instead of a polysilicon thin film transistor. Absent. Further, the liquid crystal display device may be a reflection type or a semi-transmission type instead of the transmission type as in the embodiment, or may be a projection light valve instead of the direct view type. Further, a display device using an electroluminescence element instead of the liquid crystal element may be used.

The pixel part expansion schematic diagram for demonstrating the active matrix substrate which used the conventional multigate structure transistor for the pixel switching element. FIG. 2 is a cross-sectional view taken along A-A ′ of FIG. 1. The pixel part equivalent circuit schematic which used the conventional multigate structure transistor for the switching element. The pixel part expansion schematic diagram for demonstrating a 1st Example. Sectional drawing along FIG. 4B-B '. The timing chart for demonstrating the operation | movement of a 1st Example. 6 is a graph showing an example of Ids-Vgs characteristics of an n-channel thin film transistor. The liquid crystal display device module perspective view (partially transparent) for demonstrating a 1st Example. The pixel part expansion schematic diagram for demonstrating a 2nd Example. The pixel part equivalent circuit schematic for demonstrating a 2nd Example. The pixel part equivalent circuit diagram for demonstrating the modification of a 2nd Example. Sectional drawing of the location corresponded to FIG. 1A-A 'for demonstrating a 3rd Example. Sectional drawing of the location corresponded to FIG. 1A-A 'for demonstrating the modification of a 3rd Example. The pixel part expansion schematic diagram for demonstrating a 4th Example.

Explanation of symbols

101: active matrix substrate 201: scanning line 202: data line 203: capacitance line 205a: first transistor 205b: second transistor 205c: third transistor 206: charging transistor 207: charging resistor 211a: first Gate electrode 211b: second gate electrode 211c: third gate electrode 212: capacitor electrode 221a: first channel portion 221b: second channel portion 221c: third channel portion 222a: first inter-transistor conductive portion 222b: second inter-transistor conductive portion 223: data line junction 224: pixel electrode junction 225a: first low concentration implantation region 225b: second low concentration implantation region 225c: third low concentration implantation region 225d: Fourth low concentration implantation region 402: pixel electrode Vgate: scanning line and Over gate electrode potential Vvideo: data line potential V1: first transistor Mashirube conductive portion potential V2: second transistor Mashirube conductive portion potential Vpixel: pixel electrode potential

Claims (18)

An active matrix substrate in which a plurality of scanning lines, a plurality of data lines, a plurality of pixel electrodes, and a plurality of pixel switching elements are arranged on the substrate;
Each of the plurality of pixel switching elements is an n-stage multi-gate transistor in which first to n-th (n ≧ 2) transistors are connected in series, and the gate electrodes of the first to n-th transistors are the same in the scanning. Each connected to one of the lines,
One of the source and drain electrodes of the m-th (1 ≦ m ≦ n−1) transistor constituting the multi-gate transistor is one of the source and drain electrodes of the m + 1-th transistor via the m-th transistor-to-transistor conductive portion. Connected to the
One of the source and drain electrodes of the first transistor constituting the multi-gate transistor is connected to one of the plurality of data lines, and one of the source and drain electrodes of the nth transistor is the plurality of pixel electrodes. Connected to one of the
The capacitance between the m-th (1 ≦ m ≦ n−1) inter-transistor conductive portion and the gate electrode is denoted as Cgd _m, and the capacitance between the pixel electrode and the gate electrode of the n-th transistor is denoted as Cgd _pix. An active matrix substrate characterized in that at least one of Cgd _{1 to n-1} is larger than twice Cgd _pix . 2. The active matrix substrate according to claim 1, wherein the n is 3 or more, and the Cgd ₁ is larger than twice the Cgd _pix and larger than Cgd _n−1 . A maximum potential difference between a non-selection potential applied to the scanning line and a video signal applied to the plurality of data lines when the plurality of pixel switching elements connected to the scanning line have a relatively high impedance. Where Vmax is Vmax, and the potential applied to each gate electrode by applying the potential of Vmax between each drain electrode and each source electrode of the first to n-th transistors (= Vg) as a parameter. current flowing between the electrode and the source electrode were respectively _{I 1 (Vg) ~I n (} Vg), wherein when obtained by sweeping the potential (Vg) applied to the gate electrode _{I 1 (Vg) ~I n (} Vg) the minimum value indicated by the Imin ₁ ~Imin _n, when the interval for selecting one of the scan lines (refresh period) was TR, the _Cgd m (1 ≦ m ≦ n At least one active matrix substrate according to 2 claim 1 characterized in that greater than _{(Imin m + Imin m + 1} ) × TR 1).   4. The active matrix substrate according to claim 1, wherein at least a part of the first inter-transistor conductive portion overlaps with an electrode connected to the scanning line via an insulating film to form a capacitor.   The source / drain side connected to the pixel electrode of the n-th transistor has an offset structure having an intrinsic semiconductor having an offset length L that does not overlap with the gate electrode, and the first to n-1th transistors have the offset structure. 2. At least one of the source / drain sides connected to the n-1 transistor-to-transistor conductive portion has no offset structure or has an offset structure with an offset length shorter than L. 5. An active matrix substrate according to 4.   The source / drain side connected to the pixel electrode of the n-th transistor has an LDD (Lightly Doped Drain) structure having a low-injection high-resistance region of LDD length L that does not overlap the gate electrode. At least one of the source and drain sides connected to the first to (n-1) -th transistor conductive portions of one transistor does not have an LDD structure, or has an LDD structure having an LDD length shorter than L. The active matrix substrate according to claim 1, wherein:   At least one of the first to n−1 transistors has a gate electrode and a low concentration or high concentration implantation on a source / drain side connected to one of the first to n−1 inter-transistor conductive portions. It has a GOLDD (Gate Overlapped Doped Drain) structure or a GOD (Gate Overlapped Drain) structure in which layers are overlapped, and the source / drain side connected to the pixel electrode of the nth transistor has a GOLDD structure or GOD structure. The active matrix substrate according to claim 1, wherein:   8. The active matrix substrate according to claim 1, wherein a channel width of the first transistor is larger than a channel width of the second to n-th transistors.   9. The active matrix substrate according to claim 1, wherein a channel width of the nth transistor is smaller than a channel width of the first to (n-1) th transistors.   The first to n-th transistors are n-channel transistors, and the first inter-transistor conductive portion is in the pixel electrode potential holding period in which the first to n-th transistors have a relatively high impedance. 10. The active matrix substrate according to claim 1, wherein a potential lower than any of the data line to which the first transistor is connected and the pixel electrode to which the nth transistor is connected is applied. .   A drain electrode of a charging transistor made of a p-channel thin film transistor is connected to the first transistor conductive portion, and a source electrode and a gate electrode of the charging transistor are connected to a gate electrode of the first transistor, respectively. The active matrix substrate according to claim 10, wherein the active matrix substrate is connected to one of the plurality of scanning lines.   The first to n-th transistors are p-channel transistors, and the first inter-transistor conductive portion is in the pixel electrode potential holding period in which the first to n-th transistors have a relatively high impedance. 10. The active matrix substrate according to claim 1, wherein a potential higher than any of the data line to which the first transistor is connected and the pixel electrode to which the n-th transistor is connected is applied. .   A drain electrode of a charging transistor made of an n-channel thin film transistor is connected to the first transistor conductive portion, and a source electrode and a gate electrode of the charging transistor are connected to a gate electrode of the first transistor, respectively. 13. The active matrix substrate according to claim 12, wherein the active matrix substrate is connected to one of the plurality of scanning lines that are the same as the plurality of scanning lines.   Both ends of a charging resistor are connected to the scanning line to which the first transistor conductive portion and the gate electrode of the first transistor are connected, and the resistance of the charging resistor is turned on by the first transistor. 14. The active matrix substrate according to claim 1, wherein the active matrix substrate is higher than a resistance when the first transistor is turned off and lower than a resistance when the first transistor is turned off.   15. The active matrix substrate according to claim 1, wherein the first to nth transistors are thin film transistors using polysilicon.   16. A display device comprising a liquid crystal element held by the active matrix substrate according to claim 1 and a substrate opposed thereto.   A display device comprising an electroluminescent material disposed on the active matrix substrate according to claim 1. An electronic device using the display device according to claim 16.

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