JP2005088495A - Storage device that can read and write in multiple modes - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for automatically switching a communication control mode according to a received signal received from an external device in a storage device capable of switching a communication control mode.
The present invention is a storage device capable of switching a communication control mode in communication with an external device. Here, the communication control mode includes a high-speed control mode for performing high-speed data writing to a non-volatile memory capable of relatively high-speed data writing, and a relatively low-speed data writing. And a low-speed control mode for performing low-speed data writing to the nonvolatile memory. The storage device includes a non-volatile memory that can be written in either a high-speed control mode or a low-speed control mode, a communication control unit that automatically switches a communication control mode in accordance with a received signal received from an external device, It is characterized by providing.
[Selection] Figure 6

Description

  The present invention relates to memory read and write control.

  Ink cartridges that are consumables for inkjet printers are equipped with a non-volatile memory that stores the remaining amount of consumables and other attribute information. Conventionally, there is only a non-volatile memory such as an EEPROM (ELECTRONICLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY) that requires several hundred times longer than a DRAM.

  However, in recent years, flash memories that require an erasing process but have a high writing speed have been put into practical use, and high-speed non-volatile memories that can be written at a high speed at the same speed as an SRAM such as MRAM (Magnetoretic RAM) and FeRAM (Ferroelectric RAM). Is also moving toward practical use.

Japanese Patent Publication No. 2002-14870

  However, since the read / write method corresponding to the high-speed nonvolatile memory is generally different from the read / write method compatible with the conventional nonvolatile memory, the same ink is used in the transition period from the conventional nonvolatile memory to the high-speed nonvolatile memory. However, there arises a problem that a plurality of types of ink cartridges having different communication modes must be prepared. Furthermore, this problem is not limited to the ink cartridge, and may be a problem that can occur in general in a consumable container that contains toner and other consumables.

  The present invention has been made to solve the above-described problems in the prior art, and in a storage device capable of switching the communication control mode, the communication control mode is automatically set according to the received signal received from the external device. It aims at providing the technology for switching.

The present invention is a storage device capable of switching the communication control mode in communication with an external device,
The communication control mode includes a high-speed control mode for performing high-speed data writing to a non-volatile memory capable of writing data at a relatively high speed, and a non-volatile memory capable of writing data at a relatively low speed. Including a low-speed control mode for performing low-speed data writing,
The storage device
A non-volatile memory capable of writing in any of the high-speed control mode and the low-speed control mode;
In accordance with a received signal received from the external device, a communication control unit that automatically switches the communication control mode,
It is characterized by providing.

  In the storage device of the present invention, the communication control mode is automatically switched according to the received signal received from the external device, so that data can be read and written regardless of whether the external device performs communication in the high speed control mode or the low speed control mode. It can be carried out.

In the storage device, the reception signal includes a clock signal received in synchronization with data to be written to the storage device,
The communication control unit may perform the switching based on a length of a specific pulse included in the clock signal.

  Since the length of the pulse of the clock signal synchronized with the data to be written to the storage device varies depending on the time required for writing to the nonvolatile memory, the communication mode of the received signal is determined according to this variation. Then, the communication mode can be automatically switched only by applying the present invention to the storage device side.

In the storage device, the storage device is connected to a clock signal line, a data signal line, and a reset signal line,
The clock signal line is a wiring for receiving the clock signal;
The data signal line is a wiring for transmitting and receiving the data,
The reset signal line is a wiring for receiving a reset signal for initializing the storage device,
The specific pulse may be a pulse received a predetermined number after receiving the reset signal.

  Note that a connection method between the storage device and the clock signal line and other signal characteristics may be a bus connection or a discrete connection.

  In the storage device, the high-speed control mode is a mode in which the high-speed writing is performed in the specific area after erasing data stored in the specific area to be written to the nonvolatile memory in a batch. You may do it.

  As described above, if the erasing process is collectively performed on the entire specific area to be written to the nonvolatile memory, the erasing process speed can be increased.

  The present invention is embodied in a carrier wave including a storage device, a communication device, a computer program for causing a computer to realize the functions of the method or device, a recording medium storing the computer program, and the computer program. It can be realized in various forms such as a consumable container equipped with a data signal and a storage device.

A. Device configuration:
FIG. 1 is an explanatory diagram showing a configuration example of a storage system including a plurality of storage devices and a host computer in an embodiment of the present invention. This storage system includes a host computer 10 and a memory module substrate 200 having five storage devices 20, 21, 22, 23, 24.

  The host computer 10 and the memory module substrate 200 are connected by a power supply line VDL, a clock signal line CL, a data signal line DL, a reset signal line RL, and a cartridge out signal line COL. These wires can be implemented, for example, as a flexible feed cable (FFC).

  The power supply line VDL is connected to each of the five storage devices 20, 21, 22, 23, 24. The clock signal line CL, the data signal line DL, and the reset signal line RL are connected to each of the five storage devices 20, 21, 22, 23, and 24 via the clock bus CB, the data bus DB, and the reset bus RB, respectively. Bus connected. The cartridge-out signal line COL is grounded via five storage devices 20, 21, 22, 23, 24 connected in series.

  The power supply line VDL is a line for supplying power from the host computer 10 to each storage device 20, 21, 22, 23, 24. The clock signal line CL and the reset signal line RL are lines for transmitting the clock signal SCK and the reset signal RST from the host computer 10 to the storage devices 20, 21, 22, 23, and 24, respectively. The data signal line DL is a line for exchanging data and commands between the host computer 10 and the storage devices 20, 21, 22, 23, and 24. The cartridge out signal line COL is a line for the host computer 10 to receive the cartridge out signal CO.

  FIG. 2 is a block diagram showing an internal circuit configuration of the storage device 20 according to the embodiment of the present invention. The storage device 20 includes a memory array 201, an ID comparator 203, an I / O controller 205, an operation code decoder 204, and an address counter 202. The storage device 20 is connected to the power supply line VDL via the power supply positive terminal VDDM, and is connected to the clock bus CB and the data bus via the clock signal terminal CT, the data signal terminal DT, and the reset signal terminal RT, respectively. The bus is connected to the DB and the reset bus RB. Note that the storage devices 21, 22, 23, and 24 have the same configuration as the storage device 20.

  The address counter 202 is a circuit that increments the counter value in synchronization with the clock signal SCK. The counter value is associated with the storage area position (address) of the memory array 201. Thus, in this embodiment, the write position and read position in the memory array 201 are specified sequentially.

  In this embodiment, the memory array 201 has a 256-bit storage area as shown in FIG. This storage area is divided into a storage area for storing identification data (3 bits from the top), a blank area (4th bit from the top), and a data storage area (from the 5th bit onward). The data storage area stores ink consumption and other information. This storage area is configured to correspond to a data field (FIG. 3B) received by the storage device from the host computer 10 that is read and written sequentially. The memory array 201 is a flash memory or other high-speed nonvolatile memory.

  A data field (FIG. 3B) received by the storage device from the host computer 10 includes an identification data transmission field (3 bits from the top), a write / read command transmission field (the 4th bit from the top), and , And a data transmission field (after the 5th bit from the top). The signal communication control mode by the host computer 10 includes a low-speed communication control mode assuming that the memory array 201 is an EEPROM or other low-speed nonvolatile memory, and a high-speed assumed to be a flash memory or other high-speed nonvolatile memory. There is a communication control mode.

  The ID comparator 203 determines whether or not the identification data included in the data string input from the host computer 10 via the data signal terminal DT matches the identification data stored in the memory array 201. If the two identification data match, the ID comparator 203 transmits an access permission signal EN to the operation code decoder 204.

  When the operation code decoder 204 receives the access permission signal EN, the operation code decoder 204 transmits a write processing request or a read processing request to the I / O controller 205 in accordance with the acquired write / read command.

  The I / O controller 205 switches and controls the data transfer direction with respect to the memory array 201 in accordance with a request from the operation code decoder 204. The I / O controller 205 further includes a buffer memory (not shown) that temporarily stores data to be transferred. The I / O controller 205 further has an internal clock 305.

  The internal clock 305 is simply configured as a ring oscillator. The ring oscillator is a clock circuit using element delay of a transistor, and is configured by combining an odd number of inverter circuits (inversion circuits).

  The I / O controller 205 can determine whether the communication control method used by the host computer 10 is for a low-speed nonvolatile memory or a high-speed nonvolatile memory in accordance with a signal received from the host computer 10. . The determination method will be described later. The I / O controller 205 functions as a “communication control unit” in the claims.

B. Contents of processing performed by the storage device:
FIG. 4 is a flowchart showing the contents of processing performed by each storage device 20, 21, 22, 23, 24 in the embodiment of the present invention. Each of the storage devices 20, 21, 22, 23, 24 passively performs the following processing in response to a signal from the host computer 10.

  In step S100, the address counter 202 (FIG. 2) of each storage device 20, 21, 22, 23, 24 returns the counter value to the initial value. This process is performed in response to reception of the reset signal RST from the host computer 10. As a result, each of the storage devices 20, 21, 22, 23, and 24 is ready to receive data from the host computer 10 and process the data.

  In step S200, the ID comparator 203 of each storage device 20, 21, 22, 23, 24 has 3 bits from the head of the data received from the host computer 10 (identification data transmission field (FIG. 3B)). The identification data contained in is read. Reading control is performed by the I / O controller 205.

  In step S300, the ID comparator 203 of each storage device 20, 21, 22, 23, 24 is stored in the storage area (FIG. 3A) for storing the received identification data and the identification data of the memory array 201. It is determined whether or not the identification data matches. As a result of this determination, the storage device whose ID does not match among the storage devices 20, 21, 22, 23, 24 is completed, and waits until a new reset signal RST is received.

  On the other hand, for the storage devices with the matching IDs, the ID comparator 203 transmits an access permission signal EN to the operation code decoder 204, thereby enabling read / write processing. By such processing, the host computer 10 can designate a storage device to be read / written. In the present specification, the description will be made assuming that the IDs of the storage devices 20 match.

  In step S400, the operation code decoder 204 performs a data write process to the memory array 201 and a data read process from the memory array 201 in accordance with the command of the fourth bit from the top (write / read command transmission field). Proceed to one of the processes.

  When the received command is a read command, the operation code decoder 204 of the storage device 20 requests the I / O controller 205 for a data transfer direction in which data can be read from the memory 201 and transferred to the host computer 10. In response to this, reading of data from the memory 201 is started (step S600).

  When the received command is a read command, the operation code decoder 204 of the storage device 20 requests the I / O controller 205 for a data transfer direction in which the data received from the host computer 10 can be transferred to the memory 201. In response to this, data writing to the memory 201 is started (step S500).

  FIG. 5 is a flowchart showing the contents of the writing process performed by the storage device 20 designated by the host computer 10. There are two writing processes, a low-speed compatible mode and a high-speed mode. The low-speed compatible mode is a processing mode that can be used both when the memory 201 is an EEPROM or other low-speed nonvolatile memory with a low writing speed and when it is a flash memory or other high-speed nonvolatile memory. On the other hand, the high-speed mode is a processing mode that can be used only when the memory 201 is a flash memory or other high-speed memory.

  FIG. 6 is a timing chart showing a temporal relationship between the reset signal RST, the clock signal SCK, and the data signal CDA in the low-speed compatibility mode. The clocks C1 to C6 are the first to sixth clock pulses after the reset signal RST goes high.

  The data signal CDA is transmitted from the host computer 10 in synchronization with this clock pulse. For example, 3 bits of identification data are transmitted in synchronization with clocks C1, C2, and C3. On the other hand, the storage device 20 receives a data signal using the rising edges and falling edges of the clocks C1, C2, and C3 as control signals.

  In step 510, the I / O controller 205 measures the time from the rising edge of the clock C5, which is the fifth pulse received after receiving the reset signal. This measurement is performed based on the clock signal output from the internal clock 305 (FIG. 2). The clock C5 corresponds to a “specific pulse” in the claims.

  In step 520, the I / O controller 205 determines whether the time from the rising edge has exceeded 2 μS. When the time from the rising edge exceeds 2 μS, the I / O controller 205 determines that the host computer 10 is communicating in the low-speed communication control mode. In response to this determination, the I / O controller 205 switches the write processing mode to the low speed compatible mode corresponding to the low speed communication control mode. The default mode is the high speed mode.

  In step 530, the I / O controller 205 performs a writing process in the low-speed compatibility mode. In the low-speed compatible mode, the I / O controller 205 performs “erase processing” and “recording processing” over a time of 2500 μS for each bit. These processes are processes performed by the host computer 10 on the assumption that the storage device 20 includes a low-speed nonvolatile memory, but can be applied to a high-speed nonvolatile memory as it is.

  On the other hand, if the falling edge is detected before the time from the rising edge exceeds 2 μS, the I / O controller 205 determines that the host computer 10 is communicating in the high-speed communication control mode. In response to this determination, the I / O controller 205 performs a writing process in a high speed mode corresponding to the high speed communication control mode set as a default (step 540). The reason why the high speed mode is set as a default is to avoid a control delay associated with the process switching in the high speed mode in which the processing time is critical.

  FIG. 7 is a flowchart showing the contents of the high-speed mode performed by the storage device 20 designated by the host computer 10. 8 and 9 are timing charts showing temporal relationships of the reset signal RST, the clock signal SCK, and the data signal CDA in the erase process and the write process in the high-speed mode, respectively.

  The high-speed mode is performed by writing data to the memory array 201 at high speed after erasing the contents of the memory array 201 at once. As described above, the “erase” and “write” processes are separated from each other because the “erase” process is performed on the entire storage area to be written in the memory array 201 in a batch. This is to speed up the process. The storage area to be written may include not only a data storage area but also an area for storing information such as an ID and a command.

  In step 541, the I / O controller 205 buffers the signal from the host computer 10 for 8 bits in synchronization with the clocks C5 to C12. In this embodiment, data is transferred every 8 bits.

  In step 542, the I / O controller 205 determines whether the signal from the host computer 10 instructs “erase” or “data write” based on the first buffered 8-bit data. . Specifically, for example, when all the 8-bit data is “1”, it can be determined that it is an “erase instruction”. In response to this determination, the I / O controller 205 erases the contents of the memory array 201 all at once (step S523) and waits for the next rise of the reset signal RST.

  In step 544, the I / O controller 205 writes data in the high speed mode. This data writing is performed at high speed by repeating the writing to the buffer to the I / O controller 205 and the memory array 201 and every 8 bits.

  As described above, the storage device 20 according to the present embodiment switches the communication control mode based on the length of the specific pulse included in the clock signal synchronized with the data, so that the host computer 10 is not changed. Automatic switching of communication mode is possible. As a result, particularly in the period when high-speed non-volatile memories are popularized, even when high-speed non-volatile memories and low-speed non-volatile memories are mixed, it is possible to ensure the homogeneity and realize the smooth popularization of high-speed non-volatile memories. . In the present embodiment, the high speed mode and the low speed compatible mode correspond to the “high speed control mode” and the “low speed control mode” in the claims, respectively.

C. Variation:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

C-1. In the above-described embodiment, the storage device has an internal clock, but may be configured such that a separate clock signal is supplied from the outside.

C-2. In the above-described embodiment, the erasing and writing processes are separated in the high-speed mode, but erasing and writing may be performed sequentially as in the low-speed compatibility mode.

C-3. In the above-described embodiment, the communication control mode is determined based on the pulse length of a specific clock. For example, a specific circuit (for determining the communication mode is provided to a host computer that is an external device of the storage device). For example, an RC circuit or a jumper may be provided. Further, when the erase and write processes are separated as in the above-described embodiment, the communication control mode may be switched according to whether or not the “erase command” has been received.

  In general, the communication control unit used in the present invention only needs to be configured so that the communication control mode can be automatically switched in accordance with a received signal received from an external device.

C-4. In the above-described embodiment, in the high-speed mode, either “erase” or “data write” is determined based on the contents of the first buffered data. For example, the pulse length of a specific clock is determined. It may be determined based on this.

C-5. In the above-described embodiment, the memory array 201 is a flash memory or other memory that needs to be erased, but may be a memory that can be overwritten, such as MRAM or FeRAM, and does not need to be erased. However, in this case, the I / O controller 205 is preferably configured to invalidate, for example, a command that requires erasure processing.

C-6. In the above-described embodiment, the available communication control modes include a low-speed compatible mode that assumes that the memory array 201 is an EEPROM or other low-speed nonvolatile memory, and a high-speed that is assumed to be a flash memory or other high-speed nonvolatile memory. Mode, there may be a third communication control mode assuming that the memory array 201 is an overwritable memory such as RAM or FeRAM.

  In the present invention, in general, the communication control mode includes a high-speed control mode for performing high-speed data writing to a non-volatile memory capable of relatively high-speed data writing, and a relatively low-speed data writing. The number of communication control modes is not limited as long as it is configured to include a low-speed control mode for performing low-speed data writing to a possible non-volatile memory.

  When some or all of the functions of the present invention are realized by software, the software (computer program) can be provided in a form stored in a computer-readable recording medium. In the present invention, the “computer-readable recording medium” is not limited to a portable recording medium such as a flexible disk or a CD-ROM, but an internal storage device in a computer such as various RAMs and ROMs, a hard disk, and the like. An external storage device fixed to the computer is also included.

FIG. 3 is an explanatory diagram illustrating a configuration example of a storage system including a plurality of storage devices and a host computer according to an embodiment of the present invention. The block diagram which shows the internal circuit structure of the memory | storage device 20 in the Example of this invention. A data field received by the storage device from the host computer 10. The flowchart which shows the content of the process which each memory | storage device 20, 21, 22, 23, 24 performs in the Example of this invention. 5 is a flowchart showing the contents of a write process performed by the storage device 20 designated by the host computer 10. 4 is a timing chart showing a temporal relationship among a reset signal RST, a clock signal SCK, and a data signal CDA in a low-speed compatible mode. 4 is a flowchart showing the contents of a high-speed mode performed by the storage device 20 designated by the host computer 10. 4 is a timing chart showing a temporal relationship among a reset signal RST, a clock signal SCK, and a data signal CDA in an erasing process in a high speed mode. 5 is a timing chart showing a temporal relationship among a reset signal RST, a clock signal SCK, and a data signal CDA in a writing process in a high-speed mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Host computer 20, 21, 22, 23, 24 ... Storage device 200 ... Memory module board 201 ... Memory array 202 ... Address counter 203 ... ID comparator 204 ... Operation code decoder 205 ... I / O controller 305 ... Internal clock

Claims (8)

A storage device capable of switching the communication control mode in communication with an external device,
The communication control mode includes a high-speed control mode for performing high-speed data writing to a non-volatile memory capable of writing data at a relatively high speed, and a non-volatile memory capable of writing data at a relatively low speed. Including a low-speed control mode for performing low-speed data writing,
The storage device
A non-volatile memory capable of writing in any of the high-speed control mode and the low-speed control mode;
In accordance with a received signal received from the external device, a communication control unit that automatically switches the communication control mode,
A storage device comprising: The storage device according to claim 1,
The received signal includes a clock signal received in synchronization with data to be written to the storage device,
The said communication control part is a memory | storage device which performs the said switching based on the length of the specific pulse contained in the said clock signal. The storage device according to claim 2,
The storage device is connected to a clock signal line, a data signal line, and a reset signal line,
The clock signal line is a wiring for receiving the clock signal;
The data signal line is a wiring for transmitting and receiving the data,
The reset signal line is a wiring for receiving a reset signal for initializing the storage device,
The storage device according to claim 1, wherein the specific pulse is a pulse received a predetermined number after receiving the reset signal. The storage device according to any one of claims 1 to 3,
The high-speed control mode is a storage device in which the high-speed writing is performed in the specific area after erasing data stored in the specific area to be written in the nonvolatile memory in a batch. A consumable container,
A storage device according to any one of claims 1 to 4,
A consumable storage unit for storing the consumables;
A consumable container, comprising: The consumable container according to claim 5,
The consumable item is a consumable item container that is ink to be supplied to an inkjet printer. High-speed control mode for high-speed data writing to non-volatile memory capable of relatively high-speed data writing, and low-speed data for non-volatile memory capable of relatively low-speed data writing A method of switching a low-speed control mode for writing,
(A) preparing a nonvolatile memory capable of writing in any of the high-speed control mode and the low-speed control mode;
(B) automatically switching the communication control mode according to a received signal received from the external device;
A method for switching a communication control mode, comprising: High-speed control mode for high-speed data writing to non-volatile memory capable of relatively high-speed data writing, and low-speed data for non-volatile memory capable of relatively low-speed data writing A computer program for causing a storage device to execute a low-speed control mode switching process for writing,
The storage device includes a nonvolatile memory that can be written in any of the high-speed control mode and the low-speed control mode,
The computer program comprises a program for causing the computer to realize a function of automatically switching the communication control mode in accordance with a received signal received from the external device.

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