JP2005085921A - Multilayer circuit board and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a highly reliable multilayer circuit board having improved connection reliability of vias electrically connecting interlayer wiring layers and a method of manufacturing the same.
At least two wiring layers are formed on one side or both sides of an insulating base material 11 via an insulating layer, and the wiring layer is a multilayer circuit board that is via-connected, and is formed on a land. The vias are formed by providing a truncated cone-shaped conductor, a protruding conductor serving as a via on the depression of the land, and a protruding conductor serving as a via on the ring-shaped land, so that the protruding conductor and land Insulating resin layer formation during the manufacturing process of multilayer circuit boards, the protruding conductors do not leave the land in the peeling process, and the wiring layers between the layers are electrically connected It is possible to obtain a highly reliable multilayer circuit board with improved connection reliability of vias.
[Selection] Figure 1

Description

  The present invention relates to a multilayer circuit board such as a printed wiring board and an interposer used in various electronic devices and a manufacturing method thereof, and more particularly, to electrical wiring layers between layers in the multilayer circuit board such as a printed wiring board and an interposer. The present invention relates to an improved connection method.

In a multilayer circuit board in which at least two or more wiring layers are formed on one or both sides of an insulating substrate via an insulating layer, a thicker insulating layer is formed into a columnar shape (so-called so-called “high-density circuit board”). A multilayer circuit board in which stacked type vias are formed has been proposed (see, for example, Patent Document 1).
A conventional method for manufacturing a multilayer circuit board will be described below.
An example of a conventional multilayer circuit board manufacturing method is shown in FIGS. 11 (a) to 11 (e) and FIGS. 12 (f) to 12 (j).
First, electroless copper plating is performed on an insulating base material 11 in which a glass cloth is impregnated with an epoxy resin to form a thin film conductor layer 21, and a liquid photoresist is applied on the thin film conductor layer 21, or a dry film is laminated. A photosensitive layer is formed by a method such as the above, and a resist pattern 31 is formed by performing a series of patterning processes such as pattern exposure and development (see FIG. 11A).

Next, using the resist pattern 31 as a mask, electrolytic copper plating is performed to produce the circuit board 20 in which the conductor layer 41 having a predetermined thickness is formed on the unmasked thin film conductor layer 21 (see FIG. 11B). .
Next, the insulating resin layer 58 is formed by a method such as applying a resin solution on both surfaces of the circuit board 20 or laminating prepreg sheets (see FIG. 11C).

  Next, an opening 59 is formed at a predetermined position of the insulating resin layer 58 by laser processing, desmearing in the opening 59, plating catalyst nucleation and electroless copper plating are performed, and a plating underlayer (in particular, (Not shown) is formed (see FIG. 11D).

Next, electrolytic copper plating is performed using the plating base layer and the conductor layer 41 as a cathode to form a conductor 64 serving as a via in the opening 59 (see FIG. 11E).
Next, the insulating resin layer 58 and the resist pattern 31 are stripped with a dedicated stripping solution, and the thin film conductor layer 21 located under the resist pattern 31 is removed by etching, so that a protrusion that becomes a via on the land of the wiring layer 41a A two-layer circuit board 70 on which the conductor 64 is formed is obtained (see FIG. 12F).

Next, an insulating resin layer 74 is formed on both surfaces of the circuit board 70 so as to cover the protruding conductors 64 serving as vias by a method such as applying a resin solution or attaching a prepreg sheet (FIG. 12 ( g)).
Next, the surface of the insulating resin layer 74 is polished until the upper portion of the protruding conductor 64 is exposed, thereby forming the insulating layer 74a and the via 64a (see FIG. 12H).

  Next, plating catalyst nucleation and electroless copper plating are performed on the surface of the insulating layer 74a to form a plating underlayer (particularly not shown), and a photosensitive layer is formed by a method such as laminating a dry film, A series of patterning processes such as pattern exposure and development are performed to form a resist pattern 35 (see FIG. 12I).

Next, mask plating is performed by electrolytic copper plating, a conductor layer is formed on the unmasked plating base layer, the resist pattern 35 is stripped, and the plating base layer under the resist pattern 35 is removed by soft etching. Then, the wiring layer 46 is formed, and a four-layer multilayer circuit board 500 in which the wiring layer 41a and the wiring layer 46 are electrically connected by the via 64a is obtained (see FIG. 12J).

In the method for manufacturing a multilayer circuit board as described above, a protruding conductor serving as a via is formed and then a resin sheet is laminated, or a protruding conductor serving as a via is covered by a method such as applying a resin solution. Thus, the insulating resin layer is formed, and the surface of the insulating resin layer is polished to expose the upper portions of the protruding conductors to be vias, thereby forming the insulating layers and vias.
The height of the above-mentioned protruding conductor serving as a via is required to be about 40 to 50 μm because of the relationship between interlayer insulation and electrical characteristics. In recent years, due to the demand for finer wiring, the via diameter is 30 to 60 μm. It is requested.
In the method of forming the protruding conductor serving as the via, the projecting conductor serving as the via has a reverse tapered mortar shape, and the connection area between the protruding conductor serving as the via and the land has a diameter of the via. The adhesion strength with the land is considerably weakened.
For this reason, there arises a problem that the protruding conductor serving as the via is detached from the land in the resist pattern peeling step, the insulating resin layer forming step, and the peeling step.

However, due to recent demands for finer and higher density wiring layers, the via diameter is becoming increasingly finer, and the conventional via formation method is sufficient to obtain a highly reliable multilayer circuit board. The current situation is that it is no longer possible to respond to.
JP-A-6-302965

  The present invention has been devised in view of the above problems, and provides a highly reliable multilayer circuit board having improved connection reliability of vias electrically connecting interlayer wiring layers and a method for manufacturing the same. The purpose is to do.

  In order to achieve the above object, according to the first aspect of the present invention, in claim 1, at least two or more wiring layers are formed on one or both sides of an insulating substrate via an insulating layer, and the wiring layer is a via. In the multilayer circuit board connected, the via 61a is formed of a truncated cone-shaped conductor formed on the land of the wiring layer.

  Further, in claim 2, at least two wiring layers are formed on one side or both sides of the insulating substrate via an insulating layer, and the wiring layer is a multilayer circuit board formed by via connection, The via 62a is a multilayer circuit board characterized in that the via 62a is formed on a recess dug in the land of the wiring layer.

  Further, in claim 3, at least two or more wiring layers are formed on one side or both sides of the insulating base via an insulating layer, and the wiring layer is a multilayer circuit board formed by via connection, The via 63a is a multilayer circuit board provided in a ring-shaped land of a wiring layer.

According to a fourth aspect of the present invention, in the method for manufacturing a multilayer circuit board such as a printed wiring board or an interposer, the following steps are provided. .
(A) A thin film conductor layer 21 is formed on both surfaces of the insulating substrate 11, a photosensitive layer is formed on the thin film conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 31. Process.
(B) The process of producing the circuit board 20 which formed the conductor layer 41 in the predetermined position on the thin film conductor layer 21 by performing electrolytic copper plating using the resist pattern 31 as a mask.
(C) The resin sheet 51 and the resin sheet 52 in which the opening 53 is formed in a predetermined position are laminated on both surfaces of the circuit board 20 to form the insulating resin layers 51a and 52a in which the opening 53 is formed, Forming a plating base layer in the opening 53;
(D) A step of forming a conductor 61 in the opening 53 by performing electrolytic copper plating using the conductor layer 41 as a cathode.
(E) The insulating resin layer 51a, the insulating resin layer 52a, and the resist pattern 31 are peeled off, and the thin film conductor layer 21 under the resist pattern 31 is removed by etching, and the wiring layer 41a and the truncated cone are formed on the insulating substrate 11. The process of producing the circuit board 40 in which the shape conductor 61 was formed.
(F) A step of forming insulating resin layers 71 on both surfaces of the circuit board 40.
(G) A step of polishing the surface of the insulating resin layer 71 to form a via 61a in which the insulating layer 71a and the upper portion of the truncated conical conductor 61 are partially exposed.
(H) A step of forming a resist pattern 32 by forming a plating underlayer and a photosensitive layer and performing a series of patterning processes such as pattern exposure and development.
(I) A step of performing electrolytic copper plating using the resist pattern 32 as a mask, forming a conductor layer on an unmasked plating base layer, and stripping the resist pattern 32 to form a wiring layer 42.

Further, in the method of manufacturing a multilayer circuit board such as a printed wiring board or an interposer, the method according to claim 5 includes the following steps. .
(A) A thin film conductor layer 21 is formed on both surfaces of the insulating substrate 11, a photosensitive layer is formed on the thin film conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 31. Process.
(B) The process of producing the circuit board 20 which formed the conductor layer 41 in the predetermined position on the thin film conductor layer 21 by performing electrolytic copper plating using the resist pattern 31 as a mask.
(C) A step of forming insulating resin layers 54 having a predetermined thickness on both surfaces of the circuit board 20.
(D) A step of forming a recess 55a in the hole 55 and the conductor layer 41 at a predetermined position of the insulating resin layer 54 by laser processing, and forming a plating base layer in the hole 55.
(E) A step of forming a conductor 62 on the opening 55 and the depression 55a by performing electrolytic copper plating using the conductor layer 41 as a cathode.
(F) The insulating resin layer 54 and the resist pattern 31 are peeled off, the thin film conductor layer 21 under the resist pattern 31 is removed by etching, and the wiring layer 41a and the land depression 55a are projected on the insulating substrate 11. Manufacturing the circuit board 50 on which the conductor 62 is formed.
(G) A step of forming insulating resin layers 72 on both surfaces of the circuit board 50.
(H) A step of polishing the surface of the insulating resin layer 72 to form the insulating layer 72a and the via 62a in which the upper portion is partially exposed.
(I) A step of forming a resist pattern 33 by forming a plating base layer and a photosensitive layer and performing a series of patterning processes such as pattern exposure and development.
(J) A step of performing electrolytic copper plating using the resist pattern 33 as a mask, forming a conductor layer on an unmasked plating base layer, and stripping the resist pattern 33 to form a wiring layer 43.

Furthermore, in Claim 6, in the manufacturing method of multilayer circuit boards, such as a printed wiring board and an interposer, it is set as the manufacturing method of the multilayer circuit board of Claim 3 characterized by including the following processes. is there.
(A) A thin film conductor layer 21 is formed on both surfaces of the insulating base material 11, a photosensitive layer is formed on the thin film conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form resist patterns 34a and 34b. Forming.
(B) The process of producing the circuit board 30 which formed the conductor layer 42 on the thin film conductor layer 21 which is not masked by performing electrolytic copper plating using the resist patterns 34a and 34b as a mask.
(C) A step of forming insulating resin layers 56 having a predetermined thickness on both surfaces of the circuit board 30.
(D) A step of forming the opening portion 57 and the opening portion 57a at predetermined positions of the insulating resin layer 56 by laser processing, and forming a plating base layer in the opening portion 57 and the opening portion 57a.
(E) A step of performing electrolytic copper plating using the thin film conductor layer 21 and the conductor layer 42 as cathodes to form a conductor 63 in the opening 57 and the opening 57a.
(F) The insulating resin layer 56 and the resist pattern 34a are peeled off, and the thin film conductor layer 21 under the resist pattern 34a is removed by etching, and the wiring layer 42a and the ring-shaped land 42b are projected on the insulating substrate 11. The process of producing the circuit board 60 in which the conductor 63 was formed. (G) A step of forming an insulating resin layer 73 on both surfaces of the circuit board 60.
(H) A step of polishing the surface of the insulating resin layer 73 to form the insulating layer 73a and the via 63a partially exposed at the top.
(I) A step of forming a resist pattern 35 by forming a plating base layer and a photosensitive layer and performing a series of patterning processes such as pattern exposure and development.
(J) A step of performing electrolytic copper plating using the resist pattern 35 as a mask, forming a conductor layer on an unmasked plating base layer, and stripping the resist pattern 35 to form a wiring layer 45.

  The multilayer circuit board of the present invention is provided with a truncated cone-shaped conductor serving as a via on the land of the wiring layer, a protruding conductor serving as a via on the depression of the land, and a protruding conductor serving as a via on the ring-shaped land. Since the via is formed, the adhesion between the protruding conductor and the land is improved, and the protruding conductor is detached from the land in the formation and peeling process of the insulating resin layer during the manufacturing process of the multilayer circuit board. Rather, it is possible to obtain a highly reliable multilayer circuit board (printed wiring board or interposer) in which the connection reliability of vias that electrically connect the wiring layers between layers is improved.

An embodiment of a multilayer circuit board comprising a printed wiring board or an interposer of the present invention will be described.
As shown in FIG. 1, the multilayer circuit board 100 according to the first aspect of the present invention has a wiring layer 41 a and a wiring layer 42 formed on both surfaces of an insulating base material 11 via an insulating layer 71 a. And the wiring layer 42 are electrically connected by a via 61a. The via 61a is formed of a frustoconical conductor on the land of the wiring layer 41a. By forming the via 61a into a truncated cone shape, a frustoconical shape that becomes a via during the manufacturing process of a multilayer circuit board described later is formed. During the process of forming the conductor on the land (particularly, the insulating resin layer forming, polishing, and peeling process), the truncated cone-shaped conductor hardly detaches from the land, and the wiring layer 41a and the wiring layer 42 are stabilized. An electrical connection is obtained.

  In the multilayer circuit board 200 of the present invention according to claim 2, as shown in FIG. 2, the wiring layer 41a and the wiring layer 43 are formed on both surfaces of the insulating substrate 11 via the insulating layer 72a. And the wiring layer 43 are electrically connected by a via 62a. The via 62a is formed on the land depression of the wiring layer 41a. By adopting such a structure, the contact area between the lower portion of the via 62a and the land is increased, and the adhesion strength between the protruding conductor serving as the via and the land is improved. During the manufacturing process of the multilayer circuit board described later, the protruding conductor is removed from the land during the process of forming the protruding conductor serving as a via on the depression of the land (particularly, the insulating resin layer formation, polishing, peeling process). The wiring layer 41a and the wiring layer 43 can be stably connected to each other without being separated.

  As shown in FIG. 3, the multilayer circuit board 300 according to the third aspect of the present invention includes the wiring layer 41a and the wiring layer 45 formed on both surfaces of the insulating base material 11 via the insulating layer 73a. And the wiring layer 45 are electrically connected by a via 63a. The via 63a is formed in the ring-shaped land 41b of the wiring layer 41a. By adopting such a structure, the adhesion strength between the protruding conductors and lands serving as vias is improved, and the projecting conductors serving as vias are formed in the ring shape of the wiring layer during the manufacturing process of the multilayer circuit board described later. During the process of forming on the land (particularly, the formation, polishing, and peeling process of the insulating resin layer), the protruding conductor hardly detaches from the land, and stable electrical connection between the wiring layer 41a and the wiring layer 45 is achieved. can get.

FIGS. 4A to 4D schematically show an example of forming a protruding conductor on a land, and FIG. 4A shows an example in which a truncated cone-shaped conductor 61 is formed on the land. FIG. 4B shows an example in which the protruding conductor 63 is formed on the ring-shaped land, and FIG. 4C shows an example in which the protruding conductor 62 is formed in the depression of the land. These show an example in which a projecting conductor 64 having a reverse taper shape is formed on a land, respectively.
Here, when the tip of the protrusion-like conductor is pressed with a certain force F, the adhesion strength between the protrusion-like conductor and the land is the strongest in FIG. 4 (b) in which a protruding conductor 63 is provided on a ring-shaped land, FIG. 4 (c) in which a protruding conductor 62 is provided in a depression in the land, and a reverse-tapered protruding conductor 64 is provided on the land. The adhesion strength decreases in the order of FIG.

Hereinafter, the manufacturing method of the multilayer circuit board of this invention is demonstrated.
A method for manufacturing a multilayer circuit board according to a fourth aspect of the present invention will be described.
5 (a) to 5 (e) and FIGS. 6 (f) to (i) are schematic partial cross-sectional views showing an embodiment of the method for manufacturing a multilayer circuit board according to the fourth aspect in the order of steps. .
First, the thin film conductor layer 21 is formed on the insulating substrate 11 made of epoxy resin by a method such as electroless copper plating, and the photosensitive layer is formed by laminating a dry film or applying a resist solution with a spinner. A resist pattern 31 is formed by performing a series of patterning processes such as pattern exposure and development (see FIG. 5A).

Next, electrolytic copper plating is performed using the resist pattern 31 as a mask to form a conductor layer 41 having a predetermined thickness on the unmasked thin-film conductor layer 21 to produce the circuit board 20 (see FIG. 5B). .
Next, the resin sheet 51 in which the opening 53 is formed at a predetermined position and the resin sheet 52 are laminated on both sides of the circuit board 20, and the insulating resin layer 51a in which the opening 53 is formed on both sides of the circuit board 20. And 52a are formed, and the residue on the aperture conductor is removed with a dedicated alkaline solution to form a plating underlayer (not shown) (see FIG. 5C).

  Here, the insulating resin layers 51a and 52a are provided to form a protruding conductor serving as a via on the land of the wiring layer, and are removed after forming the protruding conductor serving as a via. Resins that are soluble in a stripping solution such as alkali (for example, acrylic resins) are preferable.

Next, electrolytic copper plating is performed using the conductor layer 41 as a cathode to form a conductor 61 in the opening 53 (see FIG. 5D).
Next, the insulating resin layer 51a, the insulating resin layer 52a, and the resist pattern 31 are stripped with a dedicated stripping solution, and the thin film conductor layer 21 under the resist pattern 31 is removed by etching. The circuit board 40 on which the layer 41a and the truncated conical conductor 61 are formed is manufactured (see FIG. 5E).

Next, a resin sheet made of an epoxy resin or the like is laminated on both surfaces of the circuit board 40 to form an insulating resin layer 71 having a predetermined thickness (see FIG. 6F). Here, the thickness of the insulating resin layer 71 is such that it covers the truncated cone-shaped conductor 61, but since it will be polished later, it may be a resin layer that is about 5 μm thicker than the tip of the truncated cone-shaped conductor 61. That's fine.

Next, the surface of the insulating resin layer 71 is polished until a part of the upper part of the truncated conical conductor 61 is exposed, thereby forming a via 61a and an insulating layer 71a where the upper part of the truncated conical conductor 61 is partially exposed ( (Refer FIG.6 (g)).
Next, plating catalyst nuclei are applied to the surface of the insulating layer 71a, electroless copper plating is performed to form a plating underlayer (not shown in particular), a dry film is laminated to form a photosensitive layer, pattern exposure, development A series of patterning processes such as the above are performed to form a resist pattern 32 (see FIG. 6H).

  Next, electrolytic copper plating is performed using the resist pattern 32 as a mask, a conductor layer is formed on the unmasked plating base layer, the resist pattern 32 is peeled off, and the plating base layer under the resist pattern 32 is formed. The wiring layer 42 is formed by etching to form the wiring layer 42, the wiring layer 41 a and the wiring layer 42 are formed on both surfaces of the insulating base material 11 via the insulating layer 71 a, and the wiring layer 41 a and the wiring layer 42 are electrically connected by the via 61 a. 4 layers of multilayer circuit boards 100 can be obtained (see FIG. 6 (i)).

  Thus, since the via 61a is formed after forming the truncated cone-shaped conductor 61 on the land, the adhesion strength between the truncated cone-shaped conductor 61 and the land is ensured during the manufacturing process of the multilayer circuit board. During the process, the truncated conical conductor 61 is not detached from the land.

A method for manufacturing a multilayer circuit board according to a fifth aspect of the present invention will be described.
7 (a) to 7 (e) and FIGS. 8 (f) to 8 (j) are schematic partial cross-sectional views showing an embodiment of the method for manufacturing a multilayer circuit board according to the fourth aspect in the order of steps. .

  First, the thin film conductor layer 21 is formed on the insulating substrate 11 made of epoxy resin by a method such as electroless copper plating, and the photosensitive layer is formed by laminating a dry film or applying a resist solution with a spinner. The resist pattern 31 is formed by performing a series of patterning processes such as pattern exposure and development (see FIG. 7A).

Next, electrolytic copper plating is performed using the resist pattern 31 as a mask to form a conductor layer 41 having a predetermined thickness on the unmasked thin-film conductor layer 21, thereby producing the circuit board 20 (see FIG. 7B). .
Next, an acrylic resin sheet is laminated on both surfaces of the circuit board 20 to form an insulating resin layer 54 (see FIG. 7C).

  Here, the insulating resin layer 54 is provided to form a protruding conductor serving as a via on the land of the wiring layer and is removed after the protruding conductor serving as a via is formed. A resin (for example, an acrylic resin or the like) that dissolves in the release liquid is preferable.

Next, a hole is machined at a predetermined position of the insulating resin layer 54 to form a recess 55a having a predetermined depth in the opening 55 and the conductor layer 41, and a special alkaline solution is used to form a hole 55a on the opening conductor. Residue removal is performed to form a plating underlayer (particularly not shown) (see FIG. 7D).
Here, a YAG laser or a carbon dioxide gas laser is used as the laser, and the depth of the depression is set to 1/2 of the conductor layer thickness.

Next, electrolytic copper plating is performed using the conductor layer 41 as a cathode to form a conductor 62 on the opening 55 and the recess 55a (see FIG. 7E).
Next, the insulating resin layer 54 and the resist pattern 31 are stripped with a dedicated stripping solution, the thin film conductor layer 21 under the resist pattern 31 is removed by etching, and the wiring layer 41a and the protruding shape are formed on the insulating substrate 11. The circuit board 50 on which the conductor 62 is formed is manufactured (see FIG. 8F).

  Next, a resin sheet made of epoxy resin or the like is laminated on both surfaces of the circuit board 50 to form an insulating resin layer 72 having a predetermined thickness (see FIG. 8G). Here, the film thickness of the insulating resin layer 72 is such that it covers the protruding conductor 62, but since it will be polished later, it may be a resin layer that is about 5 μm thicker than the tip of the protruding conductor 62. .

  Next, the surface of the insulating resin layer 72 is polished until the upper portion of the protruding conductor 62 is partially exposed, thereby forming the via 62a and the insulating layer 72a where the upper portion of the protruding conductor 62 is exposed (FIG. 8). (See (h)).

  Next, plating catalyst nuclei are applied to the surface of the insulating layer 72a, electroless copper plating is performed to form a plating underlayer (not shown in particular), a dry film is laminated to form a photosensitive layer, pattern exposure, development The resist pattern 33 is formed by performing a series of patterning processes such as (see FIG. 8I).

  Next, electrolytic copper plating is performed using the resist pattern 33 as a mask, a conductor layer is formed on the unmasked plating base layer, the resist pattern 33 is peeled off, and the plating base layer under the resist pattern 33 is formed. The wiring layer 43 is formed by etching to form the wiring layer 43, and the wiring layer 41a and the wiring layer 43 are formed on both surfaces of the insulating base 11 via the insulating layer 72a. The wiring layer 41a and the wiring layer 43 are electrically connected by the via 62a. 4 layers of multilayer circuit boards 200 can be obtained.

  As described above, since the via 62a is formed after the protruding conductor 62 is formed on the land depression, the adhesion strength between the protruding conductor 62 and the land during the manufacturing process of the multilayer circuit board is ensured. In the process, the protruding conductor 62 is not detached from the land.

A method for manufacturing a multilayer circuit board according to a sixth aspect of the present invention will be described.
9 (a) to 9 (e) and FIGS. 10 (f) to 10 (j) are schematic partial cross-sectional views showing an embodiment of the method for manufacturing a multilayer circuit board according to the sixth aspect in the order of steps. .
First, the thin film conductor layer 21 is formed on the insulating substrate 11 made of epoxy resin by a method such as electroless copper plating, and the photosensitive layer is formed by laminating a dry film or applying a resist solution with a spinner. Then, a series of patterning processes such as pattern exposure and development are performed to form resist patterns 34a and 34b (see FIG. 9A). Here, a resist pattern 34b is formed in the center of the pattern in which the land is formed (see FIG. 9 (a ')) to form a resist pattern for forming a ring-shaped land by plating.

Next, electrolytic copper plating is performed using the resist patterns 34a and 34b as masks, a conductor layer 42 having a predetermined thickness is formed on the unmasked thin film conductor layer 21, and the circuit board 30 is fabricated (FIG. 9B). And (b ′)).
Next, an acrylic resin sheet is laminated on both surfaces of the circuit board 30 to form an insulating resin layer 56 (see FIG. 9C).
Here, the insulating resin layer 56 is provided to form a protruding conductor serving as a via on the land of the wiring layer, and is removed after the protruding conductor serving as a via is formed. A resin (for example, an acrylic resin or the like) that dissolves in the release liquid is preferable.

Next, a hole is formed at a predetermined position of the insulating resin layer 56 with a laser to form an opening 57 and an opening 57a, and the openings 57 and 57a are formed on the conductors in the opening 57a using a dedicated alkaline solution. The plating underlayer (in particular, not shown) is formed by removing the residue (see FIG. 9D).
Here, as a laser, a YAG laser or a carbon dioxide gas laser is used, and the resist pattern 34b is positioned below the opening 57, and the resist pattern 34b is also laser processed to form the opening 57a. And the side surface of the conductor 42 is exposed.

Next, electrolytic copper plating is performed using the thin-film conductor layer 21 and the conductor layer 42 as cathodes to form conductors 63 in the opening portions 57 and the opening portions 57a (see FIG. 9E).
Next, the insulating resin layer 56 and the resist pattern 34a are stripped with a dedicated stripping solution, and the thin film conductor layer 21 under the resist pattern 34a is removed by etching, and the wiring layer 42a and the ring shape are formed on the insulating base material 11. A circuit board 60 in which a protruding conductor 63 is formed on the land 42b is produced (see FIG. 10F).

  Next, a resin sheet made of epoxy resin or the like is laminated on both surfaces of the circuit board 60 to form an insulating resin layer 72 having a predetermined thickness (see FIG. 10G). Here, the film thickness of the insulating resin layer 73 is such that it covers the protruding conductor 63, but since it is polished later, it may be a resin layer that is about 5 μm thicker than the tip of the protruding conductor 63. .

Next, the surface of the insulating resin layer 73 is polished until a part of the upper portion of the protruding conductor 63 is exposed to form a via 63a and an insulating layer 73a where the upper part of the protruding conductor 63 is partially exposed (FIG. 10). (See (h)).
Next, plating catalyst nuclei are applied to the surface of the insulating layer 73a, electroless copper plating is performed to form a plating underlayer (not shown), a dry film is laminated to form a photosensitive layer, pattern exposure, development A series of patterning processes such as the above are performed to form a resist pattern 35 (see FIG. 10I).

  Next, electrolytic copper plating is performed using the resist pattern 35 as a mask, a conductor layer is formed on the unmasked plating base layer, the resist pattern 35 is stripped, and the plating base layer under the resist pattern 35 is formed. The wiring layer 45 is formed by etching to form the wiring layer 45, and the wiring layer 42a and the wiring layer 45 are formed on both surfaces of the insulating base material 11 via the insulating layer 73a. The wiring layer 42a and the wiring layer 45 are electrically connected by the via 63a. 4 layers of multilayer circuit boards 300 can be obtained.

  Thus, since the via 63a is formed after the protruding conductor 63 is formed on the ring-shaped land, the lower portion of the protruding conductor 63 is held by the conductor side surface at the center of the land. The adhesion strength between the protruding conductor 63 and the land during the manufacturing process is ensured, and the protruding conductor 63 is not detached from the land during the manufacturing process.

Hereinafter, the present invention will be described in detail by way of examples.
First, plating catalyst nucleation and electroless copper plating are performed on both surfaces of an insulating base material 11 in which a glass cloth is impregnated with an epoxy resin to form a thin film conductor layer 21. A photosensitive layer was formed by laminating a film photoresist, and pattern exposure and development were performed to form a resist pattern 31 (see FIG. 5A).

Next, electrolytic copper plating was performed using the resist pattern 31 as a mask to form a conductor layer 41 having a thickness of 12 μm, and the circuit board 20 was fabricated (see FIG. 5B).
Next, an acrylic resin sheet 51 and a resin sheet 52 in which the opening 53 is formed using a UVYAG laser at a predetermined position are laminated on both sides of the circuit board 20, and the opening 53 is formed on both sides of the circuit board 20. The formed insulating resin layers 51a and 52a are formed, and the residue on the conductor in the opening 53 is removed using a dedicated alkaline solution to form a plating base layer (not shown in particular) (FIG. 5). (See (c)).

Next, electrolytic copper plating was performed using the conductor layer 41 as a cathode to form a conductor 61 in the opening 53 (see FIG. 5D).
Next, the insulating resin layer 51a, the insulating resin layer 52a, and the resist pattern 31 are stripped with a dedicated stripping solution, and the thin film conductor layer 21 located under the resist pattern 31 is removed by soft etching with an aqueous ammonium persulfate solution. A circuit board 40 in which a wiring layer 41a and a truncated cone-shaped conductor 61 were formed on the material 11 was produced (see FIG. 5E).

Next, a resin sheet made of an epoxy resin was laminated on both surfaces of the circuit board 40 with a vacuum pressure heating laminator to form an insulating resin layer 71 having a thickness of 40 μm (see FIG. 6F).
Next, the surface of the insulating resin layer 71 was polished by about 3 μm to form a truncated cone-shaped conductor 61a and an insulating resin layer 71a in which the upper part of the truncated cone-shaped conductor 61 was partially exposed (see FIG. 6G). .

  Next, plating catalyst nucleation and electroless copper plating are performed on the surface of the insulating resin layer 71a to form a plating base layer (not shown in particular), and a dry film photoresist having a thickness of 12 μm is laminated to form a photosensitive layer. Then, pattern exposure and development were performed to form a resist pattern 32 (see FIG. 6H).

  Next, electrolytic copper plating is performed using the resist pattern 32 as a mask, a conductor layer is formed on the unmasked plating base layer, the resist pattern 32 is stripped with a dedicated stripping solution, and the resist pattern 32 is formed under the resist pattern 32. The plated underlayer was removed by soft etching with an aqueous ammonium persulfate solution to form the wiring layer 42, and the wiring layer 41a and the wiring layer 42 were formed on both surfaces of the insulating base 11 via the insulating layer 71a. A four-layer multilayer circuit board 100 was obtained in which the wiring layer 42 and the wiring layer 42 were electrically connected by a via 61a (see FIG. 6I).

First, a conductor layer 41 having a thickness of 12 μm on both sides of an insulating base material 11 in which a glass cloth was impregnated with an epoxy resin was formed in the same manner as in Example 1 to fabricate a circuit board 20 (FIGS. 7A and 7B). b)).
Next, an acrylic resin sheet was laminated on both surfaces of the circuit board 20 with a vacuum pressure heating laminator to form an insulating resin layer 54 on both surfaces of the circuit board 20 (see FIG. 7C).

  Next, a hole is formed at a predetermined position of the insulating resin layer 54 using a UVYAG laser to form a recess 55a having a depth of 6 μm in the opening 55 and the conductor layer 41, and the opening is formed using a dedicated alkaline solution. The residue on the inner conductor 55 was removed to form a plating underlayer (particularly not shown) (see FIG. 7D).

Next, electrolytic copper plating was performed using the conductor layer 41 as a cathode, and a conductor 62 was formed on the opening 55 and the recess 55a (see FIG. 7E).
Next, the insulating resin layer 54 and the resist pattern 31 are stripped with a dedicated stripping solution, and the thin film conductor layer 21 located under the resist pattern 31 is removed by soft etching with an aqueous ammonium persulfate solution. A circuit board 50 on which the layer 41a and the protruding conductors 62 were formed was produced (see FIG. 8F).

Next, an epoxy resin sheet was laminated on both surfaces of the circuit board 50 with a vacuum pressure heating laminator to form an insulating resin layer 72 having a thickness of 40 μm (see FIG. 8G).
Next, the surface of the insulating resin layer 72 was polished by about 3 μm to form a protruding conductor 62a and an insulating resin layer 72a partially exposed (see FIG. 8H).

  Next, plating catalyst nucleation and electroless copper plating are performed on the surface of the insulating resin layer 72a to form a plating underlayer (not shown), and a dry film photoresist having a thickness of 12 μm is laminated to form a photosensitive layer. Then, pattern exposure and development were performed to form a resist pattern 33 (see FIG. 8I).

  Next, electrolytic copper plating is performed using the resist pattern 33 as a mask, a conductor layer is formed on the unmasked plating base layer, the resist pattern 33 is stripped with a dedicated stripping solution, and the resist pattern 33 is formed under the resist pattern 33. The plated underlayer was removed by soft etching with an aqueous ammonium persulfate solution to form the wiring layer 43, and the wiring layer 41a and the wiring layer 43 were formed on both surfaces of the insulating base 11 via the insulating layer 72a. A four-layer multilayer circuit board 200 was obtained in which the wiring layer 43 and the wiring layer 43 were electrically connected by a via 62a (see FIG. 8J).

  First, plating catalyst nucleation and electroless copper plating are performed on both surfaces of an insulating base material 11 in which a glass cloth is impregnated with an epoxy resin to form a thin film conductor layer 21, and a 12 μm thick dry film is formed on the surface of the thin film conductor layer 21. Film photoresist was laminated to form a photosensitive layer, and pattern exposure and development were performed to form a resist pattern 34a and a resist pattern 34b (see FIGS. 9A and 9A).

  Next, electrolytic copper plating was performed using the resist pattern 34a and the resist pattern 34b as a mask to form a 12 μm-thick conductor layer 42 on the unmasked thin-film conductor layer 21 to produce a circuit board 30 (FIG. 9 ( b) and (b ′)).

  Next, an acrylic resin sheet was laminated on both surfaces of the circuit board 30 with a vacuum pressure heating laminator to form an insulating resin layer 56 on both surfaces of the circuit board 30 (see FIG. 9C).

  Next, drilling is performed at a predetermined position of the insulating resin layer 56 using a UVYAG laser to form openings 57 and 57a, and residues on the conductors in the openings 57 and 57a are removed using a dedicated alkaline solution. Then, a plating underlayer (not shown in particular) was formed (see FIG. 9D).

Next, electrolytic copper plating was performed using the conductor layer 42 as a cathode to form a conductor 63 in the opening portions 57 and 57a (see FIG. 9E).
Next, the insulating resin layer 56 and the resist pattern 34a are stripped with a dedicated stripping solution, and the thin film conductor layer 21 located under the resist pattern 34a is removed by soft etching with an aqueous ammonium persulfate solution. A circuit board 60 in which the protruding conductor 63 was formed on the layer 42a and the ring-shaped land 42b was produced (see FIG. 10F).

Next, resin sheets made of an epoxy resin were laminated on both surfaces of the circuit board 50 with a vacuum pressure heating laminator to form an insulating resin layer 73 having a thickness of 40 μm (see FIG. 10G).
Next, the surface of the insulating resin layer 73 was polished by about 3 μm to form a protruding conductor 63a and an insulating layer 73a in which the upper portion of the protruding conductor 63 was partially exposed (see FIG. 8H).

  Next, plating catalyst nucleation and electroless copper plating are performed on the surface of the insulating resin layer 73a to form a plating base layer (not shown in particular), and a dry film photoresist having a thickness of 12 μm is laminated to form a photosensitive layer. The resist pattern 35 was formed by pattern exposure and development (see FIG. 10I).

Next, electrolytic copper plating is performed using the resist pattern 35 as a mask, a conductor layer is formed on the unmasked plating underlayer, the resist pattern 35 is stripped with a dedicated stripping solution, and a lower portion of the resist pattern 35 is formed. The plating underlayer was removed by soft etching with an aqueous solution of ammonium persulfate to form the wiring layer 45, and the wiring layer 42a and the wiring layer 45 were formed on both surfaces of the insulating substrate 11 via the insulating layer 73a. A four-layer multilayer circuit board 300 was obtained in which the wiring layer 45 and the wiring layer 45 were electrically connected by a via 63a (see FIG. 10J).

It is a fragmentary sectional view which shows typically the structure of the multilayer circuit board which concerns on Claim 1 of this invention. It is a fragmentary sectional view which shows typically the structure of the multilayer circuit board which concerns on Claim 2 of this invention. It is a fragmentary sectional view which shows typically the structure of the multilayer circuit board which concerns on Claim 3 of this invention. (A)-(d) is explanatory drawing which showed typically the example of protrusion-shaped conductor formation on a land. (A)-(e) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board based on Claim 4 of this invention. (F)-(i) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board based on Claim 4 of this invention. (A)-(e) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board based on Claim 5 of this invention. (F)-(j) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board which concerns on Claim 5 of this invention. (A)-(e) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board based on Claim 6 of this invention. (A ') and (b') are schematic plan views of a wiring layer and a land portion. (F)-(j) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the multilayer circuit board which concerns on Claim 6 of this invention. (A)-(e) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the conventional multilayer circuit board. (F)-(j) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the conventional multilayer circuit board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating base material 20, 30, 40, 50, 60, 70 ... Circuit board 21 ... Thin film conductor layers 31, 32, 33, 34a, 34b ... Resist pattern 41, 42 ... Conductor layers 41a, 42a , 43, 45, 46... Wiring layer 42 b... Ring-shaped land 51, 52... Resin sheet 51 a, 52 a, 54, 56, 58, 71, 72, 73, 74 ...... insulating resin layer 53, 55, 57 59 ... Opening 55a ... Depression 57a on the conductor layer ... Opening 61 in the conductor layer ... Frustum-shaped conductors 62, 63, 64 ... Protruding conductors 61a, 62a, 63a, 64a ... vias 71a, 72a, 73a, 74a ... insulating layers 100, 200, 300, 500 ... multilayer circuit boards

Claims (6)

  At least two or more wiring layers are formed on one side or both sides of an insulating substrate via an insulating layer, and the wiring layer is a multilayer circuit board formed by via connection, and the via (61a) is a wiring layer. A multi-layer circuit board comprising a truncated cone-shaped conductor formed on a land.   At least two or more wiring layers are formed on one side or both sides of an insulating substrate via an insulating layer, and the wiring layer is a multilayer circuit board formed by via connection, and the via (62a) is a wiring layer. A multilayer circuit board, characterized in that the multilayer circuit board is formed on a depression dug in a land of   At least two or more wiring layers are formed on one side or both sides of an insulating substrate via an insulating layer, and the wiring layer is a multilayer circuit board formed by via connection, and the via (63a) is a wiring layer. A multilayer circuit board provided on a ring-shaped land. 2. The method for manufacturing a multilayer circuit board according to claim 1, comprising the following steps in the method for manufacturing a multilayer circuit board such as a printed wiring board or an interposer.
(A) A thin film conductor layer (21) is formed on both surfaces of the insulating substrate (11), a photosensitive layer is formed on the thin film conductor layer (21), and a series of patterning processes such as pattern exposure and development are performed. And a step of forming a resist pattern (31).
(B) The process of producing the circuit board (20) which formed the conductor layer (41) in the predetermined position on the thin film conductor layer (21) by performing electrolytic copper plating using the resist pattern (31) as a mask.
(C) The resin sheet (51) and the resin sheet (52) each having the opening (53) formed at a predetermined position are laminated on both sides of the circuit board (20) to form the opening (53). A step of forming an insulating resin layer (51a) and an insulating resin layer (52a), and forming a plating base layer in the opening (53).
(D) A step of forming a conductor (61) in the opening (53) by performing electrolytic copper plating using the conductor layer (41) as a cathode.
(E) The insulating resin layer (51a), the insulating resin layer (52a), and the resist pattern (31) are stripped, and the thin film conductor layer (21) under the resist pattern (31) is removed by etching. A step of producing a circuit board (40) in which a wiring layer (41a) and a truncated cone-shaped conductor (61) are formed on a material (11).
(F) A step of forming insulating resin layers (71) on both surfaces of the circuit board (40).
(G) A step of polishing the surface of the insulating resin layer (71) to form a via (61a) in which the insulating layer (71a) and the upper part of the truncated conical conductor (61) are partially exposed.
(H) A step of forming a plating underlayer and a photosensitive layer, and performing a series of patterning processes such as pattern exposure and development to form a resist pattern (32).
(I) Electrolytic copper plating is performed using the resist pattern (32) as a mask, a conductor layer is formed on an unmasked plating base layer, and the resist pattern (32) is stripped to form a wiring layer (42). Process. The method for producing a multilayer circuit board according to claim 2, comprising the following steps in the method for producing a multilayer circuit board such as a printed wiring board or an interposer.
(A) A thin film conductor layer (21) is formed on both surfaces of the insulating substrate (11), a photosensitive layer is formed on the thin film conductor layer (21), and a series of patterning processes such as pattern exposure and development are performed. And a step of forming a resist pattern (31).
(B) The process of producing the circuit board (20) which formed the conductor layer (41) in the predetermined position on the thin film conductor layer (21) by performing electrolytic copper plating using the resist pattern (31) as a mask.
(C) A step of forming an insulating resin layer (54) having a predetermined thickness on both surfaces of the circuit board (20).
(D) A hole (55) and a recess (55a) are formed on the insulating resin layer (54) at a predetermined position by laser processing on the conductor layer (41), and a plating base layer is formed in the hole (55). Forming.
(E) A step of forming a conductor (62) on the opening (55) and the depression (55a) by performing electrolytic copper plating using the conductor layer (41) as a cathode.
(F) The insulating resin layer (54) and the resist pattern (31) are peeled off, the thin film conductor layer (21) under the resist pattern (31) is removed by etching, and the wiring is formed on the insulating substrate (11). A step of producing a circuit board (50) in which a protruding conductor (62) is formed on the layer (41a) and the land depression (55a).
(G) A step of forming insulating resin layers (72) on both surfaces of the circuit board (50).
(H) A step of polishing the surface of the insulating resin layer (72) to form the insulating layer (72a) and a via (62a) partially exposed at the top.
(I) A step of forming a plating underlayer and a photosensitive layer, and performing a series of patterning processes such as pattern exposure and development to form a resist pattern (33).
(J) Electrolytic copper plating is performed using the resist pattern (33) as a mask, a conductor layer is formed on the unmasked plating base layer, and the resist pattern (33) is removed to form a wiring layer (43). Process. 4. The method of manufacturing a multilayer circuit board according to claim 3, comprising the following steps in a method of manufacturing a multilayer circuit board such as a printed wiring board or an interposer.
(A) A thin film conductor layer (21) is formed on both surfaces of the insulating substrate (11), a photosensitive layer is formed on the thin film conductor layer (21), and a series of patterning processes such as pattern exposure and development are performed. And a step of forming resist patterns (34a) and (34b).
(B) Electrolytic copper plating is performed using the resist patterns (34a) and (34b) as a mask to produce a circuit board (30) in which a conductor layer (42) is formed on an unmasked thin film conductor layer (21). Process.
(C) A step of forming insulating resin layers (56) having a predetermined thickness on both surfaces of the circuit board (30).
(D) An opening (57) and an opening (57a) are formed at predetermined positions of the insulating resin layer (56) by laser processing, and plating is performed in the opening (57) and the opening (57a). Forming an underlayer.
(E) A step of performing electrolytic copper plating using the thin-film conductor layer (21) and the conductor layer (42) as a cathode to form a conductor (63) in the opening (57) and the opening (57a).
(F) The insulating resin layer (56) and the resist pattern (34a) are peeled off, the thin film conductor layer (21) under the resist pattern (34a) is removed by etching, and the wiring is formed on the insulating substrate (11). A step of producing a circuit board (60) in which a protruding conductor (63) is formed on the layer (42a) and the ring-shaped land (42b).
(G) A step of forming an insulating resin layer (73) on both surfaces of the circuit board (60).
(H) A step of polishing the surface of the insulating resin layer (73) to form the insulating layer (73a) and a via (63a) partially exposed at the top.
(I) A step of forming a plating underlayer and a photosensitive layer, and performing a series of patterning processes such as pattern exposure and development to form a resist pattern (35).
(J) Electrolytic copper plating is performed using the resist pattern (35) as a mask, a conductor layer is formed on an unmasked plating base layer, and the resist pattern (33) is stripped to form a wiring layer (45). Process.