JP2005079116A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for preventing diffusion to the interlayer insulating film of a wiring material, such as a barrier metal and Cu. <P>SOLUTION: The method for manufacturing the semiconductor device has a process for forming a thin film made of an insulating material on a substrate, a process for opening a hole on the thin film, a process for exposing the thin film to the atmosphere of rare gas plasma, and a process for depositing a conductive material into the hole. In this manner by forming a reformed layer on the surface of the interlayer insulating film, the diffusion to the interlayer insulating film of the barrier metal and the wiring material (Cu) can be prevented reliably and easily. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor element device having an interlayer insulating film and using Cu (copper) wiring.
[0002]
[Prior art]
In recent semiconductor devices typified by the 65 nm node generation, the delay of signal propagation in the wiring determines the device operation. The delay constant in wiring is represented by the product of wiring resistance and wiring capacitance. For this reason, in order to reduce the wiring resistance and speed up the device operation, a material having a relative dielectric constant smaller than that of conventional SiO ₂ is used as the material of the interlayer insulating film, and Cu (copper) having a small specific resistance as the wiring material. Is being used.
[0003]
Cu multilayer wiring is often formed by a damascene method.
[0004]
FIG. 13 is a process cross-sectional view illustrating a main part of the damascene method.
That is, first, as shown in FIG. 2A, an interlayer insulating film 220 is formed on a base body 200 such as a silicon (Si) substrate. Next, as illustrated in FIG. 13B, a hole H is formed in the interlayer insulating film 220. The hole H serves as a wiring groove for a wiring layer and a via hole for a via. Next, as shown in FIG. 13C, the barrier metal layer 240 is formed on the inner wall of the hole H. Further, as shown in FIG. 13D, a Cu layer 260 is embedded as a wiring material. Here, in embedding the Cu layer 260, first, Cu is deposited in a thin film by a method such as a physical vapor deposition (PVD) method, and the Cu thin film is buried by an electrolytic plating method or the like as a cathode electrode. Are often implemented.
[0005]
In the damascene method, the barrier metal layer 240 and the Cu layer 260 are deposited, and then the barrier metal 240 and the Cu layer 260 deposited outside the hole H are chemically mechanically polished (chemical mechanical polishing: CMP). ) To form a buried structure as shown in FIG.
[0006]
Here, the barrier metal layer 240 has a role of preventing Cu diffusion to the base 200 such as a silicon substrate, improving adhesion between the interlayer insulating film 220 and the Cu layer 260, and preventing oxidation of the Cu layer 260. .
[0007]
Non-patent documents 1 and 2 can be cited as documents disclosing wiring structures using an interlayer insulating film as described above.
[0008]
[Non-Patent Document 1]
K. Maex, M.M. R. Baklanov, D.M. Shamiryan, F .; Iacopi, S .; H. Brongersma, Z. S. Yanovitskaya, Journal of Applied Physics 93 (11), pp. 8793-8841, 2003.
[Non-Patent Document 2]
W. Besling, A.D. Satta, J .; Schuhmacher, T .; Abell, V.A. Sutcliffe, A.M. -M. Hoyas, G .; Beyer, D.D. Gravesteijn, K.M. Maex, Proceedings of IEEE 2002 International Interconnect Technology Conference, pp. 288-291
[0009]
[Problems to be solved by the invention]
The porous insulator material is a promising candidate for a low dielectric constant material for the interlayer insulating film 220. However, when a Cu multilayer wiring structure is formed using this, it becomes a problem that the barrier metal material or Cu enters the porous hole in the barrier metal deposition process or the Cu deposition process. In this case, when the barrier metal enters the porous hole, the film thickness of the barrier metal becomes thin, so that the ability to suppress diffusion of Cu that the barrier metal should have decreases, and the reliability of the transistor and the like decreases. Further, when a metal such as a barrier metal or Cu enters, insulation resistance such as insulation withstand voltage is reduced, current leakage between adjacent wirings occurs, and reliability of signal propagation by the wiring is reduced.
[0010]
In recent years, it has been studied to reduce the wiring resistance and via resistance by thinning the barrier metal. However, the current mainstream PVD method as a barrier metal formation method has poor coverage, and the film thickness on the side walls of wiring grooves and via holes is still thin at present. Disappear. Therefore, it is required to form a barrier metal by a chemical vapor deposition (CVD) method that can easily form a thin film with high coverage. However, in the case of the CVD method, the deposition of the thin film proceeds by the decomposition reaction on the substrate surface, so that diffusion through the porous holes is more likely to occur than in the PVD method. In this case, the wiring groove of the porous interlayer insulating film In addition, it is essential to prevent diffusion from the holes present on the side surfaces of the via holes.
[0011]
As a countermeasure against the diffusion of the metal, a method of depositing another insulating film and closing the hole after processing the interlayer insulating film has been studied. In addition, when processing an interlayer insulating film, a method of closing a hole opened on a surface in contact with a barrier metal by depositing a by-product generated during the processing on the side surface of a wiring groove or a via hole has been studied (for example, Non-Patent Document 1). However, in this case, there is a possibility that problems such as a substantial increase in dielectric constant and a change in pore size due to the presence of a new substance may occur.
[0012]
On the other hand, a method of closing pores of a porous material by plasma processing using N ₂ plasma has been studied (for example, Non-Patent Document 2). However, as a result of examination by the present inventor of the diffusion preventing effect by the method of closing the hole by N ₂ plasma treatment, it becomes clear that the effect is thin depending on the material of the interlayer insulating film, and diffusion of barrier metal or Cu may occur. It was. Furthermore, when the N ₂ plasma treatment is performed, the dielectric constant may be increased by nitriding the surface of the interlayer insulating film.
[0013]
The present invention has been made based on recognition of such a problem, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing diffusion of wiring materials such as barrier metal and Cu into an interlayer insulating film. It is in.
[0014]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, a step of forming a thin film made of an insulating material on a substrate, a step of opening a hole in the thin film, and a step of forming a plasma of a rare gas There is provided a method of manufacturing a semiconductor device, comprising: exposing to an atmosphere; and depositing a conductive material in the hole.
[0015]
By exposing to a rare gas plasma atmosphere, a modified layer is formed on the surface of the thin film made of an insulating material. This modified layer prevents diffusion of the conductive material formed thereon, and can eliminate the deterioration of the insulating film and various other problems.
[0016]
Further, if the method further comprises a step of heating the thin film after the step of exposing to the plasma atmosphere and before the step of depositing the conductive material, the plasma is insulated by the action of a rare gas plasma. The atoms that have moved on the surface of the conductive material recombined firmly, and it is possible to obtain a further modified layer.
[0017]
In this case, the quality of the modified layer can be improved by heating the thin film to 200 ° C. or higher.
[0018]
Further, by using at least one selected from the group consisting of helium, argon, krypton, and xenon as the rare gas, the formation of the modified layer can be made more reliable.
[0019]
Further, if the step of exposing to the plasma atmosphere is performed under conditions where silicon oxide is etched by 2 nanometers or more, the modified layer can be reliably formed.
[0020]
In addition, if the insulating material is a porous material, its dielectric constant can be lowered, so that it is possible to reduce the parasitic capacitance between wirings while suppressing the diffusion of the conductive material. The semiconductor device can be manufactured.
[0021]
Further, if the conductive material is mainly composed of copper, it is possible to manufacture a semiconductor device with higher performance by lowering the parasitic resistance of wiring and vias.
A method for manufacturing a semiconductor device according to claim 1, wherein:
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0023]
FIG. 1 is a flowchart showing a main part of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
[0024]
2 and 3 are process cross-sectional views showing processes performed corresponding to this flowchart.
That is, in the present invention, formation of an insulating film (step S102), processing of the insulating film (step S104), plasma treatment with a rare gas (step S106), heat treatment (step S108), formation of a barrier metal (step S110), A series of steps of forming the wiring material (step S112) can be performed. However, the heat treatment (step S108) may be omitted. Further, as will be described in detail later, the formation of the barrier metal (step S110) may be omitted depending on the insulating film and the wiring material used.
[0025]
Hereinafter, the embodiment will be specifically described with reference to FIGS. 2 and 3.
[0026]
First, as shown in FIG. 2A, an insulating film 220 is formed on a base body 200 such as a silicon substrate. As a material of the insulating film 220, for example, porous methyl silsesquioxane (MSQ) can be used. As the formation method, for example, a spin on glass (SOG) method in which a thin film is formed by spin-coating a solution and performing heat treatment can be used. A porous insulating film having the following physical property values can be obtained by appropriately adjusting the material and formation conditions of the MSQ.
Density: 0.68 g / cm ³
Porosity: 54%
Maximum value of pore diameter distribution: 1.9 nm
Relative permittivity: 1.81
Elastic modulus: 1.6 GPa
Hardness: 0.1 GPa
After the insulating film 220 is formed, a hole H is then formed as shown in FIG. As a formation method thereof, for example, a resist mask (not shown) may be formed, the exposed insulating film may be etched, and then the resist mask may be removed by a method such as ashing.
[0027]
Thereafter, as shown in FIG. 2C, the insulating film 220 is exposed to the plasma P of a rare gas. For example, argon (Ar) plasma is used and exposed to the plasma P so that the scraping amount is about 2 nanometers or more in terms of silicon oxide (SiO ₂ ). The processing time is approximately several seconds to several tens of seconds although it depends on the density of the plasma P.
[0028]
However, if it is excessively exposed to the plasma P, the insulating film 220 is excessively etched, the film thickness becomes thin, and the diameter of the hole H increases. Therefore, it is desirable that the upper limit of the plasma treatment is within a range where the reduction of the insulating film 220 and the expansion of the hole H are allowed. For example, in the case of the latest semiconductor integrated circuit device, the thickness of the interlayer insulating film 220 is 0.2 to 0.3 micrometers, and the opening diameter of the hole H as a via is about 0.1 micrometers. Therefore, in this case, if the allowable range of change in film thickness and aperture diameter is 10 percent, the upper limit for plasma treatment can be about 15 nanometers in terms of the amount of wear converted to silicon oxide. However, the upper limit of such plasma treatment can be appropriately determined according to the structural parameters of the device to be manufactured, the material of the insulating film, and the like.
[0029]
Now, after performing the plasma treatment in this way, next, heat treatment is performed. Then, as illustrated in FIG. 2D, the modified layer 220 </ b> M is formed on the surface of the interlayer insulating film 220. Since the effect of the plasma P penetrates into the hole H, the modified layer 220M is also formed on the inner wall of the hole H. The heat treatment can be performed, for example, in an inert gas atmosphere at 400 ° C. for about 30 minutes. However, the conditions for the heat treatment can be appropriately determined according to the material of the insulating film 220, the conditions for the plasma treatment, and the like. According to the inventor's trial production, a tendency that a good modified layer 220M is obtained by heat treatment at approximately 200 ° C. or higher is recognized, and the upper limit of the heat treatment temperature is the semiconductor formed on the substrate 200. It can be determined as appropriate in consideration of damage caused by heat of other elements such as an element.
[0030]
Further, the heat treatment may be omitted depending on the material of the insulating film 220, plasma treatment conditions, and the like. That is, it is possible to form the modified layer 220M on the surface of the insulating film 220 only by the plasma treatment shown in FIG.
[0031]
After the modified layer 220M is formed in this way, a barrier metal layer 240 is then deposited as shown in FIG. As a material of the barrier metal, for example, tantalum nitride (TaN) can be used. As the deposition method, for example, vapor layer deposition (ALD) or CVD method may be used. On the other hand, when the physical vapor deposition (PVD) method is used, since the PDV particles have large energy, they may be implanted into the interlayer insulating film 220 and diffuse into the interior. By providing the layer 220M, such diffusion into the film can be suppressed.
[0032]
Thereafter, as shown in FIG. 3B, a wiring layer 260 is deposited. For example, Cu can be used as the material. In order to embed in the hole H, as described above, a Cu thin film is first formed by the PVD method, and Cu can be embedded in the hole H by the plating method using the Cu thin film as a cathode electrode. .
[0033]
Thereafter, the wiring layer 260 and the underlying barrier metal layer 240 deposited on the surface of the insulating film 220 are polished and removed by CMP to complete the buried structure shown in FIG.
[0034]
According to the manufacturing method of the present invention described above, by forming the modified layer 220M on the surface of the interlayer insulating film 220, diffusion of barrier metal and wiring material (Cu) to the interlayer insulating film is surely and easily prevented. be able to.
[0035]
4 to 6 are schematic views for explaining the effect of the modified layer 220M formed in the present invention. That is, FIG. 4 is a cross-sectional view showing a bonding interface between the interlayer insulating film (P-MSQ), the barrier metal layer (BM), and the wiring layer (Cu) when the modified layer 220M is not provided as a comparative example. is there. As illustrated in the figure, holes V are formed in the interlayer insulating film in order to effectively lower the dielectric constant.
[0036]
However, when the porous interlayer insulating film and the barrier metal layer are in direct contact as described above, the barrier metal diffuses into the interlayer insulating film through the pores as shown in FIG. . As a result, the thickness of the barrier metal layer may be reduced, and a continuous thin film state may not be maintained. Then, the metal of the wiring layer (Cu) also diffuses into the interlayer insulating film, and further diffuses into the semiconductor substrate, thereby reducing the reliability of the transistor and the like. In addition, when a metal such as a barrier metal or Cu enters, insulation resistance such as dielectric strength of the interlayer insulating film is reduced, current leakage occurs between adjacent wirings, and reliability of signal propagation by the wiring is reduced. .
[0037]
On the other hand, according to the present invention, by providing the modified layer 220M on the surface of the interlayer insulating film, such diffusion of the barrier metal or wiring material can be prevented.
[0038]
FIG. 6 is a schematic view illustrating a state in which the modified layer 220M is formed by the manufacturing method of the present invention. By forming the modified layer 220M, diffusion of the barrier metal (BM) and the wiring layer material (Cu) to the insulating film 220 is prevented. This is because the plasma treatment causes the movement of atoms on the surface of the interlayer insulating film 220 to close the vacancy V, and the subsequent heat treatment causes a strong bond between the moved atoms and the destination atoms. This is probably because of the formation of That is, it is considered that the diffusion of the barrier metal and the wiring material can be surely prevented by closing the holes V and forming the dense modified layer 220M on the surface.
[0039]
In order to investigate the effects of the plasma treatment and the heat treatment according to the present invention, the inventor made samples subjected to these treatments and samples not subjected to the treatment, and examined the diffusion in the layer.
[0040]
FIG. 7 is a graph showing the diffusion state of elements into the interlayer insulating film in the comparative example in which the plasma treatment and the heat treatment are not performed.
[0041]
FIG. 8 is a graph showing a diffusion state when the plasma treatment and the heat treatment are performed. In these graphs, the horizontal axis represents the distance from the interface between the interlayer insulating film 220 and the barrier metal layer 240, and the vertical axis represents the concentration of each element. Here, the plasma treatment was performed under the condition that the etching amount in terms of SiO ₂ was 2 nm using Ar plasma, and the heat treatment was performed at 400 ° C. for 30 minutes in a nitrogen atmosphere.
[0042]
In any sample, MSQ was used as the interlayer insulating film 220, TaN was used as the barrier metal layer 240, and Cu was used as the wiring layer 260. The thickness of the barrier metal layer 240 was 1 nanometer.
[0043]
In the case of the comparative example shown in FIG. 7, Cu of the wiring material is detected in the range of 10 nanometers from the interface, and the silicon (Si) concentration is correspondingly reduced. That is, it can be seen that the barrier metal diffusion prevention function is greatly reduced.
[0044]
On the other hand, in the case of the sample of the present invention shown in FIG. 8, the Cu concentration sharply decreases at the interface, and almost no diffusion into the insulating film is observed. That is, it can be seen that the barrier metal diffusion preventing function is normally maintained by the action of the modified layer 220M.
[0045]
In the above-described specific example, the treatment using Ar plasma is performed. However, the present invention is not limited to this, and other similar effects can be obtained using plasma of various rare gases. That is, in addition to argon, plasma of helium (He), neon (Ne), krypton (Kr), xenon (Xe), radon (Rn), or the like can be used. In this case, for example, when plasma of an element having a large atomic weight such as krypton or xenon is applied, energy applied to atoms on the surface of the interlayer insulating film 220 is increased, and thus the surface modification effect is considered to be enhanced.
[0046]
In addition, when plasma of an element having a small atomic weight such as helium (He) is used, the energy given to the atoms on the surface of the interlayer insulating film 220 is slightly small. However, for example, when copper (Cu) or the like is exposed as a lower wiring layer at the bottom of the hole H of the interlayer insulating film 220, the lower copper is also sputtered along with the plasma processing. In such a case, when a light element plasma such as helium (He) is used, it is possible to suppress a decrease that the lower layer copper is sputtered and adheres to the side wall of the hole H.
[0047]
Therefore, the gas type of the rare gas used in the plasma treatment in the present invention can be appropriately selected in consideration of the structure of the device to be applied, the formation conditions, and the like.
[0048]
Further, in the specific examples described above, the case where porous MSQ is used as the material of the interlayer insulating film 220 has been described as an example, but the present invention is not limited to this, and the same applies to other various insulating films. The effect is obtained. In particular, when the present invention is applied to a porous low dielectric constant material, a remarkable effect can be obtained as described above. Examples of materials that can be used as the material of the interlayer insulating film 220 in the present invention include various silsesquioxane compounds, polyimide, fluorocarbon, parylene, and benzocyclobutene. An insulating material can be mentioned.
[0049]
In addition to Cu, the material of the wiring layer 260 has the same effect by using a material mainly composed of Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy. can get. Furthermore, the same effect can be obtained by using other metal materials used in the semiconductor industry whose main components are aluminum (Al), tungsten (W), etc., instead of Cu-based materials.
[0050]
On the other hand, as the material of the barrier metal layer 240, in addition to TaN, tungsten nitride (WN), titanium nitride (TiN), tungsten carbonitride (WCN), titanium nitride silicate (TiSiN), tantalum (Ta), etc. Similar effects can be obtained as a multilayer film in which any one of them is laminated.
[0051]
In the case of forming a multilayer wiring structure or the like, the substrate 200 in FIG. 2 and FIG. 3 has a lower wiring layer and an insulating film 220 formed thereon.
[0052]
In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as formation of an etching stopper, photolithography process, cleaning before and after processing are omitted, but it goes without saying that these techniques are included. .
[0053]
9 and 10 are process cross-sectional views showing a manufacturing method according to a modified example of the present invention. In these drawings, the same elements as those described above with reference to FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.
In this modification, in the step shown in FIG. 10A, TaN is deposited by vapor phase atomic layer deposition (ALD or atomic layer chemical vapor deposition: ALCVD method), thereby forming a barrier metal layer. 250 is formed. As described above, when the barrier metal layer is formed by the ALD method, the diffusion into the porous low dielectric constant film becomes remarkable as compared with the PVD method. On the other hand, according to the present invention, by performing plasma treatment in advance and heat treatment as necessary, the modified layer 220 is formed on the surface of the interlayer insulating film 220, thereby effectively diffusing the barrier metal. It becomes possible to stop. As a result, the barrier metal layer 250 can be formed using the ALD method.
[0054]
The ALD method can precisely control the film thickness and can form an extremely thin thin film. In the case of this modification, an ultra-thin barrier metal layer 250 having a thickness of about 0.5 nanometer can be formed. As a result, the barrier metal layer having a relatively high resistance compared to a wiring material such as Cu can be thinned, and the wiring resistance and via resistance can be reduced without lowering the integration density.
[0055]
11 and 12 are process cross-sectional views showing a manufacturing method according to the second modification of the present invention. Also in these drawings, the same elements as those described above with reference to FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description thereof is omitted.
In this modification, the wiring layer 270 is formed by depositing tungsten (W) by the CVD method in the step shown in FIG. That is, the wiring material is directly formed without providing the barrier metal layer. Thereafter, the tungsten layer on the surface of the insulating film 220 is polished and removed by a CMP method to obtain a buried structure as shown in FIG.
[0056]
At present, an interlayer insulating film made of a porous low dielectric constant material is often used corresponding to a Cu wiring. However, in the future, it is considered that a porous low dielectric constant material will also be applied to the tungsten (W) plug. According to the present invention, in such a case, the diffusion of tungsten can be reliably and easily prevented by forming the modified layer 220M.
[0057]
The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.
[0058]
For example, the substrate 200 provided under the interlayer insulating film 220 can have various semiconductor elements or structures not shown. Further, an interlayer insulating film 220 may be further formed on a wiring structure having an interlayer insulating film and a wiring layer instead of the semiconductor substrate.
[0059]
Further, as for the film thickness of the interlayer insulating film and the size, shape, number, etc. of the holes H, those required in the semiconductor integrated circuit and various semiconductor elements can be appropriately selected and used.
[0060]
In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.
[0061]
【The invention's effect】
As described above, according to the present invention, the diffusion of the barrier metal and the wiring material to the interlayer insulating film can be reliably and easily prevented by the plasma treatment using the rare gas plasma. As a result, a porous low dielectric constant material can be used stably as a material for the interlayer insulating film, and a high-performance and highly integrated semiconductor device with reduced parasitic capacitance between wirings can be realized. Industrial benefits are tremendous.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a main part of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a process cross-sectional view illustrating a process performed corresponding to the flowchart of FIG.
3 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 1. FIG.
FIG. 4 is a cross-sectional view illustrating a bonding interface between an interlayer insulating film (P-MSQ), a barrier metal layer (BM), and a wiring layer (Cu) when a modified layer 220M is not provided as a comparative example.
FIG. 5 is a schematic diagram showing a state in which a barrier metal is diffused into an interlayer insulating film through a hole in a comparative example.
FIG. 6 is a schematic view illustrating a state in which a modified layer 220M is formed by the manufacturing method of the present invention.
FIG. 7 is a graph showing the diffusion state of elements into an interlayer insulating film in a comparative example in which plasma treatment and heat treatment are not performed.
FIG. 8 is a graph showing a diffusion state when a plasma treatment and a heat treatment are performed.
FIG. 9 is a process cross-sectional view illustrating a manufacturing method according to a modified example of the present invention.
FIG. 10 is a process cross-sectional view illustrating a manufacturing method according to a modified example of the present invention.
FIG. 11 is a process cross-sectional view illustrating a manufacturing method according to a second modification of the present invention.
FIG. 12 is a process cross-sectional view illustrating a manufacturing method according to a second modification of the present invention.
FIG. 13 is a process cross-sectional view illustrating a main part of the damascene method.
[Explanation of symbols]
200 Base 220 Interlayer Insulating Film 220M Modified Layer 240, 250 Barrier Metal Layer 260, 270 Wiring Layer H Hole P Plasma V Void

Claims (7)

Forming a thin film made of an insulating material on a substrate;
Opening a hole in the thin film;
Exposing the thin film to a rare gas plasma atmosphere;
Depositing a conductive material in the holes;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of heating the thin film after the step of exposing to the plasma atmosphere and before the step of depositing the conductive material. . The method of manufacturing a semiconductor device according to claim 2, wherein the thin film is heated to 200 ° C. or more. The method for manufacturing a semiconductor device according to claim 1, wherein at least one selected from the group consisting of helium, argon, krypton, and xenon is used as the rare gas. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing to the plasma atmosphere is performed under a condition in which silicon oxide is etched by 2 nanometers or more. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating material is a porous material. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive material contains copper as a main component.

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