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JP2005079144A - Multilayer wiring board and probe card - Google Patents

Multilayer wiring board and probe card Download PDF

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Publication number
JP2005079144A
JP2005079144A JP2003304514A JP2003304514A JP2005079144A JP 2005079144 A JP2005079144 A JP 2005079144A JP 2003304514 A JP2003304514 A JP 2003304514A JP 2003304514 A JP2003304514 A JP 2003304514A JP 2005079144 A JP2005079144 A JP 2005079144A
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thin film
semiconductor element
wiring
layer
sub
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Hitoshi Tega
仁 手賀
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Kyocera Corp
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    • H10W70/655
    • H10W90/724

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

【課題】 半導体素子に供給する副電源の電気特性の優れた、電気的な検査を行なうためのプローブカードに使用される多層配線基板を提供すること。
【解決手段】 絶縁層の層間に配線導体層2が形成されたベース基板1と、樹脂絶縁層16が複数積層されて成るとともに樹脂絶縁層16の層間に薄膜配線層15が形成された薄膜多層部12と、薄膜多層部12の表面に形成された、薄膜配線層15および半導体素子7の電極に電気的に接続されて半導体素子7の電気的接続を検査するための複数の電極パッド3と、ベース基板1の主面に形成されて電極パッド3、薄膜配線層15および配線導体層2を電気的に接続する複数の接続パッド13とを具備しており、複数の接続パッド13は複数の副電源用接続パッド4a,4b,4c,4dから成る副電源用接続パッド群4を複数群含み、副電源用接続パッド群4は半導体素子の外周部直下に位置するようにそれぞれ配置されている。
【選択図】 図1
PROBLEM TO BE SOLVED: To provide a multilayer wiring board used for a probe card for performing an electrical inspection, which is excellent in electrical characteristics of a sub power source supplied to a semiconductor element.
A base substrate 1 having a wiring conductor layer 2 formed between insulating layers and a thin film multilayer in which a plurality of resin insulating layers 16 are stacked and a thin film wiring layer 15 is formed between resin insulating layers 16. A plurality of electrode pads 3 formed on the surface of the thin film multilayer portion 12 and electrically connected to the thin film wiring layer 15 and the electrode of the semiconductor element 7 to inspect the electrical connection of the semiconductor element 7; And a plurality of connection pads 13 which are formed on the main surface of the base substrate 1 and electrically connect the electrode pad 3, the thin film wiring layer 15 and the wiring conductor layer 2. A plurality of sub-power supply connection pad groups 4 including sub-power supply connection pads 4a, 4b, 4c, and 4d are included, and the sub-power supply connection pad group 4 is disposed so as to be located immediately below the outer peripheral portion of the semiconductor element. .
[Selection] Figure 1

Description

本発明は、半導体素子等の電気的な検査をするためのプローブカードに使用される多層配線基板に関する。   The present invention relates to a multilayer wiring board used in a probe card for electrical inspection of semiconductor elements and the like.

従来、半導体素子を電気的に検査する場合において、一般的にカンチレバー方式と呼ばれる針状のプローブ用電極パッドを具備するプローブカードを半導体素子の電極パッドに接続して検査する方法で行われてきた。しかし、近年になって、半導体素子の高集積化と処理信号数の増加にともない、半導体素子の電極パッドは多ピン化と狭ピッチ化が進んでおり、カンチレバー方式のプローブカードではプローブ用電極パッドを狭ピッチ化しかつ多数配置することが困難なため、検査方法は、垂直針状のプローブを細密に配置した垂直型のプローブカードによる方法に移り変わってきている。   Conventionally, when a semiconductor element is electrically inspected, a probe card having a needle-like probe electrode pad, generally called a cantilever method, is connected to the electrode pad of the semiconductor element and inspected. . However, in recent years, with the high integration of semiconductor elements and the increase in the number of processing signals, the electrode pads of semiconductor elements have become increasingly multi-pin and narrow pitched. In the cantilever type probe card, the probe electrode pad Since it is difficult to narrow the pitch and arrange a large number, the inspection method has been changed to a method using a vertical probe card in which vertical needle-like probes are finely arranged.

図4に垂直型のプローブカードの模式的な断面図を示す。図4において、101はベース基板、103はプローブ用電極パッド、107は半導体素子、108は半導体素子107の電極、109は中継基板、110は垂直型のプローブ、111は多層配線基板、112は薄膜多層部、113は接続パッド、114は外部接続用電極パッドである。   FIG. 4 shows a schematic sectional view of a vertical probe card. In FIG. 4, 101 is a base substrate, 103 is a probe electrode pad, 107 is a semiconductor element, 108 is an electrode of the semiconductor element 107, 109 is a relay board, 110 is a vertical probe, 111 is a multilayer wiring board, and 112 is a thin film The multilayer portion, 113 is a connection pad, and 114 is an external connection electrode pad.

垂直型のプローブカードは、樹脂等から成る中継基板109上に、多層配線基板111が配設され、さらにその上に垂直針状の垂直型のプローブ110が配設されている。検査対象の半導体素子107の電極108と垂直型のプローブ110が接続することで半導体素子107の電気的検査が行われる。なお、垂直型のプローブ110の代わりに異方導電性ゴム等が用いられる場合もある。また、半導体素子107の電極108は、半導体素子を駆動するための主電源用電極、グランド用電極、シグナル用電極および副電源用電極(アナログ回路用電源やシグナルの入出力用電源等)によって構成される。   In the vertical probe card, a multilayer wiring substrate 111 is disposed on a relay substrate 109 made of resin or the like, and a vertical needle-shaped vertical probe 110 is disposed thereon. The electrical inspection of the semiconductor element 107 is performed by connecting the electrode 108 of the semiconductor element 107 to be inspected and the vertical probe 110. Note that anisotropic conductive rubber or the like may be used instead of the vertical probe 110. The electrode 108 of the semiconductor element 107 is constituted by a main power supply electrode, a ground electrode, a signal electrode, and a sub power supply electrode (an analog circuit power supply, a signal input / output power supply, etc.) for driving the semiconductor element. Is done.

一般的に電気的特性を考えると、多層配線基板111の副電源は伝送線路の配線抵抗が高いと、入力波形が伝送線路から出力される際に減衰するため、配線抵抗が低い方が良い。また、伝送線路の配線のインダクタンスが大きいと入力波形の立ち上がり部、立ち下り部に対応する出力波形にスパイク状のノイズを生じる。   In general, considering the electrical characteristics, the sub-power supply of the multilayer wiring substrate 111 is preferably low in wiring resistance because if the wiring resistance of the transmission line is high, the input waveform is attenuated when output from the transmission line. If the inductance of the transmission line wiring is large, spike-like noise is generated in the output waveform corresponding to the rising and falling portions of the input waveform.

多層配線基板111は、絶縁層が複数積層されて成るとともに絶縁層の層間に配線導体層が形成された、アルミナセラミックス、窒化アルミニウムセラミックス等のセラミックスから成るベース基板101の主面上に、エポキシ樹脂やポリイミド樹脂等から成り、スピンコート法等によって樹脂の前駆体を塗布し加熱硬化させることによって形成される樹脂絶縁層が複数積層されて成るとともに、樹脂絶縁層の層間に銅やアルミニウム等の金属から成り、めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィー技術を採用することによって形成される薄膜配線層が形成された薄膜多層部112を具備し、その薄膜多層部112の表層には垂直型のプローブ110との接続用にプローブ用電極パッド103が形成されている。また、中継基板109との接続のためにベース基板101の下面には外部接続用電極パッド114が形成され、これらのプローブ用電極パッド103と外部接続用電極パッド114とはベース基板101と薄膜多層部112の界面に存在する接続パッド113で接続されている。   The multilayer wiring board 111 is formed of an epoxy resin on the main surface of a base substrate 101 made of ceramics such as alumina ceramics or aluminum nitride ceramics, in which a plurality of insulating layers are laminated and a wiring conductor layer is formed between the insulating layers. In addition, a plurality of resin insulation layers are formed by applying a resin precursor by spin coating, etc. and heat-curing, and a metal such as copper or aluminum between the resin insulation layers. A thin film multilayer portion 112 formed with a thin film wiring layer formed by employing a thin film forming technique such as a plating method or a vapor deposition method and a photolithography technique, and the surface layer of the thin film multilayer portion 112 is perpendicular to the surface layer. A probe electrode pad 103 is formed for connection to the probe 110 of the mold. Further, external connection electrode pads 114 are formed on the lower surface of the base substrate 101 for connection to the relay substrate 109. The probe electrode pads 103 and the external connection electrode pads 114 are formed of the base substrate 101 and the thin film multilayer. The connection pads 113 existing at the interface of the parts 112 are connected.

しかし、最近では半導体素子107の開発期間が非常に短縮されてきており、その電気検査に用いられるプローブカードも短納期対応が必須となっている。上記の垂直型のプローブカードは多ピン化と狭ピッチ化に優れているものの、カンチレバー方式に対して、製造納期が長くなるという問題がある。   However, recently, the development period of the semiconductor element 107 has been greatly shortened, and the probe card used for the electrical inspection is also required to meet the short delivery date. Although the above-mentioned vertical type probe card is excellent in increasing the number of pins and narrowing the pitch, there is a problem that the manufacturing delivery time is longer than that of the cantilever type.

垂直型のプローブカードに用いられる多層配線基板111は、検査対象である半導体素子107の電極108のレイアウトを元に設計を行ない、半導体素子107の設計完了後に多層配線基板111の設計を行ない、配線導体パターンとビアホールを形成したセラミックス等から成る絶縁層を積層して高温で焼成することでベース基板101を作製し、その後、そのベース基板101上に、下層から1層ずつ薄膜配線導体パターンおよび有機樹脂から成る絶縁層を積層し、ビアホールを形成することで薄膜多層部112を作製する必要がある。そのために製造納期が非常に長くなってしまうのである。   The multilayer wiring board 111 used for the vertical probe card is designed based on the layout of the electrodes 108 of the semiconductor element 107 to be inspected, and the multilayer wiring board 111 is designed after the design of the semiconductor element 107 is completed. A base substrate 101 is manufactured by laminating a conductive pattern and an insulating layer made of ceramics or the like in which a via hole is formed and firing at a high temperature. Thereafter, a thin film wiring conductor pattern and an organic layer are formed on the base substrate 101 one by one from the lower layer. It is necessary to produce the thin film multilayer portion 112 by laminating an insulating layer made of resin and forming a via hole. As a result, the production delivery time becomes very long.

そこで、これらの多層配線基板111の製造納期を短縮し、かつ安価に製造するために、多層配線基板111のべース基板101を多品種に共通で使用できるように共通化が図られ、半導体素子107の設計を開始する前にベース基板101を作製しておいて、ベース基板101の作製時間を削減することができるような工夫が行なわれている。   Therefore, in order to shorten the manufacturing delivery time of these multilayer wiring boards 111 and to manufacture them at low cost, the multilayered wiring board 111 is made common so that the base board 101 of the multilayer wiring board 111 can be commonly used for various types of semiconductors. The base substrate 101 is manufactured before the design of the element 107 is started, and an effort is made to reduce the manufacturing time of the base substrate 101.

図5は従来の多層配線基板111の例を示す平面図である。図5において、101はベース基板、107は半導体素子、103はプローブ用電極パッド、104aは副電源用接続パッド(A)、105はシグナル配線、106は副電源用接続配線、112は薄膜多層部を示す。   FIG. 5 is a plan view showing an example of a conventional multilayer wiring board 111. In FIG. 5, 101 is a base substrate, 107 is a semiconductor element, 103 is a probe electrode pad, 104a is a sub power connection pad (A), 105 is a signal wiring, 106 is a sub power connection wiring, and 112 is a thin film multi-layer part. Indicates.

副電源用接続パッド(A)104aはベース基板101の表面にプレーン形状の配線導体層を有するものであるが、半導体素子107の電極108のパッドレイアウトが半導体素子107毎に全く異なるため、副電源用接続配線106は電極パッドと同様に、ベース基板101表面の副電源用接続パッド(A)104aから他のシグナル配線105と同様に結線されていた。
特開2002−76073号公報
The sub power connection pad (A) 104a has a plain wiring conductor layer on the surface of the base substrate 101, but the pad layout of the electrodes 108 of the semiconductor element 107 is completely different for each semiconductor element 107. Similarly to the electrode pads, the connection wiring 106 is connected from the sub power connection pad (A) 104a on the surface of the base substrate 101 in the same manner as the other signal wirings 105.
JP 2002-76073 A

しかしながら、半導体素子107の副電源用接続配線106は配線幅が細く、配線長が長くなるので、配線抵抗が大きく、インダクタンスも大きくなり、その結果、副電源の伝送線路にノイズが発生するとともに電気特性も良くないという問題点があった。   However, the sub-power supply connection wiring 106 of the semiconductor element 107 has a narrow wiring width and a long wiring length, so that the wiring resistance increases and the inductance also increases. As a result, noise is generated in the transmission line of the sub-power supply and the electric power is increased. There was a problem that the characteristics were not good.

従って、本発明は上記従来の問題点に鑑みて完成されたものであり、その目的は、製造納期を短縮することができ、副電源用接続配線の電気特性を向上させた高性能の多層配線基板とそれを用いたプローブカードを提供することにある。   Therefore, the present invention has been completed in view of the above-mentioned conventional problems, and its purpose is to reduce the manufacturing delivery time and to improve the electrical characteristics of the sub power connection wiring. It is to provide a substrate and a probe card using the substrate.

本発明の多層配線基板は、絶縁層が複数積層されて成るとともに、前記絶縁層の層間に配線導体層が形成されたベース基板と、このベース基板の主面に積層された、樹脂絶縁層が複数積層されて成るとともに前記樹脂絶縁層の層間に薄膜配線層が形成された薄膜多層部と、この薄膜多層部の表面に形成された、前記薄膜配線層および半導体素子の電極に電気的に接続されて前記半導体素子の電気的接続を検査するための複数の電極パッドと、前記ベース基板の主面に形成されて前記電極パッド、前記薄膜配線層および前記配線導体層を電気的に接続する複数の接続パッドとを具備しており、前記複数の接続パッドは複数の副電源用接続パッドから成る副電源用接続パッド群を複数群含み、前記副電源用接続パッド群は前記半導体素子の外周部直下に位置するようにそれぞれ配置されていることを特徴とするものである。   The multilayer wiring board of the present invention comprises a base substrate in which a plurality of insulating layers are laminated, a wiring conductor layer formed between the insulating layers, and a resin insulating layer laminated on the main surface of the base substrate. A thin film multi-layer part in which a plurality of layers are formed and a thin film wiring layer is formed between the resin insulating layers, and is electrically connected to the thin film wiring layer and the electrode of the semiconductor element formed on the surface of the thin film multi-layer part A plurality of electrode pads for inspecting electrical connection of the semiconductor element, and a plurality of electrode pads formed on the main surface of the base substrate to electrically connect the electrode pads, the thin film wiring layer, and the wiring conductor layer. The plurality of connection pads include a plurality of sub power supply connection pad groups each including a plurality of sub power connection pads, and the sub power connection pad group is an outer peripheral portion of the semiconductor element. And it is characterized in that it is arranged so as to be positioned below.

また、本発明のプローブカードは、本発明の多層配線基板と、前記電極パッド上に接続されたプローブと、前記ベース基板の他の主面に形成されるとともに前記接続パッドに電気的に接続されている外部接続用電極パッドと、一端が前記外部接続用電極パッドに電気的に接続されるとともに他端が前記半導体素子の検査装置に電気的に接続される配線層が形成された中継基板とを具備したことを特徴とするものである。   In addition, the probe card of the present invention is formed on the other main surface of the multilayer wiring board of the present invention, the probe connected on the electrode pad, and the base substrate, and is electrically connected to the connection pad. An external connection electrode pad, and a relay substrate formed with a wiring layer having one end electrically connected to the external connection electrode pad and the other end electrically connected to the semiconductor device inspection apparatus. It is characterized by comprising.

本発明の多層配線基板によれば、絶縁層が複数積層されて成るとともに、絶縁層の層間に配線導体層が形成されたベース基板と、ベース基板の主面に積層された、樹脂絶縁層が複数積層されて成るとともに樹脂絶縁層の層間に薄膜配線層が形成された薄膜多層部と、薄膜多層部の表面に形成された、薄膜配線層および半導体素子の電極に電気的に接続されて半導体素子の電気的接続を検査するための複数の電極パッドと、ベース基板の主面に形成されて電極パッド、薄膜配線層および配線導体層を電気的に接続する複数の接続パッドとを具備しており、複数の接続パッドは複数の副電源用接続パッドから成る副電源用接続パッド群を複数群含み、副電源用接続パッド群は半導体素子の外周部直下に位置するようにそれぞれ配置されていることより、副電源用の電極パッドと副電源接続パッドを接続する配線幅を太く、かつ配線長を短くできることから、副電源電力供給の電気特性に優れた、電気的な検査を行なうためのプローブカードに使用される多層配線基板を提供することができる。   According to the multilayer wiring board of the present invention, a plurality of insulating layers are laminated, a base substrate in which a wiring conductor layer is formed between the insulating layers, and a resin insulating layer laminated on the main surface of the base substrate. A thin film multilayer part in which a plurality of layers are formed and a thin film wiring layer is formed between resin insulation layers, and a semiconductor that is electrically connected to the thin film wiring layer and the electrode of the semiconductor element formed on the surface of the thin film multilayer part A plurality of electrode pads for inspecting the electrical connection of the element; and a plurality of connection pads formed on the main surface of the base substrate to electrically connect the electrode pads, the thin film wiring layer and the wiring conductor layer. The plurality of connection pads include a plurality of sub-power supply connection pad groups each including a plurality of sub-power supply connection pads, and the sub-power supply connection pad groups are respectively disposed so as to be located immediately below the outer peripheral portion of the semiconductor element. about Probe card for electrical inspection with excellent electrical characteristics of sub-power supply because the wiring width connecting the electrode pad for the sub-power supply and the sub-power supply connection pad is wide and the wiring length can be shortened A multilayer wiring board used in the above can be provided.

また、本発明のプローブカードによれば、本発明の多層配線基板を具備したことにより、精度の高い電気検査を実施することができるプローブカードを提供することができる。   In addition, according to the probe card of the present invention, it is possible to provide a probe card capable of performing an electrical test with high accuracy by including the multilayer wiring board of the present invention.

本発明の多層配線基板を添付図面に基づき詳細に説明する。図1は本発明の多層配線基板の実施の形態の一例を示す平面図である。図1において、1はベース基板、7は半導体素子、3はプローブ接続用の電極パッド、4は副電極用接続パッド群、4aは副電源用接続パッド(A)、4bは副電源用接続パッド(B)、4cは副電源用接続パッド(C)、4dは副電源用接続パッド(D)、5はシグナル配線、6は副電源用接続配線、12は薄膜多層部である。   The multilayer wiring board of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a plan view showing an example of an embodiment of a multilayer wiring board according to the present invention. In FIG. 1, 1 is a base substrate, 7 is a semiconductor element, 3 is an electrode pad for probe connection, 4 is a sub-electrode connection pad group, 4a is a sub-power connection pad (A), and 4b is a sub-power connection pad. (B) 4c is a sub-power connection pad (C), 4d is a sub-power connection pad (D), 5 is a signal wiring, 6 is a sub-power connection wiring, and 12 is a thin film multilayer section.

本発明の多層配線基板11は、絶縁層が複数積層されて成るとともに、絶縁層の層間に配線導体層2が形成されたベース基板1と、ベース基板1の主面に積層された、樹脂絶縁層16が複数積層されて成るとともに樹脂絶縁層16の層間に薄膜配線層15が形成された薄膜多層部12と、薄膜多層部12の表面に形成された、薄膜配線層15および半導体素子7の電極8に電気的に接続されて半導体素子7の電気的接続を検査するための複数の電極パッド3と、ベース基板1の主面に形成されて電極パッド3、薄膜配線層15および配線導体層2を電気的に接続する複数の接続パッド13とを具備しており、複数の接続パッド13は複数の副電源用接続パッド4a,4b,4c,4dから成る副電源用接続パッド群4を複数群含み、副電源用接続パッド群4は半導体素子7の外周部直下に位置するようにそれぞれ配置されている。なお、図1においては複数の副電源用接続パッドとして4つの副電源用接続パッド4a,4b,4c,4dを示しているが、副電源用接続パッドの個数は何個であってもよい。副電源用接続パッド群4の数も4群に限られることはない。   The multilayer wiring board 11 of the present invention comprises a base substrate 1 in which a plurality of insulating layers are laminated and a wiring conductor layer 2 is formed between the insulating layers, and a resin insulation laminated on the main surface of the base substrate 1. A thin film multilayer portion 12 in which a plurality of layers 16 are laminated and a thin film wiring layer 15 is formed between the resin insulation layers 16, and the thin film wiring layer 15 and the semiconductor element 7 formed on the surface of the thin film multilayer portion 12. A plurality of electrode pads 3 that are electrically connected to the electrodes 8 to inspect the electrical connection of the semiconductor element 7, and the electrode pads 3, the thin-film wiring layer 15 and the wiring conductor layer that are formed on the main surface of the base substrate 1 And a plurality of connection pads 13 for electrically connecting two, the plurality of connection pads 13 includes a plurality of sub-power supply connection pad groups 4 including a plurality of sub-power supply connection pads 4a, 4b, 4c, 4d. Sub power supply connection pad group 4 includes semiconductor elements It is arranged so as to be located immediately below the outer peripheral portion of the. In FIG. 1, four sub power connection pads 4a, 4b, 4c, and 4d are shown as a plurality of sub power connection pads. However, the number of sub power connection pads may be any number. The number of sub-power supply connection pad groups 4 is not limited to four.

本発明の多層配線基板11によれば、ベース基板1の主面に形成された副電源用接続パッド群4を半導体素子7の外周部直下に位置するように配置することにより、半導体素子7の電極8のパッドレイアウトが半導体素子7毎に全く異なっており半導体素子7の副電源用電極がどの位置にあったとしても、半導体素子7の外周部直下にあることから、半導体素子7の副電源用電極と副電源用接続パッド4a,4b,4c,4dとの間の距離が小さくなり、副電源用接続配線6の配線長を短くかつ配線幅を太くすることができる。これにより、副電源用接続配線6の配線抵抗やインダクタンスを小さくすることができ、半導体素子7に副電源電力を供給する電気特性に優れた多層配線基板11を提供することができる。   According to the multilayer wiring board 11 of the present invention, the sub-power supply connection pad group 4 formed on the main surface of the base substrate 1 is arranged so as to be located immediately below the outer peripheral portion of the semiconductor element 7. Since the pad layout of the electrode 8 is completely different for each semiconductor element 7 and the sub power supply electrode of the semiconductor element 7 is located at any position, the sub power supply of the semiconductor element 7 is located immediately below the outer peripheral portion of the semiconductor element 7. The distance between the electrode for power supply and the sub power supply connection pads 4a, 4b, 4c, 4d can be reduced, and the wiring length of the sub power connection wiring 6 can be shortened and the wiring width can be increased. As a result, the wiring resistance and inductance of the sub power supply connection wiring 6 can be reduced, and the multilayer wiring board 11 having excellent electrical characteristics for supplying the sub power supply power to the semiconductor element 7 can be provided.

なお、副電源用接続パッド群4の複数の副電源用接続パッド4a,4b,4c,4dのうち、半導体素子7に近いものから順に副電源用接続パッド4a,4b,4c,4dに使用頻度の高い順に優先順位をつけて配置をしておくと良い。図1のように、副電源用接続パッド(A)4a、副電源用接続パッド(B)4b、副電源用接続パッド(C)4c、副電源用接続パッド(D)4dの順に優先順位を設けておくと、最優先すべき副電源用接続配線6の配線長および太さを、他の副電源用接続パッドに接続される副電源用接続配線6より短く、かつ太くすることができるため、副電源用接続配線6の配線抵抗やインダクタンスを小さくすることができ、半導体素子7に安定した副電源電力を提供することができる。   Of the plurality of sub-power supply connection pads 4a, 4b, 4c, 4d in the sub-power supply connection pad group 4, the frequency of use of the sub-power supply connection pads 4a, 4b, 4c, 4d in order from the one closest to the semiconductor element 7 It is good to place them in order of priority in descending order. As shown in FIG. 1, the sub power connection pad (A) 4a, the sub power connection pad (B) 4b, the sub power connection pad (C) 4c, and the sub power connection pad (D) 4d are prioritized in this order. If provided, the wiring length and thickness of the sub power connection wiring 6 that should be given the highest priority can be made shorter and thicker than the sub power connection wiring 6 connected to other sub power connection pads. The wiring resistance and inductance of the sub power connection wiring 6 can be reduced, and stable power of the sub power can be provided to the semiconductor element 7.

半導体素子7の副電源用電極は、半導体素子7全体を作動させる主電源よりも低い電圧を供給する副電源用の電極であって、半導体素子7の回路中の一部の回路、例えばアナログ回路やシグナルの入出力回路、メモリー回路等の個別の回路に電力を供給する電源用の電極であり、それぞれの回路の駆動電圧に応じて必要な電圧を供給するために設けられている。   The sub power supply electrode of the semiconductor element 7 is a sub power supply electrode for supplying a voltage lower than the main power supply for operating the entire semiconductor element 7, and is a part of the circuit of the semiconductor element 7, for example, an analog circuit. And power supply electrodes for supplying power to individual circuits such as signal input / output circuits and memory circuits, and are provided to supply necessary voltages according to the driving voltages of the respective circuits.

図2は本発明の多層配線基板11のA−A’線における断面を示す断面図である。図2において、1はベース基板、2は配線導体層、12は薄膜多層部、15は薄膜配線層、16は樹脂絶縁層、17は薄膜多層部のビアホールを示す。   FIG. 2 is a sectional view showing a section taken along line A-A 'of the multilayer wiring board 11 of the present invention. In FIG. 2, 1 is a base substrate, 2 is a wiring conductor layer, 12 is a thin film multilayer part, 15 is a thin film wiring layer, 16 is a resin insulating layer, and 17 is a via hole in the thin film multilayer part.

ベース基板1は絶縁層が複数積層されて成るとともに絶縁層の層間に配線導体層2が形成されている。また、ベース基板1の主面には薄膜配線層15および配線導体層2を電気的に接続する複数の接続パッド13や接続パッド13の一部をなす複数の副電源用接続パッド4a,4b,4c,4dを具備しており、他の主面には配線導体層2を介して接続パッド13に電気的に接続されている外部接続用電極パッド14が形成されている。   The base substrate 1 is formed by laminating a plurality of insulating layers, and a wiring conductor layer 2 is formed between the insulating layers. Further, on the main surface of the base substrate 1, a plurality of connection pads 13 for electrically connecting the thin film wiring layer 15 and the wiring conductor layer 2 and a plurality of sub-power supply connection pads 4a, 4b forming a part of the connection pad 13 are provided. 4c and 4d are provided, and external connection electrode pads 14 electrically connected to the connection pads 13 via the wiring conductor layer 2 are formed on the other main surface.

ベース基板1は、酸化アルミニウム質焼結体,ムライト質焼結体等の酸化物系セラミックス、あるいは表面に酸化物膜を有する窒化アルミニウム質焼結体,炭化珪素質焼結体等の非酸化物系セラミックス、さらにはガラス繊維から成る基材にエポキシ樹脂を含浸させたガラスエポキシ樹脂やガラス繊維から成る基材にビスマレイミドトリアジン樹脂を含浸させたもの等の電気絶縁材料から成る。ベース基板1が、例えば、酸化アルミニウム質焼結体から成る場合であれば、アルミナ,シリカ,カルシア,マグネシア等の原料粉末に適当な有機溶剤,溶媒を添加混合して泥漿状となすとともにこれをドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート(セラミック生シート)を形成し、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施し所定形状となすとともにこれらセラミックグリーンシートを積層し、高温(約1600℃)で焼成することによって製作される。あるいは、アルミナ等の原料粉末に適当な有機溶剤,溶媒を添加混合して原料粉末を調製するとともにこの原料粉末をプレス成形機によって所定形状に成形し、最後にこの成形体を高温(約1600℃)で焼成することによってもよい。また、ベース基板1がガラスエポキシ樹脂から成る場合は、例えばガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって製作される。   The base substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-oxide such as an aluminum nitride sintered body having an oxide film on its surface or a silicon carbide sintered body. Further, it is made of an electrically insulating material such as a glass ceramic resin obtained by impregnating a glass fiber base material with an epoxy resin or a glass fiber base material impregnated with a bismaleimide triazine resin. If the base substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with raw material powders such as alumina, silica, calcia, and magnesia to form a slurry. A ceramic green sheet (ceramic green sheet) is formed by adopting a doctor blade method or a calender roll method. After that, an appropriate punching process is performed on the ceramic green sheet to obtain a predetermined shape, and these ceramic green sheets are laminated. Manufactured by firing at high temperature (about 1600 ° C). Alternatively, a raw material powder is prepared by adding an appropriate organic solvent and solvent to a raw material powder such as alumina, and the raw material powder is formed into a predetermined shape by a press molding machine. Finally, the compact is heated to a high temperature (about 1600 ° C). ) May be fired. Further, when the base substrate 1 is made of glass epoxy resin, for example, it is manufactured by impregnating a base material made of glass fiber with an epoxy resin precursor and thermosetting the epoxy resin precursor at a predetermined temperature.

ベース基板1の配線導体層2や接続パッド13、複数の副電源用接続パッド4a,4b,4c,4d、外部接続用電極パッド14はセラミックグリーンシートの所定位置にメタライズ層を被着形成することによって形成される。メタライズ層はタングステンやモリブデン,マンガン等の高融点金属から成り、これら金属の粉末に有機溶剤,溶媒を添加混合した金属ペーストをそれぞれセラミックグリーンシートの所定位置に従来周知のスクリーン印刷法等により所定パターンに被着形成させておき、セラミックグリーンシートと同時に焼成することにより形成される。なお、副電源用接続パッド4a,4b,4c,4dと外部接続用電極パッド14とは、ベース基板1に形成されたビアホール等の貫通導体によって電気的に接続されている。   The metal conductor layer 2 and the connection pads 13 of the base substrate 1, the plurality of sub-power supply connection pads 4a, 4b, 4c and 4d, and the external connection electrode pads 14 are formed by depositing a metallized layer at predetermined positions on the ceramic green sheet. Formed by. The metallized layer is made of a refractory metal such as tungsten, molybdenum, or manganese, and a metal paste obtained by adding an organic solvent and a solvent to the metal powder is mixed in a predetermined pattern on the ceramic green sheet by a conventionally known screen printing method. It is formed by being deposited on and fired simultaneously with the ceramic green sheet. The sub-power supply connection pads 4a, 4b, 4c, 4d and the external connection electrode pads 14 are electrically connected by through conductors such as via holes formed in the base substrate 1.

さらに、このベース基板1の主面に樹脂絶縁層16が複数積層されて成るとともに樹脂絶縁層16の層間に薄膜配線層15が形成された薄膜多層部12が形成される。薄膜多層部12の樹脂絶縁層16は上下に位置する薄膜配線層15を電気的に絶縁し、薄膜配線層15は電気信号を伝達するための伝達路として機能する。また、薄膜多層部の表面には薄膜配線層15に電気的に接続され、半導体素子7の電極8に接続される電極パッド3が形成される。   Further, a thin film multilayer portion 12 is formed in which a plurality of resin insulation layers 16 are laminated on the main surface of the base substrate 1 and a thin film wiring layer 15 is formed between the resin insulation layers 16. The resin insulating layer 16 of the thin film multilayer portion 12 electrically insulates the thin film wiring layer 15 positioned above and below, and the thin film wiring layer 15 functions as a transmission path for transmitting an electric signal. In addition, an electrode pad 3 is formed on the surface of the thin film multilayer portion so as to be electrically connected to the thin film wiring layer 15 and connected to the electrode 8 of the semiconductor element 7.

配線多層部12の樹脂絶縁層16は絶縁フィルム層と絶縁性接着剤層とから構成されており、絶縁フィルム層はポリイミド樹脂,ポリフェニレンサルファイド樹脂,全芳香族ポリエステル樹脂,フッ素樹脂等から成る。また、絶縁性接着剤層はポリアミドイミド樹脂,シロキサン変性ポリイミド樹脂,シロキサン変性ポリアミドイミド,ビスマレイミドトリアジン樹脂,エポキシ樹脂等から成る。薄膜多層部12の樹脂絶縁層16は、例えば、まず12.5乃至50μm程度の絶縁フィルム層に絶縁性接着剤をドクターブレード法等を用いて乾燥厚みで5乃至20μm程度に塗布し乾燥させたものを準備し、これをベース基板1や下層の樹脂絶縁層16の上面に下面が絶縁性接着剤層となるように積み重ね、加熱プレス装置を用いて加熱加圧し接着することによって形成される。   The resin insulating layer 16 of the wiring multilayer portion 12 is composed of an insulating film layer and an insulating adhesive layer, and the insulating film layer is made of polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, fluorine resin, or the like. The insulating adhesive layer is made of polyamideimide resin, siloxane-modified polyimide resin, siloxane-modified polyamideimide, bismaleimide triazine resin, epoxy resin, or the like. For example, the resin insulating layer 16 of the thin film multilayer portion 12 is obtained by applying an insulating adhesive to an insulating film layer of about 12.5 to 50 μm to a dry thickness of about 5 to 20 μm using a doctor blade method or the like and then drying it. This is prepared by stacking the upper surfaces of the base substrate 1 and the lower resin insulating layer 16 so that the lower surface becomes an insulating adhesive layer, and applying heat and pressure using a hot press device.

薄膜多層部12の樹脂絶縁層16の層間に形成される薄膜配線層15は、銅,金,アルミニウム,ニッケル,クロム,モリブデン,チタンおよびそれらの合金等の金属材料から成り、これらをスパッタリング法,蒸着法,めっき法等の薄膜形成技術を採用することによって形成する。薄膜多層部12の薄膜導体層15の形成方法は、例えば、まず薄膜多層部12の樹脂絶縁層16の表面に広面積に、銅層を主体としこの銅層の少なくとも一方の主面に拡散防止層(バリア層)としてのクロム,モリブデン,チタン等を被着させて下地導体層を形成する。次に、この上に所望のパターンにフォトレジストを形成し、このフォトレジストをマスクにして主導体層の部分をめっき法にて所望の厚みまで形成する。その後、めっきされなかった不要部分のフォトレジストを剥離し、さらに下地導体層をエッチングにて除去することにより、所望のパターンに加工することができる。   The thin film wiring layer 15 formed between the resin insulation layers 16 of the thin film multilayer portion 12 is made of a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium, and alloys thereof, and these are sputtered, It is formed by adopting thin film formation techniques such as vapor deposition and plating. The method for forming the thin-film conductor layer 15 of the thin-film multilayer portion 12 is, for example, first of a wide area on the surface of the resin insulating layer 16 of the thin-film multilayer portion 12, mainly composed of a copper layer, and diffusion prevention on at least one main surface of the copper layer A base conductor layer is formed by depositing chromium, molybdenum, titanium or the like as a layer (barrier layer). Next, a photoresist is formed in a desired pattern thereon, and the main conductor layer portion is formed to a desired thickness by plating using this photoresist as a mask. Thereafter, an unnecessary portion of the photoresist that has not been plated is peeled off, and the underlying conductor layer is removed by etching, whereby a desired pattern can be processed.

さらに、薄膜多層部12の樹脂絶縁層16には所定位置に貫通するビアホール17が形成されている。ビアホール17は、例えば所定位置の薄膜多層部12の樹脂絶縁層16を紫外線レーザ等で除去することにより形成される。その内部の樹脂絶縁層16の層間に配置された薄膜配線層15に、通常は上側の配線導体層15を上記薄膜配線層15の形成方法と同様に形成することによって層間の薄膜配線層15間が導通される。このビアホール17が薄膜多層部12の樹脂絶縁層16を挟んで上下に位置する薄膜配線層15の各々を電気的に接続する接続路となる。   Further, a via hole 17 penetrating at a predetermined position is formed in the resin insulating layer 16 of the thin film multilayer portion 12. The via hole 17 is formed, for example, by removing the resin insulating layer 16 of the thin film multilayer portion 12 at a predetermined position with an ultraviolet laser or the like. Usually, the upper wiring conductor layer 15 is formed in the thin film wiring layer 15 disposed between the resin insulation layers 16 inside thereof in the same manner as the method for forming the thin film wiring layer 15, thereby forming the space between the thin film wiring layers 15 between the layers. Is conducted. The via holes 17 serve as connection paths that electrically connect the thin film wiring layers 15 positioned above and below the resin insulating layer 16 of the thin film multilayer portion 12.

なお、薄膜多層部12の最上層となる樹脂絶縁層16の表面に形成されるの薄膜配線層15の主導体には、プローブ10の電気的な接続信頼性および耐環境性の観点から、主導体が銅から成るものとすることがよく、また、その場合にはその主導体の上にニッケルや金を被着形成しておくとよい。   The main conductor of the thin film wiring layer 15 formed on the surface of the resin insulating layer 16 that is the uppermost layer of the thin film multilayer portion 12 is led from the viewpoint of electrical connection reliability and environmental resistance of the probe 10. The body is preferably made of copper. In that case, nickel or gold is preferably deposited on the main conductor.

次に、図3は本発明のプローブカードの実施の形態の一例を示す模式的な断面図であり、9は中継基板、10はプローブ、7は半導体素子、8は半導体素子7の電極を示す。なお、多層配線基板11を示す部分には図1,図2と同じ符号を示した。   FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of the probe card of the present invention, wherein 9 is a relay substrate, 10 is a probe, 7 is a semiconductor element, and 8 is an electrode of the semiconductor element 7. . Note that the same reference numerals as those in FIGS. 1 and 2 are given to the portions showing the multilayer wiring board 11.

本発明のプローブカードは、本発明の多層配線基板11とその電極パッド3上に接続されたプローブ10と、一端がベース基板1の他の主面に形成されている外部接続用パッド14に電気的に接続されるとともに他端が半導体素子の検査装置(図示せず)に電気的に接続される配線層が形成された中継基板9とを備えている。   The probe card of the present invention is electrically connected to the multilayer wiring board 11 of the present invention and the probe 10 connected on the electrode pad 3 and the external connection pad 14 having one end formed on the other main surface of the base substrate 1. And a relay substrate 9 on which a wiring layer is formed, the other end of which is electrically connected to a semiconductor device inspection device (not shown).

プローブ10は、主に金やアルミニウム等の金属から成るスプリング性のある針状の接続端子で、電極パッド3に錫や鉛等から成る半田等を用いて接合したり、圧力をかけた状態で固定することによって取り付けられる。そして、電極パッド3に取り付けられた反対側の先端を半導体素子7の電極8に接触させることにより、多層配線基板11と半導体素子7とを接続させる機能を有する。   The probe 10 is a spring-like needle-shaped connection terminal mainly made of a metal such as gold or aluminum. The probe 10 is joined to the electrode pad 3 by using solder or the like made of tin, lead or the like, or under pressure. Attached by fixing. The multilayer wiring board 11 and the semiconductor element 7 are connected by bringing the opposite end attached to the electrode pad 3 into contact with the electrode 8 of the semiconductor element 7.

中継基板9は、一般的なガラス繊維入りエポキシ樹脂を基材とする多層配線基板であり、多層配線基板11の外部接続用電極パッド14と半導体素子の検査装置(図示せず)とを電気的に接続する機能を有する。多層配線基板11の外部接続用電極パッド14と中継基板9との接続は、主に錫や鉛等で構成されるボール形状の半田等を用いて接続され、中継基板9と半導体素子の検査装置(図示せず)はポゴピン等を使用して接続される。   The relay board 9 is a multilayer wiring board based on a general epoxy resin containing glass fiber, and electrically connects the external connection electrode pads 14 of the multilayer wiring board 11 and a semiconductor device inspection device (not shown). It has a function to connect to. The connection between the external connection electrode pad 14 of the multilayer wiring board 11 and the relay board 9 is made by using ball-shaped solder or the like mainly composed of tin, lead or the like. (Not shown) are connected using pogo pins or the like.

かくして、本発明のプローブカードによれば、本発明の多層配線基板11の上面にプローブ10と、一端が多層配線基板11の外部接続用電極パッド14に電気的に接続されるとともに他端が半導体素子7の検査装置に電気的に接続される配線層が形成された中継基板9とを具備したことより、副電源用接続パッド4a,4b,4c,4dより半導体素子7に副電源用接続配線6を介して副電源電力を供給することにより、精度の高い半導体素子7の電気検査を実施することができる。   Thus, according to the probe card of the present invention, the probe 10 is electrically connected to the upper surface of the multilayer wiring board 11 of the present invention, one end is electrically connected to the external connection electrode pad 14 of the multilayer wiring board 11, and the other end is a semiconductor. Sub-power supply connection wiring to the semiconductor element 7 from the sub-power connection pads 4a, 4b, 4c, and 4d is provided. By supplying the sub power supply via 6, the electrical inspection of the semiconductor element 7 with high accuracy can be performed.

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更は可能である。例えば、前述のプローブ10の代わりに異方性導電ゴム等を用いたプローブ10を採用して半導体素子7と多層配線基板11を接続するプローブカードとしても良い。   It should be noted that the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the present invention. For example, a probe card that uses anisotropic conductive rubber or the like instead of the probe 10 described above may be adopted to connect the semiconductor element 7 and the multilayer wiring board 11.

本発明の多層配線基板の実施の形態の一例を示す平面図である。It is a top view which shows an example of embodiment of the multilayer wiring board of this invention. 図1の多層配線基板のA−A’線における断面図である。It is sectional drawing in the A-A 'line | wire of the multilayer wiring board of FIG. 本発明のプローブカードの実施の形態の一例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of embodiment of the probe card of this invention. 従来の垂直型のプローブカードの例を示す断面模式図である。It is a cross-sectional schematic diagram which shows the example of the conventional vertical type probe card. 従来の多層配線基板の例を示す平面図である。It is a top view which shows the example of the conventional multilayer wiring board.

符号の説明Explanation of symbols

1:ベース基板
2:配線導体層
3:電極パッド
4:副電源用接続パッド群
4a:副電源用接続パッド(A)
4b:副電源用接続パッド(B)
4c:副電源用接続パッド(C)
4d:副電源用接続パッド(D)
5:シグナル配線
6:副電源用接続配線
7:半導体素子
8:(半導体素子の)電極
9:中継基板
10:プローブ
11:多層配線基板
12:薄膜多層部
13:接続パッド
14:外部接続用電極パッド
15:薄膜配線層
16:樹脂絶縁層
17:薄膜多層部のビアホール
1: Base substrate 2: Wiring conductor layer 3: Electrode pad 4: Sub power source connection pad group 4a: Sub power source connection pad (A)
4b: Sub power connection pad (B)
4c: Sub power connection pad (C)
4d: Sub power supply connection pad (D)
5: Signal wiring 6: Connection wiring for sub power supply 7: Semiconductor element 8: Electrode (of semiconductor element) 9: Relay substrate
10: Probe
11: Multilayer wiring board
12: Thin film multilayer
13: Connection pad
14: Electrode pad for external connection
15: Thin film wiring layer
16: Resin insulation layer
17: Via hole in thin film multilayer

Claims (2)

絶縁層が複数積層されて成るとともに前記絶縁層の層間に配線導体層が形成されたベース基板と、該ベース基板の主面に積層された、樹脂絶縁層が複数積層されて成るとともに前記樹脂絶縁層の層間に薄膜配線層が形成された薄膜多層部と、該薄膜多層部の表面に形成された、前記薄膜配線層および半導体素子の電極に電気的に接続されて前記半導体素子の電気的接続を検査するための複数の電極パッドと、前記ベース基板の主面に形成されて前記電極パッド、前記薄膜配線層および前記配線導体層を電気的に接続する複数の接続パッドとを具備しており、前記複数の接続パッドは複数の副電源用接続パッドから成る副電源用接続パッド群を複数群含み、前記副電源用接続パッド群は前記半導体素子の外周部直下に位置するようにそれぞれ配置されていることを特徴とする多層配線基板。 A base substrate in which a plurality of insulating layers are stacked and a wiring conductor layer is formed between the insulating layers, and a plurality of resin insulating layers that are stacked on the main surface of the base substrate are stacked and the resin insulation A thin film multilayer portion in which a thin film wiring layer is formed between the layers, and an electrical connection of the semiconductor element that is electrically connected to the thin film wiring layer and the electrode of the semiconductor element formed on the surface of the thin film multilayer portion And a plurality of connection pads that are formed on the main surface of the base substrate and electrically connect the electrode pads, the thin film wiring layer, and the wiring conductor layer. The plurality of connection pads include a plurality of sub power supply connection pad groups each including a plurality of sub power connection pads, and the sub power connection pad groups are respectively arranged so as to be located immediately below the outer peripheral portion of the semiconductor element. Multi-layer wiring board, characterized in that it is. 請求項1記載の多層配線基板と、前記電極パッド上に接続されたプローブと、前記ベース基板の他の主面に形成されるとともに前記接続パッドに電気的に接続されている外部接続用電極パッドと、一端が前記外部接続用電極パッドに電気的に接続されるとともに他端が前記半導体素子の検査装置に電気的に接続される配線層が形成された中継基板とを具備したことを特徴とするプローブカード。 2. The multilayer wiring board according to claim 1, a probe connected on the electrode pad, and an external connection electrode pad formed on the other main surface of the base substrate and electrically connected to the connection pad. And a relay substrate on which a wiring layer is formed, one end of which is electrically connected to the external connection electrode pad and the other end of which is electrically connected to the semiconductor device inspection apparatus. Probe card.
JP2003304514A 2003-08-28 2003-08-28 Multilayer wiring board and probe card Pending JP2005079144A (en)

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JP2006278374A (en) * 2005-03-28 2006-10-12 Sony Corp Semiconductor device and its mounting structure
JP2008164427A (en) * 2006-12-28 2008-07-17 Micronics Japan Co Ltd Probe unit board
JP2009158761A (en) * 2007-12-27 2009-07-16 Ngk Spark Plug Co Ltd Wiring board for electronic component inspection equipment
WO2009118850A1 (en) * 2008-03-26 2009-10-01 株式会社アドバンテスト Probe wafer, probe device, and testing system
JP2010232253A (en) * 2009-03-26 2010-10-14 Kyocera Corp Probe card wiring board and probe card using the same
JP2012042446A (en) * 2010-08-13 2012-03-01 Samsung Electro-Mechanics Co Ltd Method for repairing probe board and probe board using the method
CN102656468A (en) * 2009-12-17 2012-09-05 特拉华资本构造公司 Wiring Board for Testing Loaded Printed Circuit Board
WO2016024534A1 (en) * 2014-08-11 2016-02-18 株式会社村田製作所 Probe card and multilayer circuit board with which said probe card is provided
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JP2020181842A (en) * 2019-04-23 2020-11-05 京セラ株式会社 Circuit board and probe card

Cited By (20)

* Cited by examiner, † Cited by third party
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JP2006278374A (en) * 2005-03-28 2006-10-12 Sony Corp Semiconductor device and its mounting structure
JP2008164427A (en) * 2006-12-28 2008-07-17 Micronics Japan Co Ltd Probe unit board
JP2009158761A (en) * 2007-12-27 2009-07-16 Ngk Spark Plug Co Ltd Wiring board for electronic component inspection equipment
WO2009118850A1 (en) * 2008-03-26 2009-10-01 株式会社アドバンテスト Probe wafer, probe device, and testing system
US8134379B2 (en) 2008-03-26 2012-03-13 Advantest Corporation Probe wafer, probe device, and testing system
JP5306326B2 (en) * 2008-03-26 2013-10-02 株式会社アドバンテスト Probe wafer, probe apparatus, and test system
JP2010232253A (en) * 2009-03-26 2010-10-14 Kyocera Corp Probe card wiring board and probe card using the same
US8907694B2 (en) 2009-12-17 2014-12-09 Xcerra Corporation Wiring board for testing loaded printed circuit board
CN102656468A (en) * 2009-12-17 2012-09-05 特拉华资本构造公司 Wiring Board for Testing Loaded Printed Circuit Board
US9753058B2 (en) 2009-12-17 2017-09-05 Xcerra Corporation Wiring board for testing loaded printed circuit board
JP2012042446A (en) * 2010-08-13 2012-03-01 Samsung Electro-Mechanics Co Ltd Method for repairing probe board and probe board using the method
US9095065B2 (en) 2010-08-13 2015-07-28 Samsung Electro-Mechanics Co., Ltd. Method of repairing probe board and probe board using the same
US8806731B2 (en) 2010-08-13 2014-08-19 Samsung Electro-Mechanics Co., Ltd. Method of repairing a probe board
WO2016024534A1 (en) * 2014-08-11 2016-02-18 株式会社村田製作所 Probe card and multilayer circuit board with which said probe card is provided
JPWO2016024534A1 (en) * 2014-08-11 2017-05-25 株式会社村田製作所 Probe card and multilayer wiring board provided with the probe card
CN106796251A (en) * 2014-08-11 2017-05-31 株式会社村田制作所 The stacking circuit board that probe card and the probe card possess
EP3165932A1 (en) * 2015-11-03 2017-05-10 NGK Spark Plug Co., Ltd. Wiring board for device testing
US9903887B2 (en) 2015-11-03 2018-02-27 Ngk Spark Plug Co., Ltd. Wiring board for device testing
TWI639835B (en) * 2015-11-03 2018-11-01 日商日本特殊陶業股份有限公司 Wiring board for device testing
JP2020181842A (en) * 2019-04-23 2020-11-05 京セラ株式会社 Circuit board and probe card

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