JP2005072461A - Semiconductor device manufacturing method, semiconductor device, electro-optical device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, a semiconductor device, an electro-optical device using the same, and an electronic apparatus capable of optimizing a threshold voltage of a field effect transistor in accordance with a driving voltage. about.
In a manufacturing process of a TFT array substrate of an electro-optical device, after forming a gate insulating film 2, an etching mask is formed by photolithography, and a predetermined region of the gate insulating film 2 is selected from the opening of the etching mask. The predetermined region of the gate insulating film 2 is thinned by etching. Accordingly, the threshold voltages of the N-channel TFTs and the P-channel TFTs can be made different between the CMOS circuits having different driving voltages.
[Selection] FIG.

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a plurality of field effect transistors are formed on the same substrate, a semiconductor device, an electro-optical device using the semiconductor device, and an electronic apparatus.

  In an electro-optical device such as an active matrix liquid crystal device or an organic electroluminescence display device, a substrate holding an electro-optical material has a plurality of thin film transistors (field effect transistors / hereinafter referred to as TFTs (Thin)) as active elements for pixel switching. And a TFT array substrate (semiconductor device) in which a plurality of drive circuit TFTs constituting the drive circuit are formed.

  In such an element substrate, in the drive circuit, as shown in FIGS. 1A and 1B, an N-channel TFT and a P-channel TFT constitute a complementary circuit. On the other hand, from the standpoint of speeding up operation and reducing power consumption, a configuration in which the absolute value of the threshold voltage of the TFT is as close to 0 V as possible, and the threshold voltages of the N-channel TFT and P-channel TFT are as equal as possible A configuration in which a voltage value is used, a configuration in which variation in threshold voltage of an N-channel TFT or a P-channel TFT is reduced, and the like have been proposed (for example, see Patent Document 1).

  In addition, in the drive circuit built-in type electro-optical device, the pixel switching TFT is required to have a small off-current, and the drive circuit TFT is required to have a large on-current. It has also been proposed that the transistor characteristics be different from those of the TFT for use (see, for example, Patent Document 2).

  Here, the driving voltage of the complementary circuit is defined by the maximum potential difference between a plurality of power supplies and signals input to the corresponding circuit. Conventionally, a threshold voltage for turning on / off an electro-optical material such as a liquid crystal or an IC It is determined by external factors such as the output signal level. In general, a control input signal output from an IC, that is, a clock signal or a start pulse signal has a relatively small voltage amplitude of about 1V to 5V. In addition, since the power consumption of the circuit is proportional to the square of the drive voltage, it is preferable to drive the circuit at as low a voltage as possible. Therefore, in a logic circuit such as a shift register, it is desirable to set the drive voltage to a low voltage as long as the TFT characteristics allow. However, the higher the frequency (high-speed operation) of the circuit, the higher the driving voltage is required. Further, in order to switch the alignment state of the liquid crystal between the black level and the white level, a potential difference of about 3 V to 5 V is necessary, and since the polarity needs to be inverted, the total width of the voltage amplitude is about 6 V to 10 V. The amplitude of the signal applied to the scan bus line needs to be higher than that in consideration of the threshold voltage of the pixel switching transistor. Therefore, when the scanning line driving circuit and the data line driving circuit are compared, it is originally preferable that the driving voltage is low in the data line driving circuit and the driving voltage is high in the scanning line driving circuit.

However, in the past, the TFT characteristics were originally low, the circuits that could be built were limited, and the drive voltage of the circuit was mostly determined by the TFT characteristics, so changing the drive voltage depending on the circuit in this way was not very common. It was.
JP-A-7-273349 JP-A-9-266316

  Conventionally, since the threshold voltage of the TFT is generally high and it is difficult to lower the voltage of the complementary circuit, the entire display device has to be driven at 8V to 12V. For this reason, the balance between the drive voltage of the built-in peripheral circuit and the voltage applied to the display portion is secured to some extent, so that the absolute value of the threshold voltage of the TFT can be set as much as possible from the viewpoint of reducing power consumption and holding capacity. Although only studies have been made such as approaching 0 V or setting different threshold voltages for pixel switching TFTs and driving circuit TFTs, polysilicon film crystallization techniques and gate insulating film formation techniques Now that TFTs with low threshold voltages can be manufactured, the balance between the drive voltage of the built-in peripheral circuit and the voltage applied to the display portion is being greatly broken.

  In other words, the peripheral logic circuit can be driven at a voltage of 7 V or less, and it is expected that the drive voltage will further decrease from the viewpoint of reducing current consumption. However, since there is a threshold voltage of the electro-optic material, the voltage applied to the display portion cannot be kept below a certain level, and there is a tendency that circuits with greatly different driving voltages are mixed depending on the circuit. Moreover, if many circuits are further integrated on the same substrate toward the SOP in the future, the driving voltage will inevitably become different depending on the circuit. For example, a circuit driven at a high frequency requires a higher driving voltage because an on-state current of the transistor is required, and a low frequency circuit has a circumstance that it is desired to operate at a low driving voltage in order to reduce power consumption.

  Under such circumstances, when the entire electro-optical device is composed of TFTs having a low threshold voltage, there is a problem that a malfunction occurs in a complementary circuit having a high drive voltage. This point will be described with reference to the drawings.

  When the inverter is configured by a complementary circuit as shown in FIG. 1A and used at a driving voltage of 10 V, the output signal OUT is ideal as the input signal IN is periodically switched between a high level and a low level. Specifically, as shown in FIG. However, in an actual circuit, as shown in FIG. 2B, due to the influence of the resistance and parasitic capacitance of the wiring, the input signal IN does not rise or fall rapidly, but has a gentle gradient. Change. Therefore, when the threshold voltage of the N-channel TFT is about + 1V to + 3V and the threshold voltage of the P-channel TFT is about -1V to -3V, for example, each is + 2V and -2V. In the case where there is, a period during which the input voltage IN is between (high level side power supply voltage + threshold voltage of P-channel TFT) and (low level side power supply voltage + N channel type TFT threshold voltage), that is, 2V In an interval of ˜8 V, an inversion layer is formed in the channel region in both the N-channel TFT and the P-channel TFT, and both TFTs are in a low resistance state. For this reason, the output signal OUT takes an intermediate voltage between the high level and the low level, which causes a problem that a malfunction or malfunction is caused in the circuit.

  In the CMOS clocked inverter as shown in FIG. 1B, when the threshold voltages of the N-channel TFT and the P-channel TFT are +2 V and −2 V, respectively, the clock signal CLK is 5 V due to signal delay. When the inverted signal CLKX is 5V, the clocked inverter shown in FIG. 1B and the clocked inverter in which CLK and CLKX are switched with respect to FIG. Therefore, there is a problem that the signal selection operation and the latch operation are not performed correctly. Such a problem also applies to the complementary transmission gate.

  In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a plurality of field effect transistors with different threshold voltages on the same substrate in accordance with a driving voltage or the like, A semiconductor device, an electro-optical device using the semiconductor device, and an electronic apparatus are provided.

  In order to solve the above problems, according to the present invention, in a method of manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode constituting a channel region are formed, at least the gate An insulating film forming step for forming an insulating film for forming an insulating film and an insulating film etching step for selectively etching a predetermined region of the insulating film are performed, and the conductivity type is the same, and the thickness of the gate insulating film The first field-effect transistor and the second field-effect transistor with different lengths are formed over the same substrate.

  In the present invention, after the first insulating film for forming the gate insulating film is formed in the first insulating film forming process as the insulating film forming process, the first insulating film is formed in the insulating film etching process. A predetermined region of the film is selectively etched, and then a second insulating film forming step is performed again to form the gate insulating film on the surface side of the first insulating film in the second insulating film forming step. Two insulating films may be formed.

  In the present invention, after forming the first insulating film for forming the gate insulating film in the first insulating film forming process as the insulating film forming process, the second insulating film forming process is performed again as the second insulating film forming process. In the insulating film forming step, a second insulating film for forming the gate insulating film is formed on the surface side of the first insulating film, and then in the insulating film etching step, the second insulating film is formed. The predetermined region may be selectively etched.

  In the present invention, insulating films having different dielectric constants may be formed as the first insulating film and the second insulating film.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. A semiconductor film forming step for forming a semiconductor film for the semiconductor film, and a semiconductor film thickness adjusting step for adjusting the thickness of the semiconductor film by selectively oxidizing or etching a predetermined region of the semiconductor film. A first field effect transistor and a second field effect transistor which are the same and have different thicknesses of semiconductor films constituting the channel region are formed over the same substrate.

  In the present invention, after forming a first semiconductor film for forming the channel region in the first semiconductor film forming step as the semiconductor film forming step, the first semiconductor in the semiconductor film thickness adjusting step. A second region for selectively etching a predetermined region of the film and then forming the channel region on the surface side of the first semiconductor film again in a second semiconductor film forming step as the semiconductor film forming step. The semiconductor film may be formed.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. A semiconductor film forming step of forming a semiconductor film for the semiconductor film and a laser annealing step of crystallizing the semiconductor film by performing excimer laser annealing on the semiconductor film under different conditions for each region, and having the same conductivity type The first field effect transistor and the second field effect transistor having different film qualities of the semiconductor film constituting the channel region are formed over the same substrate.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors having a semiconductor layer, a gate insulating film, and a gate electrode constituting a channel region are formed, at least the film quality or film for each region A base insulating film forming step for forming base insulating films having different thicknesses; a semiconductor film forming step for forming a semiconductor film for forming the channel region on the surface side of the base insulating film; and excimer laser annealing for the semiconductor film. A first annealing and a second field effect transistor having the same conductivity type and different film quality of the semiconductor film constituting the channel region Are formed on the same substrate.

  In the present invention, the base insulating film is made of, for example, a silicon compound in which the content ratio of nitrogen and oxygen in the outermost layer is different for each region.

  In the present invention, the base insulating film may be made of a silicon compound having a different etching rate for hydrofluoric acid in each region.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each including a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least in a predetermined region on a substrate A base metal film forming step for selectively forming a base metal film, a base insulating film forming step for forming a base insulating film on the surface side of the base metal film, and the channel region on the surface side of the base insulating film are configured. A semiconductor film forming step for forming a semiconductor film for performing the semiconductor film and a laser annealing step for crystallizing the semiconductor film by performing excimer laser annealing on the semiconductor film to form the channel region having the same conductivity type A first field-effect transistor and a second field-effect transistor having different semiconductor film qualities are formed over the same substrate.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. A semiconductor film forming step for forming a semiconductor film, an insulating film forming step for forming an insulating film having a different film thickness on the surface of the semiconductor film, and an excimer laser annealing on the semiconductor film to form the semiconductor film And a first field effect transistor and a second field effect transistor having the same conductivity type and different film quality of the semiconductor film constituting the channel region are formed on the same substrate. It is characterized by doing.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. A semiconductor film forming step for forming a semiconductor film, a laser annealing step in which excimer laser annealing is performed on the semiconductor film to crystallize the semiconductor film, and an inert element is selectively introduced into a predetermined region of the semiconductor film The first field effect transistor and the second field effect transistor having the same conductivity type and different film quality of the semiconductor film constituting the channel region are formed on the same substrate. It is characterized by that.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed, at least the channel region is formed. A channel doping step of selectively introducing impurity ions into a predetermined region of the semiconductor layer is performed, and a first field effect transistor and a second field effect transistor having the same conductivity type and different types or concentrations of impurities contained in the channel region A field effect transistor is formed over the same substrate.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. An insulating film forming step of forming an insulating film having a different thickness depending on a region on the surface side of the semiconductor layer and a channel doping step of introducing impurity ions into the semiconductor layer through the insulating film are performed to have the same conductivity type Thus, the first field effect transistor and the second field effect transistor having different types or concentrations of impurities contained in the channel region are formed over the same substrate.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each including a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, impurity ions are added to at least the semiconductor layer. An impurity introducing step to be introduced and an activation step of activating the impurity ions by selectively irradiating light to a predetermined region of the semiconductor layer constituting the channel region, and having the same conductivity type and the channel A first field effect transistor and a second field effect transistor having different film qualities of the semiconductor layer constituting the region are formed over the same substrate.

  In another embodiment of the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode that form a channel region are formed, at least the channel region is formed. An insulating film forming step of forming an insulating film having a different thickness depending on a region on the surface side of the semiconductor layer, and a hydrogen ion introducing step of introducing hydrogen ions into the semiconductor layer through the insulating film are performed. A first field effect transistor and a second field effect transistor which are the same and have different film qualities of the semiconductor layer forming the channel region are formed over the same substrate.

In the present invention, for example, a first complementary circuit is formed by an N-channel field-effect transistor and a P-channel field-effect transistor as the first field-effect transistor, and the second field-effect transistor The second complementary circuit in which the driving voltage defined by the maximum voltage difference between the signal input to the first complementary circuit and the power supply differs depending on the N-channel field-effect transistor and the P-channel field-effect transistor And a threshold voltage for forming an inversion layer in the channel region of the N-channel field effect transistor and a threshold voltage for forming an inversion layer in the channel region of the P-channel field effect transistor, respectively. When Vth-Nch and Vth-Pch,
In the first complementary circuit and the second complementary circuit, the following expression Vth−d = | (Vth−Nch) − (Vth−Pch) |
This is performed when manufacturing a semiconductor device in which the absolute value Vth-d of the threshold voltage difference represented by In the semiconductor device configured as described above, in each of the first and second complementary circuits having different driving voltages, the threshold voltage of the N-channel field effect transistor and the threshold of the P-channel field effect transistor are used. The absolute value of the difference between the value voltages is made different in accordance with the drive voltage, and is made appropriate. For this reason, in order to achieve high-speed operation and low power consumption, even when the threshold voltage of the field effect transistor is reduced, the balance between the drive voltage and the threshold voltage is not achieved in each complementary circuit. Therefore, no malfunction occurs in the complementary circuit. In particular, in an electro-optical device, although there is no space in spite of driving a large number of pixels, the wiring and the like are considerably miniaturized. When used in a direct-view display, the input signal waveform is likely to be distorted due to RC delay because the device itself is large and the wiring length becomes long. Even in such a case, the complementary circuit malfunctions. Does not occur. Therefore, in the electro-optical device, high reliability can be ensured even when the number of pixels is increased, the screen is enlarged, the operation speed is increased, and the power consumption is reduced.

Here, regarding the threshold voltage, the configuration is defined using the threshold voltage in the physical sense as a parameter, but the condition may be defined as the threshold voltage in terms of circuit operation. That is, according to the present invention, for example, a first complementary circuit is formed by an N-channel field effect transistor and a P-channel field effect transistor as the first field effect transistor, and the second field effect is formed. The driving voltage defined by the maximum voltage difference between the signal inputted to the first complementary circuit and the power source differs depending on the N-channel field-effect transistor and the P-channel field-effect transistor as the type transistors. A value obtained by dividing a drain-source resistance by a channel width when a complementary circuit is formed and a predetermined constant voltage Vds-Nch between 1 V and 20 V is applied between the drain and source in an N-channel field effect transistor. Von-off-Nch when the gate voltage becomes a predetermined value Ron-off between 1 MΩ / μm and 1 GΩ / μm, and P A value obtained by dividing the drain-source resistance by the channel width when a predetermined voltage Vds-Pch between -1 V to -20 V is applied between the drain and the source in the channel type field effect transistor is the predetermined value. When the gate voltage when Ron-off is Von-off-Pch,
In the first complementary circuit and the second complementary circuit, the following expression Von-off-d = | (Von-off-Nch) − (Von-off-Pch) |
This is carried out when manufacturing a semiconductor device in which the absolute value Von-off-d of the threshold voltage difference in terms of circuit operation obtained in (1) is different.

  The semiconductor device according to the present invention is used, for example, as an electro-optical device substrate for holding an electro-optical material in an electro-optical device. In this case, a field-effect transistor for pixel switching corresponding to each of a plurality of pixels arranged in a matrix and a drive circuit for driving the plurality of pixels are formed on the electro-optical device substrate. A field effect transistor for a driving circuit, and the plurality of field effect transistors include a first complementary circuit having a driving voltage defined by a signal input and a maximum voltage difference between power supplies, and An N-channel field effect transistor and a P-channel field effect transistor constituting the second complementary circuit are included.

  In the present invention, the electro-optical material is, for example, a liquid crystal held between the electro-optical device substrate and a counter substrate.

  In the present invention, the electro-optical material is, for example, an electroluminescent material that constitutes a light-emitting element on the electro-optical device substrate.

  An electro-optical device to which the present invention is applied is used in an electronic apparatus such as a mobile phone or a mobile computer.

  According to the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed, the gate insulating film or the semiconductor layer forming the channel region A plurality of field effect transistors having different threshold voltages are formed on the same substrate by differentiating the thickness and film quality. For this reason, a complementary circuit or the like can be configured by a field effect transistor having a threshold voltage corresponding to the drive voltage, so that malfunction caused by an imbalance between the threshold voltage and the drive voltage can be prevented. it can.

  Embodiments of the present invention will be described below with reference to the drawings.

[Configuration Example 1 of Complementary Circuit Subject of the Present Invention]
A specific configuration of an active matrix liquid crystal device (electro-optical device) with a built-in driving circuit to which the present invention is applied will be described later. A TFT array for holding liquid crystal as an electro-optical material between a counter substrate and a counter substrate. On the substrate (active matrix substrate), along with the pixel switching TFTs, drive circuit TFTs constituting the drive circuit are formed in the peripheral region of the element substrate. In this type of driving circuit, a scanning line driving circuit and a data line driving circuit including a shift resistor are constituted by a complementary circuit (hereinafter referred to as a CMOS circuit) including an N-channel TFT and a P-channel TFT. Here, the drive circuit includes CMOS circuits having different drive voltages. For example, the data line driving circuit includes a CMOS circuit having a driving voltage of 12V, and the scanning line driving circuit includes a CMOS circuit having a driving voltage of 5V. Conventionally, an apparatus having such a configuration is manufactured so as to reduce the threshold voltage in accordance with a scanning line driving circuit having a low driving voltage (5V), and this is a data line driving circuit having a high driving voltage (12V). This was a cause of malfunction.

  Under such a technical background, the present invention is characterized in that a TFT having an appropriate threshold voltage corresponding to the driving voltage is used for each CMOS circuit, and details thereof will be described below.

(Relationship between threshold voltage and driving voltage of TFT)
1A and 1B are explanatory diagrams of an inverter circuit using a CMOS circuit and a clocked inverter circuit, respectively. 2A, 2B, and 2C are waveform diagrams showing the relationship between an input signal and an output signal for the CMOS circuit, respectively. In the following description, CMOS circuits having different driving voltages are referred to as a first CMOS circuit and a second CMOS circuit. Here, “first” and “second” mean that the drive voltages are different, and that there are not only two types of CMOS circuits but also three or more types of CMOS circuits. .

  In the present invention, first, the relationship between the threshold voltage of the N-channel TFT and P-channel TFT constituting the CMOS circuit and the driving voltage of the CMOS circuit is optimized for each CMOS circuit.

That is, in the present invention, the physical threshold voltage at which the inversion layer is formed in the channel of the N-channel TFT is Vth-Nch, and the physical threshold voltage at which the inversion layer is formed in the channel region of the P-channel TFT. When the voltage is Vth-Pch,
In the first CMOS circuit and the second CMOS circuit, the following formula Vth−d = | (Vth−Nch) − (Vth−Pch) |
In any CMOS circuit, the absolute value Vth-d of the threshold voltage difference is different from the driving voltage of the CMOS circuit. For example, it is set in the range of 0.25 to 1 times, preferably in the range of 0.5 to 1 times.

  For example, when the driving voltage of the first CMOS circuit is 5V, the absolute value Vth-d of the threshold voltage difference between TFTs constituting the CMOS circuit is in the range of 1.25V to 5V, preferably 2. It is in the range of 5V-5V. On the other hand, when the driving voltage of the second CMOS circuit is, for example, 12V, the absolute value Vth-d of the threshold voltage difference between TFTs constituting this CMOS circuit is in the range of 3V to 12V, preferably , In the range of 6V to 12V. That is, in the case of adopting a preferable configuration, the absolute value (Vth-d) of the difference between the threshold voltages of the transistors constituting the first CMOS circuit and the transistors constituting the second CMOS circuit does not take different values. Must not. For example, Vth-Nch and Vth-Pch in the first CMOS circuit may be + 2V and -2V, respectively, and Vth-Nch and Vth-Pch in the second CMOS circuit may be + 5V and -5V, respectively.

  In this way, if the absolute value Vth-d of the threshold voltage difference is optimized in correspondence with the driving voltage of each CMOS circuit, malfunction of the driving circuit can be prevented. That is, in the case where the inverter is configured by a CMOS circuit as shown in FIG. 1A, even if the waveform of the input signal IN is distorted and the rise or fall is not steep due to the influence of wiring resistance or parasitic capacitance, the threshold is reduced. When the absolute value Vth-d of the value voltage difference is made equal to the power supply voltage, for example, the driving voltage, the threshold voltage at which an inversion layer is formed in the channel region of the N-channel TFT, and the P-channel TFT When the threshold voltages are 10 V, +5 V, and -5 V, respectively, the absolute value Vth-d of the difference between the threshold voltages is equal to the drive voltage of the CMOS circuit, and the N-channel transistor and the P-channel transistor Are not simultaneously turned ON or OFF, and an output waveform with a steep rise or fall can be obtained as shown in FIG.

  Here, as the absolute value Vth-d of the threshold voltage difference is closer to the driving voltage of the CMOS circuit, malfunction can be prevented. However, the absolute value Vth-d of the threshold voltage difference is less than that of the CMOS circuit. When the drive voltage is exceeded, there is a timing with no output when both transistors are OFF, and an ON current cannot be secured sufficiently, which is also not preferable. Therefore, the absolute value Vth-d of the threshold voltage difference may be set to a level slightly lower than the driving voltage of the CMOS circuit.

  In addition, since there is always a variation in the threshold voltage in each TFT, an inversion layer is formed in the channel region of the N-channel TFT when obtaining the absolute value Vth-d of the threshold voltage difference. The minimum value of the threshold voltage and the maximum value of the threshold voltage at which the inversion layer is formed in the channel region of the P-channel TFT are Vth-Nch and Vth-Pch, respectively. It is preferable to obtain an absolute value Vth−d (= | (Vth−Nch) − (Vth−Pch) |) of the difference between the value voltages.

  The allowable range of the absolute value Vth-d of the threshold voltage difference becomes narrower as the gradient of the input signal IN is larger. That is, the time that the input signal IN takes between (high level side driving voltage + threshold value of the P-channel TFT) and (low level side driving voltage + threshold value of the N channel type TFT) causes malfunction. It should be shorter than time. Here, since the slope of the input signal IN is inversely proportional to the wiring relaxation time τ = RC (R: wiring resistance, C: parasitic capacitance), the wiring length, wiring material, film thickness / dielectric constant of the interlayer insulating film It depends on etc. In this embodiment, the absolute value Vth-d of the threshold voltage difference is calculated with respect to the driving voltage of the CMOS circuit based on the result of waveform measurement performed on the element substrate of the liquid crystal device using low-temperature polysilicon. The range is 0.25 times to 1 time, preferably 0.5 times to 1 time.

  Therefore, it can be seen from the above setting that the effect of the present invention is remarkable when the ratio of Vth-d between the circuits differs by 2 times or more. Therefore, according to the present embodiment, it is possible to prevent malfunction of the high voltage side circuit even when the drive voltage includes a CMOS circuit that is twice or more that of other CMOS circuits. Further, according to this embodiment, in at least one of the first CMOS circuit and the second CMOS circuit, the absolute value Vth-d of the threshold voltage difference is equal to the driving voltage of the other CMOS circuit. Even in the case of half or more, since the balance between the drive voltage and the absolute value Vth-d of the difference between the threshold voltages is ensured for each CMOS circuit, the occurrence of malfunction can be prevented. Therefore, when the present invention is applied to an electro-optical device using such a TFT having a low threshold voltage, the effect is remarkable.

  Furthermore, since a large number of pixels are arranged in a matrix as in an electro-optical device, even when the input signal IN is distorted and rises or falls easily due to the influence of wiring resistance and parasitic capacitance. In this embodiment, since the relationship between the threshold voltage of the TFT and the drive voltage is optimized, no malfunction of the CMOS circuit occurs.

(Balance of threshold voltage between TFTs)
From the viewpoint of preventing malfunction in the CMOS circuit configured as described above, as will be described in detail later with reference to FIG. 6, the absolute value of the threshold voltage of the N-channel TFT and the P-channel TFT It is preferable that the difference from the absolute value of the threshold voltage is small. Specifically, according to the measurement by the inventor, it is preferable that the maximum value of | (Vth−Nch) + (Vth−Pch) | is less than ¼ times the driving voltage of the CMOS circuit, so that malfunction can be reliably prevented. .

  Further, as will be described in detail later with reference to FIG. 7, in at least one of the first CMOS circuit and the second CMOS circuit, the threshold voltage Vth-Nch of the N-channel TFT is It is preferably a positive value and the threshold voltage Vth-Pch of the P-channel TFT is preferably a negative value. That is, it is preferable that both the N-channel TFT and the P-channel TFT are in the enhancement mode.

(Effect of this embodiment)
As described above, in the electro-optical device according to this embodiment, the data line driving circuit includes a CMOS circuit having a driving voltage of 12V, and the scanning line driving circuit includes a CMOS circuit having a driving voltage of 5V. However, in each CMOS circuit, since the balance between the driving voltage and the absolute value Vth-d of the difference between the threshold voltages is ensured, for example, the transistors constituting the shift register of the scanning line driving circuit have threshold values. Since the voltages are +2 V and -2 V for the N channel portion and the P channel portion, respectively, and +4 V and -4 V for the transmission gate portion of the data line driving circuit, respectively, it is possible to prevent malfunctions. Therefore, even when the threshold voltage of the TFT is lowered to achieve high-speed operation (in this embodiment, Vth-d = 4 V), the driving voltage of the CMOS circuit can be adapted to various requirements. Even in a different case, in each CMOS circuit, since the balance between the drive voltage and the absolute value Vth-d of the difference between the threshold voltages is ensured, the occurrence of malfunction can be prevented. In addition, as the number of pixels increases, there is no room for space and the wiring is considerably miniaturized. As a result, the wiring width is narrow at the high drive frequency, or the display part is enlarged. Even when the signal waveform is distorted due to a long period of time, the balance between the drive voltage and the absolute value Vth-d of the difference between the threshold voltages is secured, so that the occurrence of malfunction can be prevented. .

[Configuration 2 of Complementary Circuit Subject of the Present Invention]
FIG. 3 is an explanatory diagram of the threshold voltage Von-off in terms of circuit operation of the TFT. FIG. 4 is a graph showing the correspondence between the threshold voltage Von-off on the circuit operation surface of the TFT and the physical threshold voltage Vth based on the formation of the inversion layer.

  In the above configuration, the relationship between the driving voltage of the CMOS circuit and the configuration of the TFT is defined by the threshold voltage (Vth) which is a physical parameter of the TFT. The threshold voltage (Vth) of a physical transistor refers to a gate voltage at which an inversion layer is formed in the channel region. There are various methods for experimental determination, and the simplest means is, for example, saturation The drain-source current Ids in the region (Vgs−Vth <Vds) is measured, and when the square root of Ids is plotted on the vertical axis and Vgs is plotted on the horizontal axis, the maximum value of Vgs at which the straight line that touches the curve intersects the horizontal axis is Vth. There are methods such as. In the above, Vgs means a gate-source voltage.

  However, particularly in the case of a polysilicon thin film transistor, it is difficult to obtain Vth experimentally with high accuracy, and the value often varies depending on the method. Therefore, the relationship with the drive voltage may be defined by using an on / off threshold voltage Von-off in terms of circuit operation as a simple parameter instead of the threshold voltage (Vth).

  In the active matrix type liquid crystal device with a built-in driving circuit of this embodiment, a driving circuit is formed on the element substrate (active matrix substrate) together with pixel switching TFTs in the peripheral region of the element substrate as in the first embodiment. A driving circuit TFT is formed. In the driving circuit, a plurality of CMOS circuits each including an N-channel TFT and a P-channel TFT are configured. The plurality of CMOS circuits include a first CMOS circuit and a second CMOS circuit having different driving voltages. CMOS circuits are included.

In the liquid crystal device having such a configuration, in this embodiment, in the Vgs-Ids characteristics of the TFT when the drain-source voltage (Vds) shown in FIG. The gate voltage when the value obtained by dividing the source-to-source resistance by the channel width becomes the predetermined value Ron-off is Von-off-Nch, and the value obtained by dividing the drain-source resistance by the channel width in the P-channel TFT is predetermined. When the gate voltage when the value of Ron-off is Von-off-Pch, the following equation Von-off-d = | Von-off-Nch between the first CMOS circuit and the second CMOS circuit: − Von-off-Pch |
The absolute value Von-off-d of the difference in threshold voltage on the circuit operation operation surface obtained in the above is made different, and the threshold voltage on the circuit operation surface is optimized in any CMOS circuit.

  For example, when the driving voltage of the first CMOS circuit is 5 V, for example, the absolute value Von-off-d of the threshold voltage difference in the circuit operation operation of the TFT constituting the CMOS circuit is 1.25 V It is in the range of -5V, preferably in the range of 2.5V-5V. On the other hand, when the driving voltage of the second CMOS circuit is 12 V, for example, the absolute value Von-off-d of the difference in threshold voltage on the circuit operation operation side of the TFT constituting the CMOS circuit is It is in the range of 3V to 12V, preferably in the range of 6V to 12V.

  Here, the threshold voltage Von-off in terms of circuit operation is the drain-source resistance (Rds) per channel width of the TFT when the drain-source voltage (Vds) is fixed to a constant value. It means the gate voltage that becomes a constant value. The constant values of the drain-source voltage (Vds) and the drain-source resistance (Rds) vary depending on the circuit drive frequency and channel length, but are CMOS digital logic circuits formed by low-temperature polysilicon TFTs on a glass substrate. In this case, it is appropriate to set the Ron-off value from about 1 MΩ / μm to about 1 GΩ / μm, the Vds values from 1 to 20 V, and Pch from −1 to −20 V. For example, the threshold voltage Von-off in terms of circuit operation is shown in FIG. 4 when the drain-source resistance (Rds) is constant (Rds˜1 MΩ / μm) or large (Rds˜). As shown in a graph in which the measurement results of a plurality of transistors are plotted for each of about 1 GΩ / μm), it is confirmed that there is a sufficient correlation with the physical threshold voltage Vth.

  Therefore, as in the present embodiment, by setting the absolute value Von-off-d of the threshold voltage difference in the circuit operation operation as described above, for example, the drive voltage ratio is more than twice. Malfunctions in different CMOS circuits can be prevented. Further, according to the present embodiment, in at least one of the first CMOS circuit and the second CMOS circuit, the absolute value Von-off-d of the threshold voltage difference on the circuit operation surface is different. Even when the driving voltage is less than half the driving voltage of the circuit, the same effects as those of the first embodiment can be obtained, such as prevention of malfunction.

  Note that, in each TFT, there is always a variation in the threshold voltage on the circuit operation surface. Therefore, also in this embodiment, the sum Von-off-d of the absolute value of the threshold voltage on the circuit operation surface is obtained. In this case, the minimum value of the gate voltage when the value obtained by dividing the drain-source resistance by the channel width in the N-channel field effect transistor becomes a predetermined value Ron-off, and the drain in the P-channel field effect transistor In terms of circuit operation operation, the maximum gate voltage when the value obtained by dividing the resistance between the sources by the channel width becomes a predetermined value Ron-off is used as Von-off-Nch and Von-off-Pch, respectively. It is preferable to obtain the absolute value Von-off-d of the difference between the threshold voltages.

  Further, from the viewpoint of preventing malfunction, as will be described in detail later with reference to FIG. 6, the absolute value of the threshold voltage on the circuit operation surface of the N-channel TFT and the circuit of the P-channel TFT are described. It is preferable that the difference from the absolute value of the threshold voltage in operation is small. That is, it is preferable that the maximum value of | (Von−off−Nch) + (Von−off−Pch) | is not more than ¼ times the driving voltage of the CMOS circuit.

  Further, as will be described in detail later with reference to FIG. 7, in at least one of the first CMOS circuit and the second CMOS circuit, the threshold value in terms of circuit operation of the N-channel TFT. It is preferable that the voltage Von-off-Nch is a positive value and the threshold voltage Von-off-Pch on the circuit operation surface of the P-channel TFT is a negative value. That is, it is preferable that both the N-channel TFT and the P-channel TFT are in the enhancement mode.

[TFT characteristics example]
FIGS. 5A and 5B show the drain-source current with respect to the gate voltage (gate-source voltage) as compared with the TFT characteristics shown in FIG. 3 in both the N-channel TFT and the P-channel TFT. A graph showing TFT characteristics when the absolute value of the threshold voltage is increased by slowing the rise of the TFT, and the rising slope of the drain / source current with respect to the gate voltage in both the N-channel TFT and the P-channel TFT Is a graph showing the TFT characteristics when the absolute value of the threshold voltage is increased as a result of the enhancement shift as it is. FIGS. 6A and 6B are graphs showing the TFT characteristics when only the absolute value of the threshold voltage of the P-channel TFT is increased by making the inclination gentle or enhancement shifting, respectively. FIGS. 7A and 7B are graphs showing TFT characteristics when both the threshold voltage of an N-channel TFT and the threshold voltage of a P-channel TFT are shifted to the gate voltage + side. 5 is a graph showing TFT characteristics when both the threshold voltage of an N-channel TFT and the threshold voltage of a P-channel TFT are shifted to the negative gate voltage side.

  In this way, when the physical threshold voltage of the TFT and the threshold voltage in terms of circuit operation are made different in the CMOS circuit, for example, a configuration in which the thickness of the gate insulating film is made different depending on the CMOS circuit, the gate Insulating film with different dielectric constants, Active layer with different semiconductor film thickness, Active layer with different acceptor / donor levels, Active layer grain boundary A configuration in which levels are made different, a configuration in which the channel length is made different and the influence of the short channel effect are made different, and a configuration in which the average grain sizes of the semiconductor films constituting the channel region are made different can be adopted.

  By adopting one or a plurality of such configurations, the TFT constituting one of the CMOS circuits driven at a lower voltage has the characteristics shown in FIG. 3, while the other is higher than the other. With respect to TFTs constituting a CMOS circuit driven by voltage, if the characteristics shown in FIGS. 5A and 5B are used, the physical threshold voltage of the TFT and the threshold voltage in terms of circuit operation are set to CMOS. Can be different in the circuit.

  That is, in the characteristics shown in FIG. 5A, the rise of the drain-source current with respect to the gate voltage (gate-source voltage) is gentle in both the N-channel TFT and the P-channel TFT. The absolute value of the threshold voltage is large.

  On the other hand, in the characteristics shown in FIG. 5B, the rise of the drain / source current with respect to the gate voltage remains unchanged and the enhancement shift occurs in both the N-channel TFT and the P-channel TFT. The absolute value of the threshold voltage is large. When these two characteristics are compared, a TFT using the characteristics shown in FIG. 5B is more preferable because it is easy to ensure a margin for voltage and process fluctuations.

  In order to make the physical threshold voltage of the TFT and the threshold voltage in terms of circuit operation different in the CMOS circuit, as shown in FIGS. 6A and 6B, the threshold value of the P-channel TFT is set. When only the absolute value of the voltage is increased, or on the contrary, when only the absolute value of the threshold voltage of the N-channel TFT is increased, the ON current level of the N-channel TFT and the P-channel TFT are increased. A large difference occurs in the on-current level, so that only the switching in a specific direction is slowed down so that the drive frequency cannot be set high, and malfunction due to timing deviation is likely to occur. Therefore, in any of the first and second embodiments, it is preferable that the difference between the absolute value of the threshold voltage of the N-channel TFT and the absolute value of the threshold voltage of the P-channel TFT is small.

  In order to make the physical threshold voltage of the TFT and the threshold voltage in terms of circuit operation different in the CMOS circuit, the threshold voltage of the N-channel TFT, as shown in FIG. Both of the threshold voltages of the P-channel TFTs are set to the + side, or both of the threshold voltages of the N-channel TFT and the P-channel TFT as shown in FIG. When shifted to the negative side, the leakage current increases when any one of the gate voltages (gate-source voltage) is 0 V, resulting in an increase in current consumption of the circuit and a malfunction. Therefore, in any of the first and second embodiments, it is preferable that both the N-channel TFT and the P-channel TFT are in the enhancement mode. In other words, the threshold voltage of the N-channel TFT is preferably positive, and the threshold voltage of the P-channel TFT is preferably negative.

[Specific configuration of electro-optical device]
(overall structure)
FIG. 8 is a plan view of the electro-optical device to which the present invention is applied as viewed from the side of the counter substrate together with each component formed thereon, and FIG. 9 is a cross-sectional view of FIG. It is H 'sectional drawing. FIG. 10 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels formed in a matrix to form an image display region of the electro-optical device.

  In FIG. 8, the electro-optical device 100 of this embodiment is an active matrix type liquid crystal device, and a sealing material 107 is provided on the TFT array substrate 10 along the edge of the counter substrate 20. A data line driving circuit 101 and a mounting terminal 102 (signal input terminal) are provided along one side of the TFT array substrate 10 in a region outside the sealing material 107, and the scanning line driving circuit 104 is adjacent to the one side. It is formed along two sides. Furthermore, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the image display area 10a. In some cases, a precharge circuit or an inspection circuit is provided. Further, at least one corner portion of the counter substrate 20 is formed with a vertical conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20.

  As shown in FIG. 9, the counter substrate 20 having substantially the same contour as the sealing material 107 shown in FIG. 8 is fixed to the TFT array substrate 10 by this sealing material 107. The sealing material 107 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them.

  As will be described in detail later, pixel electrodes 9 a are formed in a matrix on the TFT array substrate 10. On the other hand, a frame 108 made of a light-shielding material is formed in the inner area of the sealing material 107 on the counter substrate 20, and the inner side is an image display area 10 a. Further, a light shielding film 23 called a black matrix or a black stripe is formed in a region facing vertical and horizontal boundary regions of pixel electrodes (described later) formed on the TFT array substrate 10, and on the upper layer side thereof, A counter electrode 21 made of an ITO film is formed.

  In FIG. 10, in the image display region 10a of the electro-optical device 100, a pixel electrode 9a and a pixel switching TFT 30 for controlling the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix. The data line 6 a for supplying a pixel signal is electrically connected to the source of the TFT 30. Pixel signals S1, S2,... Sn written to the data line 6a are supplied line-sequentially in this order. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,... Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the pixel signal S1, S2,... Sn supplied from the data line 6a is turned on by turning on the TFT 30 as a switching element for a certain period. Are written in each pixel at a predetermined timing. Thus, the pixel signals S1, S2,... Sn at a predetermined level written to the liquid crystal via the pixel electrode 9a are constant with the counter electrode 21 (see FIG. 9) formed on the counter substrate 20. Hold for a period.

  Here, in order to prevent the held pixel signal from leaking, a storage capacitor 70 (capacitor) may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristics are improved, and an electro-optical device capable of performing display with a high contrast ratio can be realized. As a method of forming the storage capacitor 70, there is either a case where it is formed between the capacitor line 3b, which is a wiring for forming a capacitor, or a case where it is formed between the storage line 70 and the preceding scanning line 3a. Also good.

  In the electro-optical device 100 configured as described above, the data line driving circuit 101 includes a shift register 101a, a level shifter 101b, and a video signal transmission gate unit 101c. The shift register 101a and the video signal transmission gate unit 101c And a CMOS circuit including a driving circuit TFT described later. Here, the drive voltage of the CMOS circuit of the shift register 101a is 8V, the drive voltage of the CMOS circuit of the video signal transmission gate unit 101c is 12V, and the drive voltages are different. Therefore, the level shifter 101b performs a level shift from 8V to 12V.

  The scanning line driver circuit 104 includes a shift register 104a and a level shifter 104b. The shift register 104a includes a CMOS circuit including a driver circuit TFT described later. Here, the driving voltage of the CMOS circuit of the shift register 104a is 5V, and the level shifter 104b performs a level shift from 5V to 12V.

  As described above, in the data line driving circuit 101 and the scanning line driving circuit 104, the driving voltages of the CMOS circuits used in the shift register 101a, the video signal transmission gate unit 101c, and the shift register 104a are 8V, 12V, and 5V, respectively. Therefore, in the present embodiment, as described in the first and second embodiments, the threshold corresponding to the driving voltage for each of the CMOS circuits constituting the shift register 101a, the video signal transmission gate unit 101c, and the shift register 104a. A TFT having a value voltage is used. For example, the threshold voltage of the TFT of the data line driving circuit unit is N channel portion + 4V and P channel portion -4V, and the threshold voltage of the TFT of the scanning line driving circuit portion is N channel portion + 2V and P channel portion -2V. do it.

(Pixel configuration)
11A and 11B are plan views of adjacent pixels on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and electro-optics at a position corresponding to the line AA ′. It is explanatory drawing which shows a cross section when an apparatus is cut | disconnected. In these drawings, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.

  11A and 11B, on the TFT array substrate 10 of the electro-optical device 100, a plurality of transparent pixel electrodes 9a (regions surrounded by dotted lines) are formed in a matrix for each pixel. Data lines 6a (shown by alternate long and short dash lines), scanning lines 3a (shown by solid lines), and capacitor lines 3b (shown by solid lines) are formed along the vertical and horizontal boundary regions of the electrodes 9a.

  The base of the TFT array substrate 10 is made of a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the base of the counter substrate 20 is made of a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate. A pixel electrode 9 a is formed on the TFT array substrate 10, and an alignment film 16 made of a polyimide film or the like subjected to a predetermined alignment process such as a rubbing process is formed on the upper side. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is formed by performing a rubbing process on an organic film such as a polyimide film. In the counter substrate 20, an alignment film 22 made of a polyimide film is also formed on the upper layer side of the counter electrode 21, and this alignment film 22 is also a film obtained by rubbing the polyimide film.

  In the TFT array substrate 10, a base insulating film 11 is formed on the surface of the transparent substrate 10b. On the surface side of the TFT array substrate 10, adjacent to each pixel electrode 9a, switching control of each pixel electrode 9a is performed. TFT 30 is formed.

  As shown in FIGS. 11 and 12, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a channel region in which a channel is formed in the semiconductor film 1a by an electric field from the scanning line 3a. 1a ', a low concentration source region 1b, a low concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e are formed. A gate insulating film 2 for insulating the semiconductor film 1a and the scanning line 3a is formed on the upper side of the semiconductor film 1a.

  Interlayer insulating films 4 and 7 made of a silicon oxide film are formed on the surface side of the TFT 30 thus configured. A data line 6 a is formed on the surface of the interlayer insulating film 4, and the data line 6 a is electrically connected to the high concentration source region 1 d through a contact hole 5 formed in the interlayer insulating film 4. A pixel electrode 9 a made of an ITO film is formed on the surface of the interlayer insulating film 7. The pixel electrode 9 a is electrically connected to the drain electrode 6 b through a contact hole 7 a formed in the interlayer insulating film 7, and the drain electrode 6 b is a contact hole formed in the interlayer insulating film 4 and the gate insulating film 2. 8 is electrically connected to the high-concentration drain region 1e. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a.

  Further, the extension portion 1f (lower electrode) extending from the high-concentration drain region 1e has a capacitance in the same layer as the scanning line 3a through an insulating film (dielectric film) formed simultaneously with the gate insulating film 2a. The storage capacitor 70 is configured by the line 3b facing as an upper electrode.

  The TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into regions corresponding to the low concentration source region 1b and the low concentration drain region 1c. . Further, the TFT 30 may be a self-aligned TFT in which impurity ions are implanted at a high concentration using a gate electrode (a part of the scanning line 3a) as a mask to form high-concentration source and drain regions in a self-aligned manner. . In this embodiment, a single gate structure is employed in which only one gate electrode (scanning line 3a) of the TFT 30 is disposed between the source and drain regions. However, two or more gate electrodes may be disposed therebetween. Good. At this time, the same signal is applied to each gate electrode. If the TFT 30 is configured with dual gates (double gates) or triple gates or more in this way, leakage current at the junction between the channel region and the source-drain region can be prevented, and the current during OFF can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.

  In FIG. 11B, in the counter substrate 20, a light shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrode 9a formed on the TFT array substrate 10. A counter electrode 21 made of an ITO film is formed on the upper layer side. Further, an alignment film 22 made of a polyimide film is formed on the upper layer side of the counter electrode 21, and this alignment film 22 is a film obtained by rubbing the polyimide film.

  The TFT array substrate 10 and the counter substrate 20 thus configured are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and the sealing material 53 (see FIG. 8 and FIG. 8) is disposed between these substrates. A liquid crystal 50 as an electro-optical material is sealed and sandwiched in a space surrounded by (see FIG. 9). The liquid crystal 50 takes a predetermined alignment state by the alignment film in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal 50 is made of, for example, one or a mixture of several types of nematic liquid crystals.

(Configuration of peripheral circuit)
8 and 10 again, in the electro-optical device 100 according to the present embodiment, the data line driving circuit 101 and the scanning line driving circuit 104 are formed using the peripheral area of the image display area 10a on the surface side of the TFT array substrate 10. Is formed. The data line driving circuit 101 and the scanning line driving circuit 104 are basically composed of an N-channel TFT and a P-channel TFT shown in FIGS. 12A and 12B.

  12A and 12B are a plan view showing a configuration of a complementary inverter circuit using TFTs constituting peripheral circuits such as the scanning line driving circuit 104 and the data line driving circuit 101, and TFTs constituting the inverter circuit. It is sectional drawing when cut | disconnecting by BB 'line. FIG. 12B also shows a pixel switching TFT 30 formed in the image display region 10 a of the TFT array substrate 10.

  In FIGS. 12A and 12B, the TFT constituting the peripheral circuit is configured as a CMOS TFT composed of a P-channel TFT 80 and an N-channel TFT 90. The semiconductor film 60 (the outline is indicated by a dotted line in FIG. 12A) constituting the TFTs 80 and 90 for the drive circuit is formed in an island shape on the surface of the base insulating film 11 of the transparent substrate 10b.

  High potential lines 71 and low potential lines 72 are electrically connected to the source regions of the semiconductor film 60 through the contact holes 63 and 64, respectively, to the TFTs 180 and 190. The input wiring 66 is connected to the common gate electrode 65, and the output wiring 67 is electrically connected to the drain region of the semiconductor film 60 via the contact holes 68 and 69.

  Since such a peripheral circuit region is also formed through a process similar to that of the image display region 10a, the interlayer insulating films 4 and 5 and the gate insulating film 2 are also formed in the peripheral circuit region. Similarly to the pixel switching TFT 30, the driving circuit TFTs 80 and 90 have an LDD structure, and high-concentration source regions 82 and 92 and low-concentration source regions 83 are provided on both sides of the channel regions 81 and 91. , 93 and high-concentration drain regions 84, 94 and low-concentration drain regions 85, 95.

(Basic configuration of TFT array substrate manufacturing method)
13 to 15 are process cross-sectional views illustrating the method for manufacturing the TFT array substrate 10 of the present embodiment. 13 to 15 each correspond to a cross section of a portion corresponding to FIG.

  First, as shown in FIG. 13 (A), after preparing a transparent substrate 10b made of glass or the like cleaned by ultrasonic cleaning or the like, a substrate temperature is 150 ° C. to 450 ° C. under a plasma CVD method, A base insulating film 11 made of a silicon oxide film having a thickness of 300 nm to 500 nm is formed on the surface of the transparent substrate 10b (base insulating film forming step).

  Next, the semiconductor film 1 made of an amorphous silicon film is formed on the surface of the base insulating film 11 by a plasma CVD method under a temperature condition of a substrate temperature of 150 ° C. to 450 ° C. (semiconductor film forming step). Here, a small amount of phosphorus or boron ions may be implanted into the silicon film in order to introduce an impurity for adjusting the threshold voltage as necessary (channel doping).

  Next, laser annealing is performed by irradiating the semiconductor film 1 with laser light, and after the amorphous semiconductor film is melted once, it is crystallized through a cooling and solidifying process (laser annealing process). At this time, the irradiation time of the laser beam to each region is very short, and the irradiation region is also local to the entire substrate, so that the entire substrate is not heated to a high temperature at the same time. Therefore, even if a glass substrate or the like is used as the transparent substrate 10b, deformation or cracking due to heat does not occur. As a source gas for forming the semiconductor film 1, for example, disilane or monosilane can be used.

  Next, as illustrated in FIG. 13B, a resist mask 402 is formed on the surface of the semiconductor film 1 using a photolithography technique, and the semiconductor film 1 is etched through the resist mask 402, whereby FIG. As shown in (C), island-shaped semiconductor films 1a and 60 are formed.

  Next, as shown in FIG. 13E, the gate insulating film 2 made of a silicon oxide film is formed on the surface of the transparent substrate 10b (gate insulating film forming step).

  Next, although not shown, impurity ions are implanted into the extended portion 1f of the semiconductor film 1a through a predetermined resist mask to form a lower electrode for forming the storage capacitor 70 between the capacitor line 3b. To do.

  Next, as shown in FIG. 14F, an electrically conductive film made of an aluminum film, a tantalum film, a molybdenum film, or an alloy film containing any one of these metals as a main component is formed on the entire surface of the transparent substrate 10b by sputtering or the like. After the film 3 is formed to a thickness of 300 nm to 800 nm, a resist mask 402 is formed using a photolithography technique, and the conductive film is dry-etched through the resist mask 402. As a result, as shown in FIG. 14G, the scanning line 3a, the gate electrode 65, and the capacitor line 3b are formed.

Next, as shown in FIG. 14H, the semiconductor film 1a for forming the pixel switching TFT 30 in the state where the semiconductor film 60 for forming the P-channel TFT 80 is covered with the resist mask 411, and the driving About 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² with respect to the semiconductor film 60 constituting the N-channel TFT 90 for a circuit, using the scanning line 3a and the gate electrode 165 as a mask. Low-concentration N-type impurity ions (phosphorus ions) are implanted at a dose to form low-concentration source regions 1b and 93 and low-concentration drain regions 1c and 95 in a self-aligned manner with respect to the scanning line 3a and the gate electrode 65. . Here, since it is located directly below the scanning line 3a and the gate electrode 65, the portion into which the impurity ions are not introduced becomes the channel regions 1a ′ and 91 that remain as intrinsic semiconductor films.

Next, as shown in FIG. 14I, a resist mask 412 which is wider than the scanning line 3a and the gate electrode 66 and covers the semiconductor film 60 for forming the P-channel TFT 80 is formed. In this state, high-concentration N-type impurity ions (phosphorus ions) are implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² , and the high-concentration source regions 1 d and 92, and the drain region 1e and 94 are formed.

Next, as shown in FIG. 14J, a P-channel driver circuit for a driver circuit is formed in a state where the semiconductor films 1a and 60 for forming the N-channel TFTs 30 and 90 are covered with a resist mask 413. Low concentration impurity ions (boron) at a dose of about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² with respect to the semiconductor film 60 constituting the TFT 80 for use as a mask. Ions) are implanted to form a low concentration source region 83 and a low concentration drain region 85 in a self-aligned manner with respect to the gate electrode 65. Here, since it is located directly under the gate electrode 65, the portion where the impurity ions are not introduced becomes the channel region 81 that remains in the semiconductor film 60.

Next, as shown in FIG. 14K, a resist mask 414 that is wider than the gate electrode 65 and covers the semiconductor films 1a and 60 for forming the N-channel TFTs 30 and 90 is formed. In this state, high-concentration P-type impurity ions (boron ions) are implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² , and the high-concentration source region 82 and drain region 84 are implanted. Form.

  In place of these impurity introduction steps, high concentration impurities (phosphorus ions) are implanted in a state where a resist mask wider than the gate electrode is formed without implanting the low concentration impurities, and the source and drain regions of the offset structure May be formed. Needless to say, high-concentration impurities may be implanted using the scanning line 3a and the gate electrode as a mask to form a source region and a drain region having a self-aligned structure.

  Next, as shown in FIG. 15L, after an interlayer insulating film 4 made of a silicon oxide film or the like is formed on the entire surface of the transparent substrate 10b, a resist is formed on the surface of the interlayer insulating film 4 using a photolithography technique. A mask is formed, and the interlayer insulating film 4 is etched from the opening of the resist mask to form contact holes 63, 64, 68, 69, etc., and then the resist mask is removed.

  Next, as shown in FIG. 15M, after a conductive film 6 such as an aluminum film, a tantalum film, or a molybdenum film is formed to a thickness of 300 nm to 800 nm by a sputtering method or the like, a resist mask is used using a photolithography technique. 405 is formed, and the conductive film 6 is dry-etched through the resist mask 405 to form the data line 6a, the drain electrode 6b, and the like on the surface side of the interlayer insulating film 4 as shown in FIG. To do.

  Through the above steps, N-channel and P-channel TFTs can be formed on the TFT array substrate. In addition, since it is only necessary to form each layer shown in FIG. 12B by a known method after that, description thereof is omitted.

[TFT configuration and manufacturing method 1 for each CMOS circuit]
In this embodiment, when the threshold voltage of the TFT constituting the CMOS circuit is made different between the first CMOS circuit and the second CMOS circuit, the film thickness or film quality of the gate insulating film 2 is made different for each region. With this configuration, the absolute value of the threshold voltage of the TFT having the thicker gate insulating film 2 can be increased even with the same conductivity type.

  Specifically, after forming the gate insulating film 2 in the gate insulating film forming step (insulating film forming step) shown in FIG. 13E, an etching mask is formed by photolithography in the insulating film etching step. Then, the gate insulating film 2 is etched from the opening of the etching mask to selectively change the film thickness of a predetermined region of the gate insulating film 2.

  At that time, after forming a first insulating film for forming the gate insulating film 2 in the first insulating film forming process as the insulating film forming process, a predetermined region of the first insulating film is formed in the insulating film etching process. After selectively etching to partially thin the first insulating film, or after partially removing the first insulating film, the second insulating film forming step is again performed as the insulating film forming step. The thickness of the gate insulating film 2 may be changed for each region by forming a second insulating film for forming the gate insulating film 2 on the surface side of the first insulating film.

  When the gate insulating film forming step shown in FIG. 13E is performed, the first insulating film for forming the gate insulating film 2 is formed in the first insulating film forming step, and then the second insulating film is formed. A second insulating film for forming the gate insulating film 2 is formed on the surface side of the first insulating film in the forming process, and then a predetermined region of the second insulating film is selectively selected in the insulating film etching process. The gate insulating film 2 may be partially thinned or the gate insulating film 2 may be partially removed by etching.

  At that time, insulating films having different film qualities may be formed as the first gate insulating film and the second gate insulating film. As the gate insulating films having different film qualities, for example, a silicon oxide film is used as the first gate insulating film, and a silicon nitride film is used as the second gate insulating film. Thereby, in the first CMOS circuit and the second CMOS circuit, the threshold voltage can be made different by making the dielectric constant of the gate insulating film 2 of the TFT different.

[Configuration of TFT for each CMOS circuit and manufacturing method 2]
In this embodiment, the thickness of the semiconductor film 1 constituting the active layer of the TFT is changed for each region in order to make the threshold voltage of the TFT constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit. . Even in such a configuration, the absolute value of the threshold voltage of the TFT having the thicker semiconductor film 1 can be increased.

  Specifically, a predetermined region of the semiconductor film 1 is selectively oxidized or etched to adjust the thickness of the semiconductor film 1.

  More specifically, after forming the semiconductor film 1 for forming the channel regions 81, 91, 1a ′ in the step shown in FIG. 13A (semiconductor film forming step), an etching mask is formed by photolithography. Then, the semiconductor film 1 is etched from the opening of the etching mask to partially thin the semiconductor film 1 (semiconductor film thickness adjusting step). In this case, the semiconductor film thickness adjustment step may be performed before or after the laser annealing step.

  13A, after forming the first semiconductor film constituting the semiconductor film 1 (first semiconductor film forming process), an etching mask is formed using a photolithography technique. The semiconductor film 1 is etched from the opening of the etching mask to partially thin or remove the semiconductor film 1 (semiconductor film thickness adjusting step), and then again on the surface side of the first semiconductor film Alternatively, an amorphous second semiconductor film for forming the channel regions 81, 91, 1a 'may be formed (second semiconductor film forming step). In this case, a laser annealing process is performed after the second semiconductor film forming process. At this time, not only the effect due to the difference in film thickness of the semiconductor layer but also the laser annealing is performed on the semiconductor film with different film thickness under the same conditions, and the effect of threshold fluctuation due to the difference in film quality of the semiconductor layer can be expected.

  Further, instead of changing the film thickness of the semiconductor film 1 using the etching technique, the surface of the semiconductor film 1 may be partially oxidized by oxygen plasma or ozone oxidation to partially change the film thickness of the semiconductor film 1. Good. In this case, since the film thickness of the gate insulating film 2 can be partially changed, a threshold fluctuation effect due to the difference in the gate insulating film can also be expected. In addition, if the oxidation process is performed before laser annealing, the film quality of the semiconductor layer varies depending on the surface state, so that a threshold fluctuation effect due to the film quality of the semiconductor layer can be expected.

[Configuration of TFT for each CMOS circuit and manufacturing method 3]
In this embodiment, when the threshold voltage of the TFT constituting the CMOS circuit is made different between the first CMOS circuit and the second CMOS circuit, the film quality of the semiconductor film 1 constituting the channel regions 81, 91, 1a 'of the TFT. Is changed for each region.

  Specifically, after forming the amorphous semiconductor film 1 for forming the channel regions 81, 91, 1 a ′ (semiconductor film forming process) in the process shown in FIG. On the other hand, excimer laser annealing is performed under different conditions for each region to crystallize the semiconductor film 1 (laser annealing step).

  For example, when laser annealing the amorphous semiconductor film 1, the irradiation energy or the overlapping rate at the time of irradiation scanning, the energy profile of the laser irradiation beam, or the number of times of laser light irradiation (number of scans) are changed for each region. A difference is generated in the grain size of the semiconductor film 1 after the polycrystallization and the defect density in the grain boundary. Therefore, the threshold voltage of the TFT can be made different for each region.

  Further, the laser annealing is performed in combination with the above conditions, and the grain size of the semiconductor film 1 after polycrystallization and the defect density in the grain boundary are caused to vary, and the threshold voltage of the TFT differs depending on the region. You may let them.

[Configuration and Manufacturing Method 4 of TFT for Each CMOS Circuit]
In this embodiment, in order to make the threshold voltages of TFTs constituting a CMOS circuit different between the first CMOS circuit and the second CMOS circuit, first, in the base insulating film forming step shown in FIG. Then, the base insulating film 11 having different film quality or film thickness is formed. In the case of forming the base insulating film 11 having a different thickness, after the base insulating film 11 is formed, an etching mask is formed by photolithography, and the base insulating film 11 is etched from the opening of the etching mask. The insulating film 11 is partially removed or partially thinned. Further, after the base insulating film 11 is partially thinned or removed, a base insulating film may be formed on the upper layer of the base insulating film 11 to change the thickness of the base insulating film 11 for each region.

  Next, after the amorphous semiconductor film 1 for forming the channel regions 81, 91, 1 a ′ is formed on the surface side of the base insulating film 11 (semiconductor film forming step), excimer laser annealing is performed on the semiconductor film 1. Then, the semiconductor film 1 is polycrystallized (laser annealing step), and the film quality of the polycrystalline semiconductor film 1 constituting the channel regions 81, 91, 1a 'is made different for each region.

  With this configuration, when the amorphous semiconductor film 1 is laser-annealed, the heat conduction and the laser reflection intensity differ from region to region due to the difference in thickness and film quality of the base insulating film 11, and therefore the same irradiation. Even when polycrystallization is performed by laser annealing with energy, a difference occurs in the grain size of the polycrystalline semiconductor film 1 and the defect density in the grain boundary. Therefore, the threshold voltage of the TFT can be made different for each CMOS circuit, and a balance with the driving voltage can be secured.

  Further, when the base insulating film 11 is formed, a first base insulating film and a second base insulating film having a film quality different from that of the first base insulating film are sequentially formed, and then an etching mask is formed by photolithography. The second base insulating film stacked on the upper layer side may be etched from the opening of the etching mask to partially thin the base insulating film 11.

  In this case, as the base insulating film having different film quality, an N (nitrogen) rich insulating film and an O (oxygen) rich insulating film may be used in the Si—O—N-based compound. The film 11 is composed of silicon compounds in which the content ratio of nitrogen and oxygen in the outermost layer is different for each region. In addition, as the base insulating film having different film quality, films having different etching rates of HF (hydrofluoric acid) used for etching may be used in the Si—O-based compound.

[Configuration and Manufacturing Method 5 of TFT for Each CMOS Circuit]
In this embodiment, in order to make the threshold voltages of the TFTs constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit, before the base insulating film forming step shown in FIG. After the film is formed, the metal film is left only in a predetermined region by using a photolithography technique (underlying metal film forming process), and then the underlying insulating film 11 is formed in the underlying insulating film forming process. Next, an amorphous semiconductor film 1 for forming channel regions 81, 91, 1 a ′ is formed on the surface side of the base insulating film 11 (semiconductor film forming step), and then an excimer laser is applied to the semiconductor film 1. Annealing is performed to crystallize the semiconductor film 1 (laser annealing step).

  Even when configured in this way, when the amorphous semiconductor film 1 is laser annealed, the laser reflection intensity varies depending on the presence or absence of the metal film. Differences occur in the grain size of the semiconductor film 1 and the defect density in the grain boundary. Therefore, the threshold voltage of the TFT can be made different for each region.

  Note that when problems such as securing adhesion occur, the above-described steps may be performed after an insulating film is formed further below the base metal film. Of course, the base metal film may also be used as the light shielding layer or the lower capacitance line.

[Configuration of TFT for each CMOS circuit and manufacturing method 6]
In this embodiment, in order to make the threshold voltages of TFTs constituting a CMOS circuit different between the first CMOS circuit and the second CMOS circuit, insulating films having different thicknesses are formed on the surface of the semiconductor film 1 for each region. Thereafter (insulating film forming step), the semiconductor film 1 is subjected to excimer laser annealing to crystallize the semiconductor film 1 (laser annealing step).

  Thus, if the surface state of the semiconductor film 1 when the semiconductor film 1 is laser-annealed with the insulating film is made different, the crystallization speed of the semiconductor film 1 in the laser annealing can be made different. Thereby, a difference can be generated in the grain size of the semiconductor film 1 after the polycrystallization and the defect density in the grain boundary, so that the threshold voltage of the TFT can be made different for each region.

  In adopting such a configuration, for example, before laser annealing the semiconductor film 1, laser annealing is performed after partially oxidizing the surface of the silicon film by oxygen plasma or ozone oxidation.

[Configuration of TFT for each CMOS circuit and manufacturing method 7]
In this embodiment, when the threshold voltage of the TFT constituting the CMOS circuit is made different between the first CMOS circuit and the second CMOS circuit, the amorphous semiconductor for constituting the channel regions 81, 91, 1a ' After the film 1 is formed (semiconductor film forming process), the semiconductor film 1 is subjected to excimer laser annealing to crystallize the semiconductor film 1 (laser annealing process), and then selectively applied to a predetermined region of the semiconductor film 1. An inert element is introduced (inert element introduction step), the crystallinity of the semiconductor film 1 after laser annealing is made different for each region, and the defect level of the semiconductor film 1 is made different for each region.

  In adopting such a configuration, a mask is formed on the surface of the silicon film after laser annealing by photolithography, and argon, helium, oxygen, silicon, carbon, and carbon are formed from the opening of the mask to the semiconductor film 1. A relatively inert ion such as is implanted to partially destroy the crystal.

[Configuration of TFT for each CMOS circuit and manufacturing method 8]
In this embodiment, channel doping is used to make the threshold voltage of the TFTs constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit. That is, in the first CMOS circuit and the second CMOS circuit, the impurity concentrations of the channel regions 81, 91, 1a ′ are made different to make the threshold voltages of the TFTs different.

  Specifically, in a CMOS circuit with a higher driving voltage using a mask formed by photolithography, a relatively high concentration of boron is doped in the channel region of the N-channel TFT, and the P-channel TFT The channel region is doped with a relatively high concentration of phosphorus.

  On the other hand, in the CMOS circuit with the lower driving voltage, the channel region of the N-channel TFT is doped with a relatively low concentration of boron, and the channel region 1a of the P-channel TFT is doped with a relatively low concentration of phosphorus. Dope. Note that in the CMOS circuit with the lower drive voltage, channel doping is omitted, for example, one of the N-channel TFT and the P-channel TFT in each of the first CMOS circuit and the second CMOS circuit, or Channel doping may be omitted for a plurality of regions. In the CMOS circuit with the lower drive voltage, the ion species to be implanted may be reversed between the N channel region and the P channel region.

  Such channel doping may be performed in a state where an insulating film is formed on the surface of the semiconductor film 1 or in a state where no insulating film is formed, or at any timing before and after crystallization by laser annealing. It doesn't matter.

[Configuration of TFT for each CMOS circuit and manufacturing method 9]
Also in this embodiment, channel doping is used to make the threshold voltage of the TFT constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit. In other words, in the first CMOS circuit and the second CMOS circuit, the impurity concentration of the channel region is made different to make the threshold voltage of the TFT different.

  For this purpose, an insulating film having a different film thickness is formed on the surface side of the semiconductor film 1 constituting the channel regions 81, 91, 1a ′ (insulating film forming step), and in this state, the semiconductor film is interposed via the insulating film. Impurity ions are introduced into 1 (channel dope process).

  Thus, if the film thickness of the insulating film on the surface of the semiconductor film 1 is changed for each region, the impurity concentration for each region can be accurately adjusted while reducing the number of times of photolithography by controlling the ion acceleration voltage. Can be controlled. In this case, the insulating film may be used as the gate insulating film 2 or a part of the gate insulating film 2, or the gate insulating film 2 may be re-formed after the insulating film is removed.

  Further, channel doping may be performed at any timing before and after crystallization by laser annealing, or may be performed after the gate insulating film forming step.

[TFT configuration and manufacturing method 10 for each CMOS circuit]
In the TFT manufacturing method, after introducing an impurity for forming a source / drain region or an impurity for channel doping and then performing an activation treatment (heat treatment / activation step), channel regions 81, 91, 1a In ′, since the grain boundary defect density is lowered, the threshold voltage is lowered. On the other hand, when channel doping is performed on the channel regions 81, 91, and 1a ', the threshold voltage may be increased if an activation process (heat treatment) is performed.

  Therefore, in this embodiment, in order to make the threshold voltages of the TFTs constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit, after the process shown in FIG. Therefore, the heat treatment conditions (temperature applied to the silicon film and treatment time) are changed for each region.

  Specifically, laser annealing is performed as an activation process, and irradiation conditions are changed for each region. Further, after annealing the entire substrate, laser annealing as an activation process may be performed only on a predetermined region.

[TFT configuration and manufacturing method 11 for each CMOS circuit]
In the TFT manufacturing method, when each layer such as an interlayer insulating film is formed on the upper layer side of the TFT and then hydrogenated (hydrogen ion introduction step), the grain boundary of the silicon film constituting the TFT channel region is obtained. The dangling bond existing in the substrate can be compensated, and as a result, the grain boundary defect density is lowered, and the threshold voltage is lowered.

  Therefore, in this embodiment, the hydrogenation conditions are changed for each region in order to make the threshold voltage of the TFT constituting the CMOS circuit different between the first CMOS circuit and the second CMOS circuit.

  Specifically, the layer structure of the insulating film or metal film on the upper layer side of the TFT channel regions 81, 91, 1a ′ is made different for each region, and the entire surface of the substrate is subjected to hydrogenation in the hydrogen ion introduction process. The degree of hydrogenation for the channel region of the TFT is made different for each region.

  Further, before performing hydrogenation, a mask is formed by a photolithography technique, and by performing hydrogenation in this state, when the entire surface of the substrate is subjected to hydrogenation treatment, the channel regions 81, 91, 1a ′ of the TFTs are formed. The degree of hydrogenation is different for each region.

  In addition, in the case of introducing various halogen ions, for example, fluorine ions, in place of hydrogen ions for compensating for dangling bonds, the same effect can be expected.

[Other embodiments]
In the TFT, when the channel length (gate length) is shorter than a certain level, the threshold voltage as a whole is lowered by the short channel effect. Therefore, when the threshold voltage of the TFT constituting the CMOS circuit is made different between the first CMOS circuit and the second CMOS circuit, the channel length (gate length) may be made different for each region in combination with the above embodiment. Good. When such a short channel effect is used, the channel length (gate length) is set to 4 μm or less.

  In the above embodiment, the CMOS circuits formed in the scanning line driving circuit and the data line driving circuit are described as examples of the first CMOS circuit and the second CMOS circuit having different driving voltages. In some cases, switching TFTs constitute a CMOS circuit. In such a case, one of the first CMOS circuit and the second CMOS circuit may be used for pixel switching, and the other CMOS circuit may be used for the drive circuit.

  In the above embodiment, an active matrix liquid crystal device with a built-in driving circuit is described as an example of the electro-optical device. However, an electro-optical device using an electro-optical material other than liquid crystal, for example, see FIGS. 16 and 17. The present invention may be applied to the manufacture of a TFT array substrate used in an organic electroluminescence display device described below, or a thin film semiconductor device other than an electro-optical device.

  Furthermore, the present invention is not limited to the above-described embodiment, and may be applied to a thin film transistor or a bottom gate type transistor using amorphous silicon, or an electro-optical device is formed on a silicon wafer instead of an insulating substrate. It can also be applied to. Also, as a built-in circuit form, not only a simple circuit such as a shift register, but also a built-in DAC circuit or decoder circuit for digital / analog conversion of a video signal, or a graphic memory, and a sophisticated circuit such as a CPU are incorporated. You may do it.

  FIG. 16 is a block diagram of an active matrix type electro-optical device using a charge injection type organic thin film electroluminescence element. 17A and 17B are an enlarged plan view and a cross-sectional view, respectively, showing a pixel region formed in the electro-optical device shown in FIG.

  The electro-optical device 100p shown in FIG. 16 is an active matrix type that drives and controls a light emitting element such as an EL (electroluminescence) element or an LED (light emitting diode) element that emits light when a driving current flows through an organic semiconductor film. Since all of the light-emitting elements that are display devices and are used in this type of electro-optical device self-emit, there is an advantage that a backlight is not required and that the viewing angle dependency is small.

  In the electro-optical device 100p shown here, on the TFT array substrate 10p, a plurality of scanning lines 3p, a plurality of data lines 6p extending in a direction intersecting with the extending direction of the scanning lines 3p, and these A plurality of common power supply lines 23p parallel to the data lines 6p and a pixel region 15p corresponding to the intersection of the data lines 6p and the scanning lines 3p are configured. For the data line 6p, a data side driving circuit 101p including a shift register, a level shifter, a video line, and an analog switch is configured. A scanning side drive circuit 104p including a shift register and a level shifter is configured for the scanning line 3p.

  Each pixel region 15p holds a first TFT 31p to which a scanning signal is supplied to the gate electrode via the scanning line 3p, and an image signal supplied from the data line 6p via the first TFT 31p. A storage capacitor 33p to be connected, a second TFT 32p (thin film semiconductor element) to which an image signal held by the storage capacitor 33p is supplied to the gate electrode, and a common power supply line 23p through the second TFT 32p. Thus, a light emitting element 40p into which a driving current flows from the common power supply line 23p is configured.

  In this embodiment, as shown in FIGS. 17A and 17B, in any pixel region 15p, a base insulating film 11p is formed on the surface of a substrate 10p ′ made of glass or the like, and this base insulating film is formed. A first TFT 31p and a second TFT 32p are formed using two semiconductor films formed in an island shape on the surface of the film 11p. Further, the relay electrode 35p is electrically connected to one of the source / drain regions of the second TFT 32p, and the pixel electrode 41p is electrically connected to the relay electrode 35p. On the upper side of the pixel electrode 41p, a hole injection layer 42p, an organic semiconductor film 43p as an organic electroluminescence material layer, and a counter electrode 20p made of a metal film such as lithium-containing aluminum or calcium are stacked. Here, the counter electrode 20p is formed over the plurality of pixel regions 15p across the data line 6p and the like.

  A common power supply line 23p is electrically connected to the other of the source / drain regions of the second TFT 32p through a contact hole. On the other hand, in the first TFT 31p, the potential holding electrode 35p electrically connected to one of the source / drain regions is electrically connected to the extended portion 720p of the second gate electrode 72p. The extended portion 720p is opposed to the semiconductor film 400p via the second gate insulating film 50p on the lower layer side, and the semiconductor film 400p is made conductive by the impurities introduced therein. A storage capacitor 33p is formed together with the extended portion 720p and the second gate insulating film 50p. Here, the common power supply line 23p is electrically connected to the semiconductor film 400p through a contact hole of the interlayer insulating film 51p.

  Therefore, since the storage capacitor 33p holds the image signal supplied from the data line 6p via the first TFT 31p, even if the first TFT 31p is turned off, the gate electrode 31p of the second TFT 32p is not connected to the image signal. Is held at a potential corresponding to. Therefore, since the drive current continues to flow from the common power supply line 23p to the light emitting element 40p, the light emitting element 40p continues to emit light and displays an image.

  Also in the TFT array substrate 10p of the electro-optical device 100p, the driving voltage is applied to the data side driving circuit 101p including the shift register, the level shifter, the video line, and the analog switch, and the scanning side driving circuit 104p including the shift register and the level shifter. Different CMOS circuits are formed by TFTs. Accordingly, even in the electro-optical device 100p, if the balance between the drive voltage and the sum of the threshold voltages of the TFTs is ensured for each CMOS circuit, malfunction of the CMOS circuit can be prevented.

[Application to electronic devices]
Next, an example of an electronic apparatus including the electro-optical devices 100 and 100p to which the present invention is applied will be described with reference to FIGS.

  18A and 18B are an explanatory diagram of a mobile personal computer as an example of an electronic apparatus using the electro-optical device according to the invention and an explanatory diagram of a mobile phone, respectively.

  Examples of the electronic apparatus on which the electro-optical device to which the present invention is applied include a projection type liquid crystal display device (liquid crystal projector), a multimedia-compatible personal computer (PC), an engineering work station (EWS), a pager, or a portable device. Examples include a telephone, a word processor, a television, a viewfinder type or a monitor direct-view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, a touch panel, and the like. For example, as shown in FIG. 18A, the personal computer 180 includes a main body 182 provided with a keyboard 181 and a display unit 183. The display unit 183 includes the electro-optical devices 100 and 100p described above. As shown in FIG. 18B, the mobile phone 190 includes a plurality of operation buttons 191 and a display unit including the electro-optical devices 100 and 100p described above.

  As described above, in the present invention, in a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode constituting a channel region are formed, the gate insulating film or A plurality of field effect transistors are formed over the same substrate with different thicknesses and film qualities of the semiconductor layers constituting the channel region for each region. For this reason, field effect transistors having different threshold voltages for each region can be formed on the same substrate, so that a complementary circuit or the like can be configured by field effect transistors having a threshold voltage corresponding to the drive voltage. . For example, in the first and second complementary circuits having different driving voltages, the absolute value of the threshold voltage of an N-channel field effect transistor and the absolute value of the threshold voltage of a P-channel field effect transistor are It is possible to make the sum different by making it correspond to the driving voltage and to make it suitable. For this reason, in order to achieve high-speed operation, even when the threshold voltage of the field effect transistor is lowered, the balance between the drive voltage and the threshold voltage is ensured in each complementary circuit. Therefore, no malfunction occurs in the complementary circuit. In particular, in an electro-optical device, although there is no space in spite of driving a large number of pixels, the wiring is considerably miniaturized, so that the wiring width is narrow although the driving frequency is high. In this case, the input signal waveform is apt to be distorted, but even in such a case, no malfunction occurs in the complementary circuit. Therefore, in the electro-optical device, high reliability can be ensured even when the number of pixels is increased, the operation speed is increased, and the power consumption is reduced.

(A) and (B) are explanatory diagrams of an inverter circuit using a CMOS circuit and a clocked inverter circuit, respectively. (A), (B), and (C) are waveform diagrams showing the relationship between the input signal and the output signal for the CMOS circuit, respectively. It is explanatory drawing of threshold voltage Von-off in the circuit operation | movement surface of TFT. It is a graph which shows a response | compatibility with the threshold voltage Von-off in the circuit operation surface in TFT, and the physical threshold voltage Vth based on formation of an inversion layer. (A) and (B) show the absolute value of the threshold voltage in both the N-channel TFT and the P-channel TFT by slowing the rise of the drain-source current with respect to the gate voltage (gate-source voltage). The graph showing the TFT characteristics when the value is increased and the rise of the drain-source current with respect to the gate voltage in both the N-channel TFT and the P-channel TFT remain unchanged, and as a result, It is a graph which shows the TFT characteristic when the absolute value of threshold voltage is enlarged. 4 is a graph showing TFT characteristics when only the absolute value of the threshold voltage of a P-channel TFT is increased, and a graph showing TFT characteristics when only the absolute value of the threshold voltage of an N-channel TFT is increased. . (A) and (B) are graphs showing TFT characteristics when both the threshold voltage of an N-channel TFT and the threshold voltage of a P-channel TFT are shifted to the + side, and an N-channel TFT It is a graph which shows the TFT characteristic at the time of shifting both the threshold voltage of TFT and the threshold voltage of P channel type TFT to-side. 1 is a plan view of a liquid crystal device (electro-optical device) to which the present invention is applied, as viewed from the side of a counter substrate together with components formed thereon. It is HH 'sectional drawing of FIG. FIG. 9 is an equivalent circuit diagram of various elements and wirings formed in a plurality of pixels arranged in a matrix in the image display region of the electro-optical device shown in FIG. 8. 8A and 8B are plan views showing the configuration of each pixel formed on the TFT array substrate in the electro-optical device shown in FIG. 8, and the electro-optical device cut at a position corresponding to the line AA ′. It is sectional drawing when doing. FIGS. 9A and 9B are a plan view of a circuit formed in a peripheral region of an image display region of the electro-optical device shown in FIG. 8 and a cross-sectional view of a TFT for a drive circuit. (A)-(E) are process sectional drawings which show the manufacturing method of the TFT array substrate used for the electro-optical apparatus shown in FIG. FIGS. 10F to 10K are process cross-sectional views illustrating a manufacturing method of the TFT array substrate used in the electro-optical device illustrated in FIG. (L)-(N) are process sectional drawings which show the manufacturing method of the TFT array substrate used for the electro-optical apparatus shown in FIG. It is a block diagram of an active matrix type electro-optical device using a charge injection type organic thin film electroluminescence element. FIGS. 17A and 17B are a plan view and a cross-sectional view, respectively, showing an enlarged pixel region formed in the electro-optical device shown in FIG. 1A and 1B are an explanatory diagram showing a mobile personal computer as an embodiment of an electronic apparatus using an electro-optical device according to the present invention, and an explanatory diagram of a mobile phone, respectively.

Explanation of symbols

1a semiconductor film, 2 gate insulating film, 3a scanning line, 3b capacitance line, 4, 7 interlayer insulating film, 6a data line, 6b drain electrode, 9a pixel electrode, 10, 10p TFT array substrate (thin film semiconductor device), 30, 31p, 32p, 80, 90 TFT (field effect transistor), 100, 100p electro-optical device

Claims (24)

In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
Performing at least an insulating film forming step of forming an insulating film for constituting the gate insulating film and an insulating film etching step of selectively etching a predetermined region of the insulating film;
A method of manufacturing a semiconductor device, wherein a first field effect transistor and a second field effect transistor having the same conductivity type and different gate insulating film thicknesses are formed on the same substrate. In claim 1,
After forming the first insulating film for constituting the gate insulating film in the first insulating film forming step as the insulating film forming step,
Selectively etching a predetermined region of the first insulating film in the insulating film etching step;
Next, again, a second insulating film for forming the gate insulating film is formed on the surface side of the first insulating film in a second insulating film forming step as the insulating film forming step. A method for manufacturing a semiconductor device. In claim 1 or 2,
After forming the first insulating film for constituting the gate insulating film in the first insulating film forming step as the insulating film forming step,
Again, in the second insulating film forming step as the insulating film forming step, a second insulating film for forming the gate insulating film is formed on the surface side of the first insulating film,
Next, a method of manufacturing a semiconductor device, wherein a predetermined region of the second insulating film is selectively etched in the insulating film etching step. In claim 2 or 3,
The method of manufacturing a semiconductor device, wherein the first insulating film and the second insulating film have different dielectric constants. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
A semiconductor film formation step for forming at least a semiconductor film for constituting the channel region, and a semiconductor film thickness adjustment for adjusting a thickness of the semiconductor film by selectively oxidizing or etching a predetermined region of the semiconductor film Process and
Manufacturing a semiconductor device, wherein a first field effect transistor and a second field effect transistor having the same conductivity type and different thicknesses of a semiconductor film constituting the channel region are formed on the same substrate. Method. In claim 5,
After forming the first semiconductor film for forming the channel region in the first semiconductor film forming process as the semiconductor film forming process,
Selectively etching a predetermined region of the first semiconductor film in the semiconductor film thickness adjustment step;
Next, again, a second semiconductor film for forming the channel region is formed on the surface side of the first semiconductor film in a second semiconductor film forming process as the semiconductor film forming process. A method for manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
A semiconductor film forming step of forming at least a semiconductor film for constituting the channel region; and a laser annealing step of crystallizing the semiconductor film by performing excimer laser annealing on the semiconductor film under different conditions for each region. And
Forming a first field effect transistor and a second field effect transistor having the same conductivity type and different defect density or defect level distribution state of a semiconductor film constituting the channel region on the same substrate; A method of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
A base insulating film forming step of forming at least a base insulating film having a different film quality or thickness for each region; and a semiconductor film forming step of forming a semiconductor film for forming the channel region on the surface side of the base insulating film; Performing a laser annealing step of crystallizing the semiconductor film by performing excimer laser annealing on the semiconductor film,
Forming a first field effect transistor and a second field effect transistor having the same conductivity type and different defect density or defect level distribution state of a semiconductor film constituting the channel region on the same substrate; A method of manufacturing a semiconductor device. In claim 8,
The method for manufacturing a semiconductor device, wherein the base insulating film is made of a silicon compound in which the content ratio of nitrogen and oxygen in the outermost layer is different for each region. In claim 8 or 9,
The method for manufacturing a semiconductor device, wherein the base insulating film is made of silicon compounds having different etching rates for hydrofluoric acid. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
A base metal film forming step of selectively forming a base metal film in a predetermined region on the substrate; a base insulating film forming step of forming a base insulating film on the surface side of the base metal film; and Performing a semiconductor film forming step of forming a semiconductor film for forming the channel region on the surface side, and a laser annealing step of performing excimer laser annealing on the semiconductor film to crystallize the semiconductor film,
Forming a first field-effect transistor and a second field-effect transistor having the same conductivity type and different defect density or defect level distribution state of a semiconductor film constituting the channel region on the same substrate; A method of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
At least a semiconductor film forming step for forming a semiconductor film for forming the channel region, an insulating film forming step for forming an insulating film having a different thickness for each region on the surface of the semiconductor film, and an excimer for the semiconductor film Performing a laser annealing step of crystallizing the semiconductor film by performing laser annealing,
Forming a first field-effect transistor and a second field-effect transistor having the same conductivity type and different defect density or defect level distribution state of a semiconductor film constituting the channel region on the same substrate; A method of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
At least a semiconductor film forming step of forming a semiconductor film for constituting the channel region, a laser annealing step of performing excimer laser annealing on the semiconductor film to crystallize the semiconductor film, and a predetermined region of the semiconductor film An inert element introduction step of selectively introducing an inert element,
A first field-effect transistor and a second field-effect transistor having the same conductivity type and having different defect level density or defect level distribution state of the crystalline semiconductor film constituting the channel region are formed over the same substrate. A method for manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
Performing at least a channel doping step of selectively introducing impurity ions into a predetermined region of the semiconductor layer constituting the channel region;
A method of manufacturing a semiconductor device, comprising forming a first field effect transistor and a second field effect transistor having the same conductivity type and different impurity types or concentrations in the channel region on the same substrate. . In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
An insulating film forming step of forming an insulating film having a different thickness depending on the region on the surface side of the semiconductor layer constituting the channel region; and a channel doping step of introducing impurity ions into the semiconductor layer through the insulating film And
A method of manufacturing a semiconductor device, comprising forming a first field effect transistor and a second field effect transistor having the same conductivity type and different impurity types or concentrations in the channel region on the same substrate. . In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
Performing at least an impurity introduction step of introducing impurity ions into the semiconductor layer, and an activation step of activating the impurity ions by selectively irradiating light to a predetermined region of the semiconductor layer constituting the channel region;
Manufacturing a semiconductor device, wherein a first field effect transistor and a second field effect transistor having the same conductivity type and different film quality of the semiconductor layer constituting the channel region are formed on the same substrate. Method. In a method for manufacturing a semiconductor device in which a plurality of field effect transistors each having a semiconductor layer, a gate insulating film, and a gate electrode forming a channel region are formed.
An insulating film forming step of forming an insulating film having a different thickness depending on the region on the surface side of the semiconductor layer constituting the channel region; and hydrogen ion introduction for introducing hydrogen ions into the semiconductor layer through the insulating film Process and
Manufacturing a semiconductor device, wherein a first field effect transistor and a second field effect transistor having the same conductivity type and different film qualities of the semiconductor layer forming the channel region are formed on the same substrate. Method. 18. The first complementary circuit according to claim 1, wherein an N-channel field effect transistor and a P-channel field effect transistor as the first field effect transistor form a first complementary circuit. The driving voltage defined by the maximum voltage difference between the signal input to the first complementary circuit and the power supply differs depending on the N-channel field-effect transistor and the P-channel field-effect transistor as the field-effect transistors. 2 complementary circuits,
The threshold voltage at which the inversion layer is formed in the channel region of the N-channel field effect transistor and the threshold voltage at which the inversion layer is formed in the channel region of the P-channel field effect transistor are Vth-Nch and When Vth-Pch,
In the first complementary circuit and the second complementary circuit, the following expression Vth−d = | (Vth−Nch) − (Vth−Pch) |
A method for manufacturing a semiconductor device, characterized in that the absolute value Vth-d of the difference in threshold voltage expressed by 18. The first complementary circuit according to claim 1, wherein an N-channel field effect transistor and a P-channel field effect transistor as the first field effect transistor form a first complementary circuit. The driving voltage defined by the maximum voltage difference between the signal input to the first complementary circuit and the power supply differs depending on the N-channel field-effect transistor and the P-channel field-effect transistor as the field-effect transistors. 2 complementary circuits,
The value obtained by dividing the drain-source resistance by the channel width when a predetermined constant voltage Vds-Nch between 1 V and 20 V is applied between the drain and the source in an N-channel field effect transistor is 1 MΩ / μm to 1 GΩ. A gate voltage when a predetermined value Ron-off between / μm is Von-off-Nch, and a P-channel field effect transistor has a predetermined voltage between −1V and −20V between the drain and source. When the gate voltage when the value obtained by dividing the drain-source resistance when the constant voltage Vds-Pch is applied by the channel width is the predetermined value Ron-off is Von-off-Pch,
In the first complementary circuit and the second complementary circuit, the following expression Von-off-d = | (Von-off-Nch) − (Von-off-Pch) |
A method for manufacturing a semiconductor device, characterized in that the absolute value Von-off-d of the difference in threshold voltage in terms of circuit operation obtained in (1) is made different.   A semiconductor device manufactured by the manufacturing method as defined in claim 1. 21. An electro-optical device using the semiconductor device defined in claim 20 as an electro-optical device substrate for holding an electro-optical material, wherein a plurality of elements arranged in a matrix on the electro-optical device substrate. And a field effect transistor for switching a pixel corresponding to each of the pixels and a field effect transistor for a drive circuit constituting a drive circuit for driving the plurality of pixels,
The plurality of field effect transistors include an N-channel field effect that constitutes the first complementary circuit and the second complementary circuit, which are different in input voltage and drive voltage defined by a maximum voltage difference between power supplies. An electro-optical device comprising a p-channel transistor and a p-channel field effect transistor.   23. The electro-optical device according to claim 21, wherein the electro-optical material is a liquid crystal held between the electro-optical device substrate and a counter substrate.   24. The electro-optical device according to claim 21, wherein the electro-optical material is an electroluminescent material constituting a light emitting element on the electro-optical device substrate.   24. An electronic apparatus using the electro-optical device defined in any one of claims 21 to 23.

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