JP2005072378A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving drain withstand voltage in a semi-insulating substrate.
A semiconductor device according to the present invention includes a field effect transistor provided on a main surface of a semi-insulating substrate and having a drain electrode, a gate electrode, and a source electrode. A wiring 16 is provided on the main surface 2 a of the semi-insulating substrate 2 and is connected to the source electrode 14. On the side surface 18 a of the via hole 18 extending from the back surface 2 b of the semi-insulating substrate 2 to the wiring 16, a back electrode 20 is provided and connected to the wiring 16. The material of the back electrode 20 is an ohmic metal for a p-type III-V compound semiconductor. For this reason, the holes easily reach the back electrode 20. Therefore, holes are not accumulated in the semi-insulating substrate 2.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device.

In a field-effect transistor (FET), when the drain voltage (V _d ) is increased, a reverse bias is applied between the drain and the gate. For this reason, a high electric field is generated in the active layer near the drain. When conduction electrons are accelerated in this region of the active layer, electron-hole pairs are generated by impact ionization (impact ionization). Electrons move in the active layer and go to the drain, but holes are accumulated in the substrate under the active layer. As a result, the substrate is positively charged in the vicinity of the interface between the substrate and the active layer, and the active layer width is effectively increased. Thus, in _V d -I _d characteristics of the field effect transistor, increasing the drain voltage _{(V d)} the drain current _{(I d)} is increased without saturating. For this reason, the drain breakdown voltage of the field effect transistor cannot be increased.

The field effect transistor described in Patent Document 1 is provided not on a semi-insulating substrate but on a p-type GaAs substrate in order to increase the drain breakdown voltage. A back electrode is provided on the back surface of the p-type GaAs substrate. Therefore, the holes generated in the active layer of the field effect transistor pass through the p-type GaAs substrate and go to the back electrode. This prevents holes from accumulating on the p-type GaAs substrate.
Japanese Patent Laid-Open No. 04-373135

  However, when a plurality of field effect transistors are formed on the same p-type GaAs substrate, it is impossible to achieve isolation between the field effect transistors. When holes are extracted using a p-type GaAs substrate, there is a neutral region where holes exist as carriers in the pn junction region with the n-type layer of the active layer. If there is no neutral region, there is no conductive path and holes cannot be pulled out. For this reason, there is a problem that the gate capacitance increases and the high frequency characteristics deteriorate. On the other hand, isolation can be realized with a semi-insulating substrate, but the drain breakdown voltage cannot be increased as described above.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of improving drain withstand voltage in a semi-insulating substrate.

  In order to solve the above problems, a semiconductor device of the present invention is provided on a main surface of a semi-insulating substrate, and includes a field effect transistor having a drain electrode, a gate electrode, and a source electrode, A back surface electrode provided on the surface and connected to the source electrode; and a back surface electrode provided on the side surface of the via hole extending from the back surface of the semi-insulating substrate to the conductor portion and connected to the conductor portion. The material of the electrode is an ohmic metal for a p-type III-V compound semiconductor.

  When a high voltage is applied between the drain and gate of the field effect transistor, electron-hole pairs are generated by impact ionization. Here, the back electrode provided on the side surface of the via hole is connected to the source electrode via the conductor. Therefore, holes are directed to the back electrode due to the potential gradient. Furthermore, since the material of the back electrode is an ohmic metal with respect to the p-type III-V group compound semiconductor, the holes easily reach the back electrode. Therefore, holes are not accumulated on the semi-insulating substrate.

  In the semiconductor device, the III-V compound semiconductor includes GaAs, and the ohmic metal includes AuZn. Furthermore, in the semiconductor device, the active layer of the field effect transistor has a pulse doping structure. As a result, a semiconductor device having excellent high frequency characteristics can be obtained.

  The semiconductor device further includes a p-type buffer layer provided on the semi-insulating substrate. The holes are majority carriers in the p-type buffer layer and easily reach the back electrode through the p-type buffer layer. Thereby, holes are not accumulated in the semi-insulating substrate.

  According to the present invention, it is possible to provide a semiconductor device capable of improving the drain withstand voltage in a semi-insulating substrate.

  Hereinafter, the semiconductor device according to the embodiment will be described. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted. First, the structure of the semiconductor device 1 will be described.

  FIG. 1 is a cross-sectional view of a semiconductor device 1 according to the embodiment. The semiconductor device 1 includes a field effect transistor 15 provided on the main surface 2 a of the semi-insulating substrate 2. The semiconductor device 1 further includes a p-type buffer layer 4 provided on the semi-insulating substrate 2.

  An example of the semiconductor device 1 is a microwave integrated circuit (MIC). The semi-insulating substrate 2 is made of, for example, semi-insulating GaAs. The thickness of the semi-insulating substrate 2 is, for example, 100 micrometers.

  The field effect transistor 15 includes an active layer 6 provided on the semi-insulating substrate 2, a cap layer 8 provided on the active layer 6, a drain electrode 12, a gate electrode 10 provided on the cap layer 8, and Source electrode 14. A gate electrode 10 is provided between the drain electrode 12 and the source electrode 14. The field effect transistor 15 is, for example, an n-channel field effect transistor.

  The active layer 6 has a pulse dope structure, for example. The active layer 6 includes, for example, a pulse doped layer 6a, an undoped layer 6b, a pulse doped layer 6c, and an undoped layer 6d. Thereby, the semiconductor device 1 excellent in linearity and high frequency characteristics can be obtained.

The pulse doped layers 6a and 6c are made of a high concentration n-type semiconductor such as n ⁺ GaAs. The dopant concentration in the pulse dope layers 6a and 6c is, for example, 2 × 10 ¹⁸ cm ⁻³ . The dopant is, for example, Si, Sn, Te. The thicknesses of the pulse doped layers 6a and 6c are, for example, 8 nanometers and 10 nanometers, respectively.

  The undoped layers 6b and 6d are made of undoped GaAs, for example. The undoped layers 6b and 6d have thicknesses of, for example, 30 nanometers and 40 nanometers, respectively.

  The cap layer 8 is made of an undoped semiconductor, and is made of, for example, undoped AlGaAs. The thickness of the cap layer 8 is, for example, 30 nanometers.

  The gate electrode 10 is made of, for example, a Schottky metal that forms a Schottky junction with the cap layer 8. The gate length is, for example, 0.7 micrometers. The gate pitch is 40 micrometers, for example. The drain electrode 12 and the source electrode 14 are in ohmic contact with the cap layer 8. The source electrode 14 is made of, for example, AuGe / Ni. A wiring 16 (conductor portion) provided on the main surface 2 a of the semi-insulating substrate 2 is connected to the source electrode 14. The wiring 16 is made of, for example, Ti / Pt / Au. The width of the wiring 16 is, for example, 35 micrometers.

The p-type buffer layer 4 is made of a p-type semiconductor such as p-type GaAs, for example. The dopant concentration in the p-type buffer layer 4 is, for example, 5 × 10 ¹⁶ cm ⁻³ . The dopant is, for example, Zn, C, Be, Mg. The thickness of the p-type buffer layer 4 is, for example, 1 micrometer.

  A via hole 18 extends from the back surface 2 b of the semi-insulating substrate 2 to the wiring 16. That is, the via hole 18 penetrates the semi-insulating substrate 2, the p-type buffer layer 4, the active layer 6 and the cap layer 8. The opening diameter of the via hole 18 is, for example, 30 micrometers.

  A back electrode 20 is provided on the side surface 18 a of the via hole 18. Further, the back electrode 20 is also provided on one end 18 b of the via hole 18 and the back surface 2 b of the semi-insulating substrate 2. The thickness of the back electrode 20 is, for example, 10 micrometers. Further, the back electrode 20 may be provided so as to fill the via hole 18. The back electrode 20 is electrically connected to the wiring 16 at one end 18 b of the via hole 18. Therefore, the source electrode 14, the wiring 16, and the back electrode 20 are at the same potential. By providing the back electrode 20 in the via hole 18, the source inductance can be reduced.

  The material of the back electrode 20 is an ohmic metal for a p-type III-V compound semiconductor. Therefore, the back electrode 20 can form an ohmic contact with the p-type buffer layer 4. Examples of III-V compound semiconductors include GaAs, GaInP, InP, and InGaAs. Examples of the ohmic metal include AuZn, Pt / Ti / Au, and AuBe. AuZn forms ohmic contact with the p-type semiconductor, but Ti / Pt / Au does not form ohmic contact with the p-type semiconductor. Even if the material of the back electrode 20 is replaced with Ti / Pt / Au and AuZn, no particular problem occurs.

  Next, the operation of the semiconductor device 1 will be described. In the field effect transistor 15, the source region and the drain region are connected by the active layer 6. When a reverse bias is applied between the drain electrode 12 and the gate electrode 10, a high electric field is generated near the drain region in the active layer 6. The potential of the source electrode 14 is a ground potential, for example. When conduction electrons in the active layer 6 are accelerated by a high electric field, electron-hole pairs are generated by impact ionization (impact ionization). Here, the dopant concentration in the p-type buffer layer 4 and the thickness of the p-type buffer layer 4 are preferably adjusted so that the vicinity of the drain region is depleted and the neutral region remains in the vicinity of the source region.

FIG. 2 is an energy band diagram of the semiconductor device 1. In FIG. 2, the vertical axis indicates energy, and the horizontal axis indicates the position in the thickness direction of the semiconductor device 1. The region L2 corresponds to the semi-insulating substrate 2, the region L4 corresponds to the p-type buffer layer 4, the region L6 corresponds to the active layer 6, and the region L8 corresponds to the cap layer 8. E _F represents the Fermi level. As apparent from FIG. 2, holes generated in the active layer 6 are accumulated in the p-type buffer layer 4.

Since holes are majority carriers in the p-type buffer layer 4, they pass through the p-type buffer layer 4. Since the back electrode 20 is connected to the source electrode 14 via the wiring 16, the holes go to the back electrode 20. Since the material of the back electrode 20 is an ohmic metal for a p-type III-V group compound semiconductor, holes can reach the back electrode 20 more easily than when the material of the back electrode 20 is an ohmic metal for an n-type semiconductor. . Therefore, holes are not accumulated in the semi-insulating substrate 2. Therefore, since the effective active layer 6 width does not increase, V _d -I _d characteristics at a drain voltage (V _d) to significantly drain even when the current (I _d) direction of the inflection points increase does not occur . Therefore, the drain breakdown voltage of the semiconductor device 1 can be improved and avalanche breakdown can be suppressed. Specifically, for example, the operating voltage in the semiconductor device 1 can be increased from 12V to 26V. The hole moving speed is higher in the p-type buffer layer 4 than in the semi-insulating substrate 2. Therefore, in the semiconductor device 1 including the p-type buffer layer 4, the probability and speed at which holes reach the back electrode 20 can be improved as compared with a semiconductor device not including the p-type buffer layer.

  In the field effect transistor described in Patent Document 1, the thickness of the substrate is at least about 70 to 100 micrometers, and the hole moving distance becomes long. On the other hand, in the semiconductor device 1, since the holes are directed to the back electrode 20 provided on the side surface 18 a of the via hole 18, the movement distance of the holes can be short. For example, if the distance between the gate electrode 10 and the source electrode 14 is several micrometers, the movement distance of holes may be about several micrometers. Therefore, in the semiconductor device 1, holes can be efficiently extracted through the back electrode 20.

  As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to this.

  For example, the semiconductor device 1 includes the p-type buffer layer 4, but the semiconductor device according to the modification of the present invention may not include the p-type buffer layer 4. In such a semiconductor device, the field effect transistor 15 is provided on the semi-insulating substrate 2 without the p-type buffer layer 4 interposed therebetween.

  In the semiconductor device according to this modification, when a high voltage is applied between the drain and gate of the field effect transistor 15, electron-hole pairs are generated by impact ionization. Here, the back electrode 20 provided on the side surface 18 a of the via hole 18 is connected to the source electrode 14 via the wiring 16. Therefore, holes move toward the back electrode 20 through the semi-insulating substrate 2 due to the potential gradient. Since the material of the back electrode 20 is an ohmic metal for a p-type III-V group compound semiconductor, holes can reach the back electrode 20 more easily than when the material of the back electrode 20 is an ohmic metal for an n-type semiconductor. . Therefore, holes are not accumulated in the semi-insulating substrate 2.

  FIG. 3A is a cross-sectional view of the semiconductor device 100. The semiconductor device 100 includes a field effect transistor 115 provided on a semiconductor substrate 102. The field effect transistor 115 includes a pulse doped layer 106 and a cap layer 108. A buffer layer 104 is provided on the semiconductor substrate 102. The gate electrode 110 is provided on the cap layer 108. The gate electrode 110 is provided between the drain electrode 112 and the source electrode 114. A p-type electrode 116 is connected to the source electrode 114. A region 118 (p layer) into which a p-type dopant is implanted is provided under the p-type electrode 116 so as to reach the buffer layer 104.

  In the semiconductor device 100, a step of implanting p-type dopant and a step of forming the p-type electrode 116 are necessary, and the number of manufacturing steps increases. The implantation of the p-type dopant needs to be performed so that the dopant can reach the buffer layer 104. Considering that the thickness of the cap layer 108 is several tens of nanometers or less and the thickness of the pulse doped layer 106 is ten nanometers or less, even a heavy element such as Zn is p-type using a normal injection device. Dopant implantation can be performed.

  FIG. 3B is a cross-sectional view of the semiconductor device 200. The semiconductor device 200 includes a field effect transistor 215 provided on the semiconductor substrate 202. The field effect transistor 215 includes a pulse doped layer 206 and a cap layer 208. A buffer layer 204 is provided on the semiconductor substrate 202. The gate electrode 210 is provided on the cap layer 208. The gate electrode 210 is provided between the drain electrode 212 and the source electrode 214. The mesa-shaped recess 218 is provided so as to penetrate the cap layer 208 and the pulse doped layer 206 and reach the buffer layer 204. The depth of the recess 218 is, for example, 300 nanometers. The p-type electrode 216 is provided in the recess 218 so as to be connected to the source electrode 214 and the buffer layer 204.

  In the semiconductor device 200, an etching process for forming the recess 218 and a process for forming the p-type electrode 216 in the recess 218 are required, which increases the number of manufacturing processes.

  On the other hand, in the semiconductor device 1, a process for forming the via hole 18 and a process for forming the back electrode 20 are required. However, these steps are not newly added steps, and the number of manufacturing steps does not increase. Therefore, unlike the semiconductor devices 100 and 200, the semiconductor device 1 does not involve an increase in manufacturing steps (an increase in cost).

FIG. 1 is a cross-sectional view of the semiconductor device according to the embodiment. FIG. 2 is an energy band diagram of the semiconductor device. FIG. 3 is a cross-sectional view of the semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semi-insulating substrate, 2a ... Main surface, 2b ... Back surface, 4 ... P-type buffer layer, 6 ... Active layer, 6b, 6d ... Undoped layer, 6a, 6c ... Pulse doped layer, 8 ... Cap Layers, 10 ... gate electrodes, 12 ... drain electrodes, 14 ... source electrodes, 15 ... field effect transistors, 16 ... wiring (conductor portions), 18 ... via holes, 18a ... side surfaces, 18b ... one end, 20 ... back electrode, L2, L4, L6, L8 ... region, 100, 200 ... semiconductor device, 102, 202 ... semiconductor substrate, 104, 204 ... buffer layer, 106, 206 ... pulse doped layer, 108, 208 ... cap layer, 110, 210 ... gate electrode, 112, 212 ... drain electrode, 114, 214 ... source electrode, 115, 215 ... field effect transistor, 116, 216 ... p-type electrode, 218 ... recess.

Claims (4)

A field effect transistor provided on the main surface of the semi-insulating substrate and having a drain electrode, a gate electrode and a source electrode;
A conductor portion provided on the main surface of the semi-insulating substrate and connected to the source electrode;
Provided on the side surface of the via hole extending from the back surface of the semi-insulating substrate to the conductor portion, and connected to the conductor portion;
With
The material of the back electrode is a semiconductor device that is an ohmic metal with respect to a p-type III-V compound semiconductor. The III-V compound semiconductor includes GaAs,
The ohmic metal includes AuZn,
The semiconductor device according to claim 1. The active layer of the field effect transistor has a pulse dope structure,
The semiconductor device according to claim 1. A p-type buffer layer provided on the semi-insulating substrate;
The semiconductor device as described in any one of Claims 1-3.

Images