JP2005072238A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the influence of scratches caused by a CMP process as compared with the conventional case.
A method of manufacturing a semiconductor device includes a step of polishing an insulating film 3 deposited on a substrate 1 on which a transistor or the like is formed by CMP to form an insulating film 3a, and forming a through hole 5 in the insulating film 3a. A step of forming, a step of forming a polysilicon film 6 filling the through hole 5, a step of polishing the polysilicon film 6 by CMP, and a final polishing step of polishing the polysilicon and the insulating film 3a by CMP. In the final polishing step, the polysilicon 8 remaining in the scratch 4 can be removed by reducing the difference in polishing rate between the polysilicon and the insulating film.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device using CMP (Chemical Mechanical Polishing), and more particularly, to a method for manufacturing a semiconductor device including measures for suppressing the occurrence of defects due to scratches in a CMP process.

  In a manufacturing process of a semiconductor integrated circuit including a multilayer wiring layer, planarization processing by CMP is performed in various situations such as when an interlayer insulating film is formed, when wirings and plugs are formed. Thereby, the height in each wiring layer is kept uniform, and a highly integrated semiconductor integrated circuit can be manufactured.

  However, in the CMP process, since polishing is performed while applying a large pressure to the semiconductor wafer, scratches called “scratches” enter the semiconductor wafer when abrasive particles contained in the polishing liquid (slurry) aggregate. There is.

  There are various effects of scratches generated in the CMP process. One of them is that when conducting a CMP process using an oxide film as a polishing stopper in a later process, the conductive film remains on the scratch and wiring is formed. Or cause a short between plugs. A description will be given of how a scratch is formed in a semiconductor device manufacturing method including a conventional CMP process.

  4A to 4E are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device including a CMP process.

  First, as shown in FIG. 4A, a transistor having, for example, a gate electrode 142 is formed on a semiconductor substrate 141 made of silicon or the like. Next, for example, BPSG (Boron Phosphate Silicon Glass) is deposited on the semiconductor substrate 141 to form an insulating film 143 having a thickness of 800 nm.

  Next, as shown in FIG. 4B, the insulating film 143 is planarized by CMP to form an insulating film 143a having a thickness of 400 nm. Here, in order to distinguish the insulating film after the planarization treatment from the insulating film 143 before the treatment, it is referred to as an “insulating film 143a”. Note that it is assumed that a scratch 144 is generated on the upper surface of the insulating film 143a in this step.

  Next, as shown in FIG. 4C, when the semiconductor device is a MOSFET, a through hole 145 for making contact with the gate electrode 142 and the source / drain (not shown) is formed in the lithography process and the insulating film 143a. It is formed by dry etching. Here, the diameter of the through hole 145 is, for example, 300 nm. Note that the scratch 144 may expand in a cleaning process such as polymer removal after dry etching.

  Next, as shown in FIG. 4D, polysilicon doped with, for example, phosphorus is deposited on the entire surface of the substrate, and a polysilicon film 146 having a thickness of about 300 nm is formed to fill the through hole 145.

  Next, as shown in FIG. 4E, the polysilicon film 146 is polished by CMP using the insulating film 143a as a stopper until the insulating film 143a is exposed, and a polysilicon plug 147 is formed. In this step, since the polishing rate of the insulating film 143a is very small, the polishing of the insulating film 143a does not proceed. For this reason, when the scratch 144 is generated between two or more polysilicon plugs 145, the polysilicon 148 remains in the scratch 144, which causes an electrical short circuit.

  As described above, when the scratch 144 is generated, a malfunction occurs in the operation of the semiconductor device and the reliability is lowered. For this reason, many attempts have been made to prevent the occurrence of scratches by optimizing the CMP conditions and maintaining the CMP apparatus. If this is still insufficient, a method of reducing the scratch by forming an insulating film after CMP or performing heat treatment is employed. A conventional method for reducing such scratches will be briefly described.

  First, reduction of scratches by optimizing CMP conditions will be described.

  There are various causes for the occurrence of scratches, but the largest cause is the supply of aggregated coarse abrasive particles as described above. Therefore, it has been studied to improve the abrasive particles contained in the polishing liquid.

  For example, in CMP of a silicon oxide film, fumed silica is generally used as an abrasive particle in order to increase the polishing rate. In this case, the abrasive particle is likely to aggregate, and a coarse aggregate of abrasive particles is scratched on the oxide film surface. Is known to cause Therefore, a slurry containing fumed silica-based particles that hardly aggregate is used, or a slurry containing colloidal silica-based particles that does not cause aggregation although the polishing rate decreases. On the other hand, when a metal such as tungsten (W) is used as the plug material, CMP of the metal film is performed. In the CMP of this metal film, a slurry containing alumina particles has been used to increase the selectivity with the base oxide film, but scratches were likely to occur on the conductive film surface and the oxide film surface serving as a stopper. . In response to this, various improvements such as changing the composition of the abrasive particles themselves and the polishing liquid have been made, and the selectivity to the base oxide film can be improved even in slurries containing silica-based particles, and scratches can be reduced. became.

  Next, a method for reducing scratches by maintaining CMP equipment will be briefly described.

  If the slurry is allowed to stand for a long time, the abrasive particles precipitate and aggregate. Therefore, in the slurry supply apparatus, it is necessary to provide a piping structure that constantly circulates the slurry and hardly retains the slurry. Further, after the introduction of the equipment, the occurrence of scratches can be suppressed by periodically cleaning the slurry supply system and the CMP apparatus.

  Next, the process approach to scratch will be briefly described.

  First, in the conventional manufacturing method, for example, a method of newly depositing an oxide film after CMP of the oxide film has been attempted. Examples of the newly deposited film include a p-TEOS film, a BPSG film, and an HDP-CVD film. According to this method, since the oxide film is embedded in the scratch, the size of the scratch can be somewhat reduced. When depositing a BPSG film, the BPSG film can be fluidized by applying a heat treatment thereafter, and the scratch can be further reduced.

In addition, after CMP of a film having heat fluidity such as a BPSG film, scratching can be reduced by performing heat treatment.
Japanese Patent Laid-Open No. 9-191048

  However, even if the above conventional method is used, the generation of scratches cannot be completely prevented.

  For example, even if the polishing conditions are optimized, scratching can be reduced, but it is difficult to achieve zero as long as polishing is performed with abrasive particles. Even in the maintenance of the CMP facility, even if it is possible to prevent the occurrence of frequent scratches, it is not possible to expect the effect to make it zero.

  Also, in terms of process improvement, it is difficult to suppress the generation of scratches even though the conventional method can reduce the size of the scratches. In particular, in the method of performing a heat treatment after CMP, baking before CMP needs to be insufficient, the film becomes unstable, and the polishing rate reproducibility at the time of CMP may deteriorate.

  As described above, there is still a problem of further reducing the generation of scratches in the CMP process when manufacturing a semiconductor device.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the influence of scratches caused by the CMP process as compared with the conventional one.

  In order to solve the above problems, the inventors of the present invention provide a process of polishing a conductive film by CMP after a process of forming a conductive film over an insulating film provided over a substrate, and an insulating film together with the conductive film. And the process of removing it. Even if scratches (including scratches) occur on the upper surface of the insulating film due to CMP or other processes, this method makes it possible to theoretically completely remove the conductive film remaining on the scratches. is there.

  That is, the method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a conductive film on an insulating film provided on a substrate and having at least one of a trench and a through hole formed thereon, and the step (a). A step (b) of chemically mechanically polishing the conductive film under a condition that the removal rate of the conductive film is higher than a removal rate of the insulating film; and after the step (b), the conductive film with respect to the insulating film A step of forming a wiring for filling the trench or a plug for filling the through hole by removing a part of the insulating film and a part of the conductive film under the condition that the selection ratio of the removal rate is smaller than that of the step (b). (C).

  By this method, when there is a scratch such as a scratch on the upper surface of the insulating film at the time of the step (a), the conductive film remaining on the scratch on the insulating film can be removed in the step (c). Alternatively, it is possible to prevent problems caused by scratches on the insulating film, such as occurrence of a short circuit between adjacent wirings.

  In the step (c), a part of the insulating film and a part of the conductive film are removed by chemical mechanical polishing, so that even when the substrate surface has some unevenness at the end of the step (b), the upper surface of the substrate Can be flattened, and the height of the wiring or plug can be made uniform.

  In the step (c), part of the insulating film and part of the conductive film may be removed by dry etching. According to this method, the removal rate ratio between the insulating film and the conductive film can be easily adjusted as compared with the case of polishing.

  When the conductive film is made of polysilicon or amorphous silicon, it is possible to manufacture a semiconductor device having a polysilicon plug with higher reliability than the conventional one by this method.

  Prior to the step (a), a step of chemically mechanically polishing the insulating film and a step of forming a trench or a through hole in the polished insulating film may be further included.

  The insulating film includes a first insulating film provided on the substrate, and a second insulating film provided on the first insulating film and made of a material different from that of the first insulating film. The chemical mechanical polishing step of the insulating film is a step of chemical mechanical polishing the first insulating film. For example, the second insulating film is used as an etching mask when forming a trench or a through hole. In addition, the size of the scratch generated during polishing of the first insulating film can be reduced.

  The conductive film formed in the step (a) is provided on at least a first conductor film covering the trench or the through hole, and on the first conductor film, and at least the trench or the through hole is formed. A polishing rate of the first conductor film and the second conductor film than the polishing rate of the insulating film in the polishing in the step (b). Therefore, a wiring or a plug can be formed using a second conductor film that is not preferably formed directly on a member such as a transistor such as copper or tungsten.

  The second conductor film is a copper film, and in the step (a), the first conductor film and the copper film fill the trench so that there is no inconvenience such as a short circuit and the height is high. Aligned copper wiring can be formed.

  After the step (b) and before the step (c), the method further includes a step (b2) of chemically mechanically polishing the first conductive film using the insulating film as a stopper. In the step (b) By polishing the copper film using the first conductor film as a stopper, the height variation in the substrate plane can be further reduced in the step (b2).

  In the step (b), the copper film is polished using the first conductor film as a stopper, and in the step (c), the first conductor film, the insulating film, and a part of the copper film are removed. By doing so, the number of steps can be reduced as compared with the case where polishing for removing the first conductor film is performed separately, and thus the manufacturing cost can be reduced.

  In the polishing in the step (b), the ratio b / a of the polishing rate b of the conductive film to the polishing rate a of the insulating film is preferably 3 or more.

  In the step (c), a ratio d / c of the conductive film removal rate d to the insulating film removal rate c is preferably 0.3 or more and 3 or less.

  In the step (c), the thickness for removing the insulating film is preferably 30 nm to 200 nm.

  According to the method for manufacturing a semiconductor device of the present invention, even when an insulating film is damaged by CMP or the like, it is possible to form wirings or plugs having a uniform height while suppressing problems such as a short circuit.

  In order to prevent the occurrence of scratches, it is necessary to combine measures from different aspects such as improvement of the slurry supply device and CMP device, improvement of the slurry, and improvement of the manufacturing process. The inventors of the present application decided to improve the manufacturing process, which is expected to be most effective in reducing scratches among the above measures.

  In order to review the manufacturing process, the pressure conditions for the wafer in the CMP process were changed, and the rotation speed of the surface plate was changed. However, when the pressure on the wafer is reduced, scratches are difficult to enter, but on the other hand, there is a problem that the polishing rate is lowered, and even if the rotational speed is changed, a great effect is not seen. Therefore, the inventors of the present application further examined various factors, but it was impossible to completely prevent the occurrence of scratches in the CMP process.

  At one time, the inventors of the present application have changed the way of thinking and have considered the improvement of the post-CMP process based on the premise that “scratches always occur”. Accordingly, the inventors have come up with the idea of removing the conductive film embedded in the generated scratch by polishing or the like together with the insulating film.

  When a plug or wiring is formed, since scratches are generated on the insulating film, the inventors of the present application perform the CMP shown in FIG. 4E under conditions that allow the insulating film 143a and the polysilicon film 146 to be polished equally. I thought about that first. However, it has been found that this method has the following problems.

  In the step shown in FIG. 4D, when the thickness of the polysilicon film 146 is 300 nm, in order to suppress the polishing residue caused by the in-plane variation of the polishing rate, it is converted into polysilicon at the position where the polishing rate is the lowest. It is necessary to perform polishing of about 400 nm. When the variation in the polishing rate within the substrate surface is ± 20%, polishing at about 600 nm in terms of polysilicon proceeds at the portion where the polishing rate is the highest. When the polishing rate selection ratio between the polysilicon film 146 and the insulating film 143a (base oxide film) is 1, a region where the insulating film 143a decreases by 300 nm is generated. The insulating film 143a needs to be considerably thick so that the gate electrode 142 is not exposed. In this case, however, dry etching for forming the through hole 145 and polysilicon filling are difficult.

  Another problem is that the height of the polysilicon plug 147 varies within the substrate surface. In the example described here, the variation in the substrate surface when the polysilicon film 146 is polished is 200 nm, and the variation in the substrate surface when the insulating film 143 is polished until it is in the state of the insulating film 143a. For example, when the thickness is 150 nm, the variation in the height of the polysilicon plug is 350 nm at the maximum.

  In order to suppress the occurrence of such variations, it has been found that the polishing of the polysilicon film 146 is preferably performed under the condition that the insulating film 143a serves as a stopper.

  From this, the inventors of the present application first polished the polysilicon film selectively in the step of polishing the conductive film (polysilicon film) deposited on the insulating film, and then changed the conditions to change the insulating film and I came up with the idea of polishing polysilicon under conditions where it can be polished.

  As a result of conducting this method on a trial basis, it was found that scratches can be eliminated. In this method, it is necessary to change the polishing conditions in the first CMP and the second CMP, but this can be adjusted by changing the composition of the polishing liquid, the type or particle size of the polishing particles.

  Subsequently, we examined whether the same method can be applied when the plug is formed of metal or when forming the copper wiring. In these cases, the conductive film remaining above the scratch can be removed. there were. From the above, it was found that the above-described method is effective when forming a conductive member that fills the concave portion after forming the concave portion in the insulating film.

  However, the fact that this method has become possible depends largely on the improvement of the slurry. For example, when a tungsten plug is formed, a polishing liquid having a selection ratio of tungsten to oxide film of approximately 1: 1 is preferably used in the second CMP. Such a polishing liquid can be supplied within the past few years.

  As described above, the conductive film embedded in the scratch is removed by performing the second CMP with a small difference in the selection ratio between the insulating film and the conductive film after polishing the conductive film filling the through hole by CMP. It is possible to provide a semiconductor device free from defects such as a mechanical short circuit.

  From the inventors' investigation, the polishing rate ratio b / a is 0.3 or more and 3 or less when the polishing rate of the insulating film in the second CMP is a and the polishing rate of the conductive film is b. It was found that 1 or more and 3 or less is more preferable, and 1 is most preferable.

  Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
1A to 1F are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In the present embodiment, a process of forming a polysilicon plug using CMP will be described.

  First, as shown in FIG. 1A, a transistor having, for example, a gate electrode 2 is formed on a substrate 1 made of a semiconductor or an insulating material. Next, for example, BPSG is deposited on the substrate 1 to form the insulating film 3 having a thickness of about 800 nm. The insulating film 3 may be composed of two or more insulating films.

  Next, as shown in FIG. 1B, the insulating film 3 is flattened by CMP to form an insulating film 3a having a thickness of 400 nm. Here, in order to distinguish the insulating film after the planarization from the insulating film 3 before the processing, it is referred to as “insulating film 3a”. In this step, it is assumed that the scratch 4 is generated on the upper surface of the insulating film 3a. Examples of the slurry used in CMP of an oxide film such as BPSG include those containing, for example, fumed silica as abrasive particles and ammonium hydroxide or potassium hydroxide as a pH adjuster.

  Next, as shown in FIG. 1C, when the semiconductor device is a MOSFET, a through hole 5 for making contact with the gate electrode 2 and the source / drain (not shown) is formed in the lithography process and the insulating film 3a. It is formed by dry etching. Here, the diameter of the through hole 5 is, for example, 300 nm. Further, the depth of the conventional through hole 5 is set to be 30 nm or more and 200 nm or less deeper than the design value after the plug is formed so that it can be polished in a subsequent process. Note that the scratch 4 may expand in a cleaning process such as polymer removal after dry etching.

  Before this step and after the step shown in FIG. 1B, a film having dry etching resistance such as an HDP-CVD film or a p-TEOS film may be deposited on the scratched insulating film 3a. . This functions as a hard mask during dry etching. In this case, the size of the scratch 4 can be somewhat reduced.

  Next, as shown in FIG. 1D, polysilicon doped with, for example, phosphorus is deposited on the entire surface of the substrate, and a polysilicon film 6 having a thickness of about 300 nm is formed to fill the through hole 5.

  Next, as shown in FIG. 1E, the polysilicon film 6 is polished by CMP using the insulating film 3a as a stopper until the insulating film 3a is exposed, and a polysilicon plug 7 is formed. In this step, the polishing rate selection ratio b / a is 3 or more when the polishing rate of the insulating film is a and the polishing rate of the conductive film is b. In this CMP step, the polishing of the insulating film 3 a does not proceed, so that the polysilicon 8 remains on the scratch 4.

  Examples of the slurry used in the CMP of polysilicon in this step include those containing, as abrasive particles, colloidal silica, an additive for increasing the polishing rate selection ratio with the base oxide film, and the like. The polishing rate selection ratio of polysilicon to the oxide film can be 50 or more.

  Subsequently, as shown in FIG. 1F, CMP is performed again under the condition that the polishing rate difference between the conductive film (here, polysilicon) and the insulating film is small. This CMP is hereinafter referred to as “finish polishing” in the present specification. When the polishing rate of the insulating film 3a in this final polishing is a and the polishing rate of the conductive film is b, the selection ratio b / a of the polishing rate is preferably 0.3 or more and 3 or less, and is 1 or more and 3 or less. More preferably, it is 1 and most preferably. Therefore, in this step, the polysilicon 8 remaining on the scratch 4 and the insulating film 3a are polished simultaneously. The polishing amount of the insulating film 3a is suitably about 30 nm to 200 nm, but most preferably 50 nm to 150 nm.

  Examples of the slurry used in CMP in this step include those containing fumed silica as abrasive particles and ammonium hydroxide or potassium hydroxide as a pH adjuster.

  According to the above manufacturing method, the remaining polysilicon between the plugs is removed by the finish polishing step shown in FIG. 1F, so that a short circuit between the plugs can be prevented. According to this method, it is possible to completely remove the polysilicon embedded in the scratch by increasing the polishing amount in the final polishing. However, if the polishing amount is excessively large, it is necessary to deepen the through-hole formed in the step shown in FIG. 1C, which may make it difficult to form a through-hole by dry etching, and subsequent polysilicon embedding. There is a risk of failure. In addition, since the polishing variation of the finish polishing itself becomes large, the polishing amount in the finish polishing is preferably at least 200 nm, more preferably 150 nm or less.

  Further, since most scratches have a depth of 30 to 100 nm, the lower limit of the polishing amount in finish polishing is preferably 30 nm or more, and more preferably 50 nm or less.

  In the description of the present embodiment, the plug material is polysilicon, but it may be amorphous silicon.

  Further, although the CMP condition shown in FIG. 1B is the CMP for polishing the oxide film, the CMP may be performed under any conditions.

  In the step shown in FIG. 1 (f), if the removal selection ratio (removal rate ratio) of the polysilicon film 6 to the insulating film 3a is not less than 0.3 and not more than 3 as in the finish polishing, instead of the finish polishing. Alternatively, dry etching may be performed. In the case of dry etching, the removal rate ratio can be adjusted more easily than in CMP, so that scratches can be easily removed regardless of the type of conductor film or insulating film. However, since CMP can achieve higher flatness than etching, CMP is preferably used when forming a multilayer wiring layer. In the case of using CMP, unlike the dry etching, the upper surface of the substrate can be planarized even when some level difference remains.

  In this embodiment, it is assumed that scratches are caused by CMP when the insulating film 3a shown in FIG. 1B is formed. However, when the insulating film 3a is damaged due to a process other than CMP or for some other reason. In addition, the conductive film embedded in the scratch can be removed by using the manufacturing method of the present embodiment.

(Second Embodiment)
As a second embodiment of the present invention, a process for forming a metal plug using CMP will be described.

  2A to 2F are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

  First, as shown in FIG. 2A, a transistor having, for example, a gate electrode 12 is formed on a substrate 11 made of a semiconductor or an insulating material. Next, for example, BPSG is deposited on the substrate 11 and then heat treatment is performed to form an insulating film 13 having a thickness of about 800 nm.

  Next, as shown in FIG. 2B, the insulating film 13 is flattened by CMP to form an insulating film 13a having a thickness of 400 nm. Here, in order to distinguish the insulating film after the planarization treatment from the insulating film 13 before the treatment, it is referred to as an “insulating film 13a”. It is assumed that the scratch 14 is generated on the upper surface of the insulating film 13a in this step. Examples of the slurry used in CMP of an oxide film such as BPSG include those containing, for example, fumed silica as abrasive particles and ammonium hydroxide or potassium hydroxide as a pH adjuster.

  Next, as shown in FIG. 2C, when the semiconductor device is a MOSFET, a through hole 15 for making contact with the gate electrode 12 and the source / drain (not shown) is formed in the lithography process and the insulating film 13a. It is formed by dry etching. Here, the diameter of the through hole 15 is, for example, 300 nm. In addition, the depth of the conventional through hole 15 is set to be 30 nm or more and 200 nm or less deeper than the design value after the plug formation in advance so that it may be polished in a subsequent process. Note that the scratch 14 may expand in a cleaning process such as polymer removal after dry etching.

  Before this step and after the step shown in FIG. 2B, a film having dry etching resistance such as an HDP-CVD film or a p-TEOS film may be deposited on the scratched insulating film 13a. . This functions as a hard mask during dry etching. In this case, the size of the scratch 14 can be somewhat reduced.

  Subsequently, as shown in FIG. 2D, for example, tungsten is deposited as a conductor on the entire surface of the substrate, and a tungsten film 16 having a thickness of 300 nm is formed to fill the through hole 15. Although not shown, usually, titanium and titanium nitride are sequentially deposited before depositing tungsten. This is to reduce the contact resistance with tungsten or prevent the gas used in the process of depositing tungsten from affecting the members such as the gate electrode.

  Next, as shown in FIG. 2E, the tungsten film 16 is polished by CMP using the insulating film 13a as a stopper until the insulating film 13a is exposed, thereby forming a tungsten plug 17. In this step, the polishing rate selection ratio b / a is 3 or more when the polishing rate of the insulating film is a and the polishing rate of the conductive film is b. In this CMP process, the polishing of the insulating film 13a hardly proceeds, so that the tungsten 18 remains on the scratch 14.

  The slurry used in tungsten CMP in this step is, for example, fumed silica as polishing particles, hydrogen peroxide as an oxidizing agent, or the insulating film 13a (underlying oxide film) in order to increase the polishing rate selection ratio. The thing containing the additive of these etc. is mentioned. The tungsten polishing rate selection ratio with respect to the oxide film (insulating film 13a) can be 10 or more.

  Subsequently, as shown in FIG. 2F, finish polishing is performed under a condition where the polishing rate difference between tungsten and the insulating film is small.

  In this final polishing, the polishing rate selection ratio b / a, where a is the polishing rate of the insulating film 13a and b is the polishing rate of the conductive film, is preferably 0.3 or more and 3 or less, and is 1 or more and 3 or less. More preferably, it is 1 and most preferably. Therefore, in this step, the tungsten 18 remaining on the scratch 14 and the insulating film 13a are polished simultaneously. The polishing amount of the insulating film 13a is suitably about 30 nm to 200 nm, but is most preferably 50 nm to 100 nm. By this step, the tungsten 18 remaining on the scratch 14 is removed.

  In addition, as a slurry used by CMP in final polishing, the thing containing fumed silica as an abrasive | polishing particle, for example, and containing an iodic acid etc. as an oxidizing agent is mentioned, for example.

  According to the above manufacturing method, since the remaining tungsten between the plugs is removed by the finish polishing step shown in FIG. 2F, a short circuit between the plugs can be prevented. According to this method, the scratch can be completely removed by increasing the polishing amount in the finish polishing. However, if the polishing amount is excessively large, it is necessary to deepen the through hole formed in the step shown in FIG. 2C, which makes it difficult to form the through hole by dry etching, and the subsequent filling of tungsten is poor. There is a risk of becoming. In addition, since polishing variation in the finish polishing itself increases, the polishing amount in the finish polishing is preferably at least 200 nm or less, and more preferably 150 nm or less, as in the first embodiment.

  Further, since most scratches have a depth of 30 to 100 nm, the lower limit of the polishing amount in finish polishing is preferably 30 nm or more, and more preferably 100 nm or less.

  In the description of the present embodiment, the plug material is tungsten, but other metal may be used as long as the plug is shallow and can be embedded.

  Further, the CMP condition shown in FIG. 2B is the CMP for polishing the oxide film, but the CMP may be performed under any conditions.

  In the step shown in FIG. 2F, if the removal rate ratio of the tungsten film 16 to the insulating film 13a is not less than 0.3 and not more than 3 as in the finish polishing, dry etching is performed instead of finish polishing. It doesn't matter. However, since CMP can achieve higher flatness than etching, CMP is preferably used when forming a multilayer wiring layer.

(Third embodiment)
As a third embodiment of the present invention, a process for forming a copper (Cu) wiring using CMP will be described.

  3A to 3F are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

  First, as shown in FIG. 3A, after a semiconductor device such as a transistor is formed on a substrate 21 made of a semiconductor or an insulating material, an insulating film 22 made of, for example, HDP-FSG is formed on the entire surface of the substrate. Form. Next, a trench 23 having a depth of, for example, 400 nm is formed by lithography and dry etching of the insulating film 22. Thereafter, tantalum or tantalum nitride having a thickness of 50 nm is deposited on the entire surface of the substrate including the trench 23 to form a metal film (first conductor film) 24. Next, a copper film 25 having a total thickness of 700 nm, for example, is formed on the metal film 24 by physical vapor deposition (PVD), plating, or the like.

  Next, as shown in FIG. 3B, CMP is performed on the copper film 25 under the condition that the metal film 24 serves as a stopper. Subsequently, CMP is performed on the copper film 25 and the metal film 24 under the condition that the base insulating film (insulating film 22) serves as a stopper, and is provided on the barrier metal 24a and the barrier metal 24a covering the trench 23. Copper wirings 26 filling the trenches 23 are formed. It is assumed that a scratch 27 is generated on the upper surface of the insulating film 22 in this step.

  In this step, the slurry used in the CMP of the copper film 25 using the metal film 24 as a stopper includes, for example, colloidal silica as the polishing particles, hydrogen peroxide as the copper oxidizer, and glycine as the copper etching accelerator. Examples of the protective agent for copper include quinaldic acid and BTA (benzotriazole), and examples of a rate selective ratio increasing agent for the barrier film (metal film 24) include polyalkyleneimine.

  The slurry used in the CMP of the copper film 25 and the metal film 24 using the insulating film 22 as a stopper includes, for example, colloidal silica as an abrasive particle, hydrogen peroxide as an oxidizing agent of the metal film 24, and oxalic acid as a reducing agent, for example. Examples of the copper protective agent include quinaldic acid, and examples of the rate selective ratio increasing agent for the insulating film include a surfactant. In this slurry, the polishing rate of copper can be adjusted by adjusting the amount of quinaldic acid or the like that acts as a copper protective film during polishing. In general, the polishing rate of the copper film 25 is made smaller than that of the metal film 24.

Next, as shown in FIG. 3C, a silicon nitride film (Si ₃ N ₄ ), a silicon carbide film (SiC), or the like is deposited, for example, 100 nm, and then HDP-FSG is deposited, for example, 900 nm. 28 is formed. Thereafter, planarization by CMP or the like may be performed as necessary. Next, a lithography process and dry etching of the insulating film 28 form, for example, a trench 29 having a depth of 500 nm and a through hole that connects the copper wiring 26 (not shown). Next, a metal film (barrier film) 30 is formed by depositing tantalum or tantalum nitride having a thickness of 50 nm on the insulating film 28 in which the trench 29 and the through hole are formed. Next, a copper film 31 having a total thickness of 700 nm, for example, is formed on the metal film 30 by a PVD method, a plating method, or the like.

  Next, as shown in FIG. 3D, CMP is performed on the copper film 31 under the condition that the metal film 30 serves as a stopper. The copper film 31 is polished until the metal film 30 is exposed by CMP in this step. However, since the depression remains on the insulating film 28 above the scratch 27, copper remains in this portion. . In FIG. 3D, a copper film in a short-circuit state is shown as a copper film 31a for convenience. In this CMP step, the removal rate ratio of the copper film 31 to the metal film 30 is, for example, 10 or more.

  Subsequently, as shown in FIG. 3E, the copper film 31a and the metal film 30 are subjected to CMP under the condition that the insulating film 28 serves as a stopper, and the barrier metal 30a covering the trench 29 and the barrier metal 30a are formed. Copper wirings 32 that are provided and fill the trenches 29 are respectively formed. In this step, since the polishing of the insulating film 28 does not proceed, at least a metal film such as tantalum or tantalum nitride or the copper film 33 remains on the scratch 27 when the scratch is deep. The selection ratio d / c of the polishing rate d of the metal film to the polishing rate c of the insulating film is 3 or more. In general, in the CMP for polishing the metal film 30 using the insulating film 28 as a stopper, the polishing rate of the copper film 31 a is made smaller than that of the metal film 30 in order to reduce the copper recess in the copper wiring 32. Therefore, the copper film remains not only depending on the scratch depth but also because the polishing rate is low.

  Next, as shown in FIG. 3F, by performing CMP under a condition where the polishing rate difference between the copper film, the metal film, and the insulating film is small, the copper film 33 remaining on the insulating film 28 and The remaining metal film is removed. This CMP process is hereinafter referred to as “finish polishing” as in the first and second embodiments.

  The polishing rate selection ratio f / e is 0.3 or more and 3 or less, where e is the polishing rate of the insulating film 28 in this final polishing and f is the polishing rate of the copper film or metal film (barrier film). It is preferably 1 or more and 3 or less, more preferably 1, most preferably. Therefore, in this step, the metal film remaining on the insulating film 28 and the copper film 33 and the insulating film 28 are simultaneously polished. The polishing amount of the insulating film 28 is suitably about 30 nm to 200 nm, but is most preferably 50 nm to 150 nm.

  The slurry used in CMP in finish polishing includes, for example, colloidal silica as polishing particles, hydrogen peroxide as a barrier film oxidizing agent, oxalic acid as a reducing agent, quinaldic acid as a copper protective agent, and the like. Things. The polishing rate of copper can be adjusted by adjusting the addition amount of quinaldic acid and the like contained in the slurry. The polishing rate of the insulating film 28 can be adjusted by adding a surfactant, for example, when it is too large, or by increasing the abrasive particle concentration or the abrasive particle size when it is too small.

  According to the above manufacturing method, the recesses generated following the scratch 27 formed on the lower insulating film 22 can be removed by the finish polishing step shown in FIG. Can be prevented more reliably than before. Note that the scratch 27 may exist on the copper wiring. In the present embodiment, the example in which the finish polishing is not performed when the first-layer copper wiring 26 is formed has been described. However, the finish polishing is performed every time the copper wiring of each layer is formed, thereby further improving the reliability of the semiconductor device. It becomes possible to improve.

  According to this method, if the polishing amount in the final polishing is increased, the remaining conductive film generated above the scratch can be almost completely removed. However, if the amount of polishing is excessively large, the trenches and through holes must be deepened, which may cause problems such as defective formation of trenches and through holes and poor copper filling. In addition, since the polishing variation of the finish polishing itself becomes large, the polishing amount in the finish polishing is preferably at least 200 nm, more preferably 150 nm or less.

  Further, since most of the depressions in the insulating film caused by scratch have a depth of 30 to 100 nm, the lower limit of the polishing amount in finish polishing is preferably 30 nm or more, and more preferably 100 nm or less.

  In the CMP of the metal film 30 shown in FIG. 3E, the copper wiring 31 has a convex shape during polishing in order to make the polishing rate of the copper film 31a smaller than the polishing rate of the metal film 30 in general. For this reason, in the conventional method, the copper convex portion is dragged by the abrasive particles or the polishing pad, reaches the adjacent copper wiring, and may remain as it is at the end of polishing. Further, it has been found that even if adjacent copper wirings are not connected at the end of polishing, copper may move due to heat treatment or the like in a later process and cause a short circuit. If the wiring forming method of the present embodiment is used, convex copper can be polished by finish polishing, and such a problem can be prevented.

  In this embodiment, the example of performing the CMP of the copper film and the metal film before the CMP of the copper film and the metal film shown in FIGS. 3D and 3E is shown. Even if any kind of CMP is performed before the forming process, the above-described effects are not changed. As CMP before forming the copper wiring, for example, tungsten CMP, tungsten final polishing after CMP, copper film and metal film final polishing after CMP, and after the formation of the first copper wiring, the insulating film 28 is deposited. And CMP after the above.

  Further, in the step shown in FIG. 3F, if the removal selection ratio of the copper film 31a or the metal film 30 to the insulating film 28 is 0.3 or more and 3 or less as in the final polishing, the dry polishing is performed instead of the final polishing. Etching may be performed. However, since CMP can achieve higher flatness than etching, CMP is preferably used when forming a multilayer wiring layer.

  In the present embodiment, the Cu wiring forming method in single damascene has been described. However, Cu plugs can be formed by the same method.

-Modification of the third embodiment-
In the CMP step for polishing the metal film 30 of FIG. 3E described above, instead of using a slurry having a removal rate ratio of the metal film 30 to the insulating film 28 exceeding 3, the metal film 30 to the insulating film 28 is used. And the slurry whose removal rate ratio of the copper film 31a is 0.3 or more and 3 or less may be used. That is, the slurry used in the finish polishing shown in FIG. 3F can be used in the step shown in FIG.

  Thus, the metal film 30 other than the trench portion can be removed, and the insulating film 28, the remaining copper film, and the remaining metal film can be removed as they are, so that the influence of the scratch 27 can be eliminated, and the third embodiment. One polishing step can be omitted as compared with this method.

  However, since the insulating film 28 cannot function as a stopper when the metal film 30 is removed, the variation in the copper wiring height in the substrate surface is slightly larger than that of the method of the third embodiment. Therefore, the present modification that can reduce the manufacturing cost is advantageous in a semiconductor device or the like where the height regulation of the copper wiring is not strict. Is preferably used.

  In this modification, if the removal selection ratio of the copper film 31a or the metal film 30 to the insulating film 28 is not less than 0.3 and not more than 3 as in the finish polishing, dry etching may be performed instead of finish polishing. It doesn't matter.

  As described above, the present invention is useful for improving the reliability of a semiconductor integrated circuit used in various devices.

(A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(e) is sectional drawing which shows the manufacturing method of the conventional semiconductor device containing a CMP process.

Explanation of symbols

1, 11, 21 Substrate 2, 12 Gate electrode 3, 3 a, 13, 13 a, 22, 28 Insulating film 4, 14, 27 Scratch 5, 15 Through hole 6 Polysilicon film 7 Polysilicon plug 8 Polysilicon 16 Tungsten film 17 Tungsten plug 18 Tungsten 22, 29 Trench 24, 30 Metal film 24a, 30a Barrier metal 25, 31, 31a, 33 Copper film 26, 32 Copper wiring

Claims (16)

A step (a) of forming a conductive film on an insulating film provided on the substrate and having at least one of a trench or a through hole formed thereon;
After the step (a), a step (b) of chemically mechanically polishing the conductive film under a condition that the removal rate of the conductive film is larger than the removal rate of the insulating film;
After the step (b), a part of the insulating film and a part of the conductive film are removed under a condition that the selection ratio of the removal rate of the conductive film to the insulating film is smaller than that of the step (b). (C) forming a wiring for filling the trench or a plug for filling the through hole. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), a part of the insulating film and a part of the conductive film are removed by chemical mechanical polishing. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), a part of the insulating film and a part of the conductive film are removed by dry etching. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
Before the step (a), chemical mechanical polishing the insulating film;
And a step of forming a trench or a through hole in the polished insulating film. In the manufacturing method of the semiconductor device according to claim 4,
The insulating film includes a first insulating film provided on the substrate, and a second insulating film provided on the first insulating film and made of a material different from that of the first insulating film. And
The method of manufacturing a semiconductor device, wherein the step of chemically mechanically polishing the insulating film is a step of chemically mechanically polishing the first insulating film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the conductive film is made of polysilicon or amorphous silicon. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The conductive film formed in the step (a) is provided on at least a first conductor film covering the trench or the through hole, and on the first conductor film, and at least the trench or the through hole is formed. A second conductor film to be buried,
A method of manufacturing a semiconductor device, wherein the polishing rate of the first conductive film and the second conductive film is larger than the polishing rate of the insulating film in the polishing in the step (b). In the manufacturing method of the semiconductor device according to claim 7,
The method of manufacturing a semiconductor device, wherein the second conductor film is a tungsten film. In the manufacturing method of the semiconductor device according to claim 8,
The method of manufacturing a semiconductor device, wherein the first conductor film is a titanium nitride film or a titanium film, or a film in which one or more sets of both films are stacked. In the manufacturing method of the semiconductor device according to claim 7,
The second conductor film is a copper film;
In the step (a), the semiconductor device manufacturing method, wherein the first conductor film and the copper film fill the trench. In the manufacturing method of the semiconductor device according to claim 10,
After the step (b) and before the step (c), the method further includes a step (b2) of chemically mechanically polishing the first conductor film using the insulating film as a stopper,
In the step (b), the copper film is polished using the first conductor film as a stopper. In the manufacturing method of the semiconductor device according to claim 10,
In the step (b), the copper film is polished using the first conductor film as a stopper,
A method of manufacturing a semiconductor device, wherein in the step (c), a part of the first conductor film, the insulating film, and the copper film is removed. In the manufacturing method of the semiconductor device according to any one of claims 10 to 12,
The method of manufacturing a semiconductor device, wherein the first conductor film is a tantalum nitride film or a tantalum film, or a film in which one or more sets of both films are stacked. In the manufacturing method of the semiconductor device according to any one of claims 1 to 13,
In the polishing in the step (b), the ratio b / a of the polishing rate b of the conductive film to the polishing rate a of the insulating film is 3 or more. In the manufacturing method of the semiconductor device as described in any one of Claims 1-14,
In the step (c), a ratio d / c of the conductive film removal rate d to the insulating film removal rate c is 0.3 or more and 3 or less. In the manufacturing method of the semiconductor device according to any one of claims 1 to 15,
In the step (c), a method for manufacturing a semiconductor device, wherein the thickness for removing the insulating film is 30 nm to 200 nm.

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