JP2005070971A - Control method of logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep a variation in processing time of each logical operation within a certain range and to control a logic circuit composed of transistor elements, and to keep a variation in processing time of each logical operation within a certain range. The delay control logic circuit is provided.
A substrate potential control electrode of a field effect transistor or one electrode of a double gate field effect transistor is configured as a delay time control terminal when the characteristics of the transistor are used as a logic element. A signal that increases the delay of the transistor before the target propagation time and a signal that decreases the delay of the transistor after the target propagation time are given.
[Selection] Figure 1

Description

  The present invention relates to a delay time control method for a logic circuit.

  In many digital information processing apparatuses such as a CPU of a computer, synchronization control using a synchronization signal called a clock is widely performed. According to that method, information stored in a temporary storage circuit such as a latch describes the internal state of the device at a certain time. Specifically, in the logic circuit 1 shown in FIG. 9A, when a clock signal is applied to the clock signal line 3 of the temporary storage circuit 2 that supplies data or the like to the logic circuit 1, the contents of the temporary storage circuit 2 are changed. The result supplied to the logic circuit 1 through the plurality of data lines 4 and processed by the logic circuit 1 updates the contents of the temporary storage circuit 5. The temporary storage circuit 5 is the same as the temporary storage circuit 2 and information processing may be performed cyclically. The updated information is supplied to the logic circuit 1 or another logic circuit by the next clock signal. It must be ensured that the time from when the contents of the temporary storage circuit 2 are supplied to the logic circuit 1 until the signal of the processing result by the logic circuit 1 reaches the temporary storage circuit 5 is shorter than the clock cycle. This determines the lower limit of the clock period. On the other hand, the circuit operates normally no matter how short the time from when the contents of the temporary storage circuit 2 are supplied to the logic circuit 1 until the signal resulting from the processing by the logic circuit 1 reaches the temporary storage circuit 5.

  In the higher performance logic circuit, as shown in FIG. 9B, the logic circuit 1 is divided into a plurality of sections at a boundary that crosses the signal propagation path and does not divide the logic element. Reconfiguration is performed so that a serial connection structure is obtained, and an intermediate temporary storage circuit 7 is provided at each boundary. The clock signal is also supplied to the temporary storage circuit 7 at each boundary. This is a circuit configuration method called a pipeline. According to this method, the time for a signal to propagate from a temporary storage circuit to an adjacent temporary storage circuit is naturally reduced due to a decrease in the number of logical stages during that time. Since the clock cycle is determined by the maximum time until the signal supplied from all the temporary storage circuits propagates through the logic circuit and reaches the next temporary storage circuit, it is necessary to provide the boundaries appropriately and evenly. If the logic circuit 1 can be divided into n partial logic circuits, the maximum propagation time can be reduced to 1 / n when no boundary is provided, and the clock cycle can be shortened. The Since new data can be supplied to the logic circuit 1 from the temporary storage circuit 2 every clock, the amount of information processing that can be executed in a single time can be greatly increased. In such a configuration, a plurality of information processing is performed simultaneously in the logic circuit 1, but the logical operations associated with each information processing are performed in the partial logic circuit 6 isolated from each other by the temporary storage circuit 7. Signals propagating in the circuit cannot interfere with each other and behave incorrectly.

  The logic circuit of the pipeline configuration occupies an important position in the high-performance logic circuit, and in order to further improve the information processing capability, the number of pipeline stages, that is, the number of partial logic circuits 6 delimited by the boundary is increased. Things are happening.

  However, increasing the number of pipeline stages does not improve the processing capacity. First, in order to maximize the effect of the pipeline, if the maximum propagation delay time in all the partial logic circuits 6 is uniform and is constituted by n partial logic circuits 6, the logic circuit 1 Although it is desirable that the maximum propagation delay time is 1 / n, it is often impossible to divide completely evenly. In particular, when the number of divisions increases, the difficulty increases significantly. Further, since a new delay time for the temporary storage circuit 7 to update the contents is generated, shortening of the clock cycle is limited. Further, the time (turnaround) from when the signal supplied from the temporary storage circuit 2 receives the information processing to the temporary storage circuit 5 to be supplied to another logic circuit is the total time due to the increase in the temporary storage circuit 7. The increase in the delay of the system always increases the time, so when there is a dependency between the data to be processed, there is a new waiting time for the result waiting, and the possibility that the information processing speed (throughput) of the entire system itself will decrease To do.

  In order to solve the above problems, a method called wave pipeline has been devised. In the wave pipeline, the temporary storage circuit 7 is omitted, and the same configuration method as that in FIG. Specifically, when data is supplied from the temporary storage circuit 2 to the logic circuit 1 and propagates through the circuit and has not yet reached the temporary storage circuit 5, another data is newly logicized by the clock signal. This is supplied to the circuit 1. It is expected that the information processing result based on the first data arrives at the temporary storage circuit 5 and the information processing result based on the next data arrives after the contents of the temporary storage circuit 5 are updated accordingly. Therefore, in order for this circuit to operate as expected without error, the data processing result by the data reaches the temporary storage circuit 5 after the data is supplied from the temporary storage circuit 2 to the logic circuit 1 and is determined. As a result, the maximum time until the temporary storage circuit 5 finishes updating the contents and the data from the temporary storage circuit 2 starts to be supplied to the logic circuit 1, and the processing result of the data is input to the temporary storage circuit 5. It must be ensured that the difference from the minimum time until it begins to affect is less than the clock period. If the content of the temporary storage circuit 5 is updated for the first processing result after the processing result by the next signal reaches the temporary storage circuit 5, the next processing result is registered as the first processing result. This is because the circuit does not operate normally.

  In order to avoid this problem, in the wave pipeline, any data that the temporary storage circuit 2 can give the time until the signal supplied from the temporary storage circuit 2 propagates and begins to affect the input of the temporary storage circuit 5 The temporary storage circuit 2 can give the time until the signal supplied from the temporary storage circuit 2 is propagated and a fixed signal is given to the input of the temporary storage circuit 5 by examining the pattern and determining its minimum time. All data patterns are examined, the maximum time is obtained, and the clock cycle is always designed to be larger than the sum of the difference and the time required for the temporary storage circuit to update the contents. This is because there is no possibility of malfunction that causes interference between the first processing result and the next processing result (see, for example, Non-Patent Document 1).

  In a normal logic circuit design method, the difference between the minimum time and the maximum time until the signal supplied from the temporary storage circuit 2 propagates and reaches the temporary storage circuit 5 is very large, and the clock cycle determined in this way is As compared with the clock cycle when the circuit of FIG. 9A is operated as a conventional synchronous circuit, it cannot be shortened so much.

Therefore, the wave pipeline is designed so that the delay times are aligned as much as possible by intentionally adopting an element with a slow operation speed or inserting a delay element in the path where signal propagation is completed in a short time. In addition, since the clock cycle cannot be shortened even if the delay time varies depending on the data pattern, an element or circuit that gives a delay time that does not depend on the data pattern may be employed (for example, see Non-Patent Document 2).
L. Cotten, “Circuit Implementation of High-Speed Pipeline Systems,” Proc. Fall Joint Computer Conference of American Federation of Information Processing Societies (AFIPS) (1965) pp.489-504 Eduardo I. Boemo, Sergio Lopez-Buedo, Juan M. Meneses, “The Wave Pipeline Effect on LUT-Based FPGA Architectures,” Proc. Fourth International Symposium on Field Programmable Gate Arrays (FPGA '96), Monterey, CA, USA ( 1996) pp.45-50

Even when the above measures are attempted, it is difficult to completely align the delay time, and therefore, the application of the wave pipeline is extremely limited.
An object of the present invention is to control a logic circuit comprising transistor elements that eliminates the above-mentioned drawbacks and keeps the variation in processing time of each logical operation within a certain range, and variation in the processing time of each logical operation. It is to provide a delay control logic circuit that keeps the signal within a certain range.

  In order to achieve the above object, the present invention uses a logic circuit including a transistor having a control terminal for controlling the magnitude of the logic delay, and at the time when the input signal arrives earlier, the logic delay increases at the control terminal. At the time when the control signal is given and the input signal arrives late, a control signal that gives a control signal with a small logical delay to the control terminal is used.

  The time when the input signal arrives earlier or later is the maximum permissible value of the time shift assumed in the circuit design stage with respect to the reference time when the input signal is expected to reach the logic circuit. Means. Such a shift is naturally caused by factors such as differences in input data patterns, environmental changes such as power supply voltage, ambient temperature, noise, and manufacturing non-uniformity such as manufacturing variations. This is different from the actual deviation in the operating circuit. If the circuit is designed correctly, the actual signal arrival time must be between the time when the input signal arrives earlier and the time when the input signal arrives later.

In the present invention, since the actual signal arrival time is not used for the generation of the control signal, means for measuring and feeding back the actual signal arrival time is unnecessary.
In a logic circuit having a plurality of logic stages, the deviation of the logic delay from the reference time is accumulated as the number of stages increases, so that it is difficult or impossible to correct with one or a few stages of delay control logic circuits. Become. For this reason, a series of control signals are generated by a delay circuit so that the transition time from a control signal with a large logic delay to a control signal with a small logic delay is delayed as the logic stage advances. A control signal may be applied.
It is most effective to apply a control signal to all the logic stages, but if the control signal is applied to a part of the logic stages and the delay variation is sufficiently controlled, it is applied to all the logic stages. There is no need.

  For example, in the case where the entire circuit is composed of 10 logic stages, even if the control signal is applied to 5 logic stages every other stage, the delay variation can be sufficiently controlled. Absent. On the other hand, if the circuit as a whole consists of 10 logic stages and the circuit as a whole consists of 10 parallel paths, even if the control signal is applied to only half of the paths, the control signal application The intended delay cannot be achieved because the signal delay of the unrouted path is not solved at all. In this way, even when only a part of the logic elements are changed to elements with control signal terminals, except when there is a special path that is guaranteed at the design stage that the occurrence of variation in logic delay is particularly small, Logic elements with control signal terminals must be arranged in all paths.

  A logic circuit having the performance of controlling the magnitude of the logic delay is called a delay control logic circuit. In the conventional technology, it is difficult to find a positive meaning for controlling the delay of the logic circuit. However, in order to reduce the power consumption of the circuit, the entire circuit is set to a low power supply voltage when there is a margin for information processing. Thus, the delay of the logic circuit changes as a secondary effect of changing the substrate voltage of the entire circuit in order to drive it uniformly or to reduce the standby power consumption of the circuit.

An object of the present invention is to reduce the variation in logic delay. For this purpose, the delay control logic circuit generates a plurality of delay signals by using a logic circuit portion including a transistor having a control terminal for controlling the magnitude of the logic delay, and an input signal to the control terminal of the logic circuit portion. A delay circuit portion, and a time at which the input signal is applied to the logic circuit portion so that the control signal is switched at a correct timing with respect to a reference time of signal arrival in the logic circuit, and an input signal is input to the delay circuit portion. It is only necessary to have a signal input terminal for synchronizing the given time.
In order to realize such a control method and circuit (to achieve the above object), the present invention utilizes a field effect transistor or a double gate field effect transistor.

  FIG. 10A shows an element cross-sectional structure of the field effect transistor. In the figure, 11 is a substrate, 12 is a gate electrode, and 13 and 14 are a source region and a drain region, respectively. Although not shown, it is natural that the gate electrode, the source region, and the drain region are connected to the wiring of the circuit. A channel layer 15 is a place where an inversion channel layer is formed on the surface of the substrate by the electric field of the gate electrode 12. Reference numeral 16 denotes an insulating layer for insulating the gate electrode 12 from the channel layer 15.

  The substrate can be a p-type substrate in an N-type field effect transistor and an n-type substrate in a P-type field effect transistor. Further, when forming the N-type and P-type field effect transistors on one substrate, as shown in FIG. 10B, for example, a p-type substrate is used, and the portion in contact with the P-type field effect transistor is made of n-type impurities. An n-type well region 17 is formed, and a transistor is manufactured thereon. In the transistor formed in the well region, the potential control of the well region has the same effect as the substrate potential control. At this time, if the electrode 19 in the well region 17 is provided independently for each transistor, the substrate potential can be controlled independently for each transistor. When an N-type field effect transistor is manufactured using a p-type substrate, a well region is usually not required, but instead, substrate potential control is common to all transistors. When an N-type field effect transistor is manufactured using a p-type substrate and substrate potential control is to be performed independently for each transistor, an n-type well region 18 is provided in addition to the p-type well region 17. Thus, the potential of the well region 17 may be controlled by the electrode 19. If the substrate 11 and the well region 18 are also provided with electrodes and are not controlled to a constant voltage, the circuit operation becomes unstable. However, the control is not related to the present invention. There are other methods for realizing a structure for giving independent substrate potential control to each transistor, but in the present invention, any method may be used.

When the present invention is realized by a field effect transistor, a gate electrode is used as an input of a logic circuit, and a substrate potential control electrode is used as an electrode for controlling transistor characteristics.
FIG. 11 shows an element structure of the double gate field effect transistor. In the figure, the substrate 21 supports the entire element and must be in contact with the element with an insulating material. For this purpose, a structure in which the portion of the substrate 21 in contact with the element is covered with an insulator can be adopted, or it is covered with a layer such as a pn junction that can be electrically insulated by a substrate bias voltage. It is also possible to adopt the structure. 22 and 23 are gate electrodes, and 24 and 25 are a source region and a drain region, respectively. Although not shown, it is natural that the gate electrode, the source region, and the drain region are connected to the wiring of the circuit. The insulating layers 26 and 27 are insulating layers for insulating the gate electrodes 22 and 23 from the channel layer 28, respectively.

In FIG. 11, the double gate field effect transistor is placed horizontally and the substrate is arranged to support the lower electrode. However, if two gate electrodes are provided so as to sandwich the channel layer 28, the entire transistor No matter what the posture or how the substrate is supported, there is no problem with the implementation of the present invention.
When the present invention is realized by a double gate field effect transistor, one of the two gate electrodes is used as an input of a logic circuit, and the other is used as an electrode for controlling transistor characteristics.
The present invention utilizes the fact that the characteristics of the transistor change depending on the voltage applied to the substrate potential control electrode of the field effect transistor or one gate electrode of the double gate field effect transistor, and the delay of the logic operation can be controlled.

FIG. 12 schematically shows the electrical characteristics of the N-type field effect transistor of FIG. The vertical axis of the figure represents the drain current as a logarithmic axis, and the horizontal axis of the figure represents the voltage of the gate electrode 12. The curves shown in the figure are all obtained under the condition that the drain voltage is constant.
A curve 31 in the figure is a characteristic when the substrate potential is a negative value, typically about −1V, a curve 32 is a characteristic when the substrate potential is 0V, and a curve 33 is the substrate potential. Typically, the characteristics are obtained when the positive value is about 0.4V. The negative voltage applied to the substrate 11 can be increased freely as long as the source region 13, the drain region 14, and the substrate 11 do not break down, but a negative voltage power source must be newly added to the circuit. If the positive voltage applied to the substrate 11 is larger than about 0.5 V, a forward leakage current is generated between the source region 13 and the drain region 14 and the substrate 11, and the transistor does not operate normally. Within the range described above, the substrate potential can be changed freely.

  As the three curves 31 to 33 shown in the figure qualitatively show, when the substrate potential changes in the positive direction, the drain current flowing at the same gate voltage increases, and the substrate potential changes in the negative direction. Then, the drain current flowing at the same gate voltage decreases. The drain current charges the parasitic capacitance existing in the drain region, and further drives the load ahead of the output line connected to the drain terminal, thereby performing a logic operation determined by the gate signal. At that time, if more drain current can be obtained with the same gate electrode voltage, the delay time associated with the logic operation becomes smaller. Therefore, by controlling the voltage of the electrode 19, the logic delay of the transistor can be changed.

  FIG. 13 schematically shows electrical characteristics of three types of N-type double gate field effect transistors (see FIG. 11) having different internal structures. The curves in the figure are obtained under the condition that the drain voltage and the input voltage of the gate electrode 23 are constant, and correspond to elements having different thicknesses of the insulating layer 27, respectively. The vertical axis of the figure represents the drain current as a logarithmic axis, and the horizontal axis of the figure represents the input voltage of the gate electrode 22. A curve 34 represents a characteristic obtained by an element having the same thickness of the insulating layer 26 and the insulating layer 27, and a curve 35 represents a characteristic obtained by an element having the insulating layer 27 twice as thick as the insulating layer 26. Reference numeral 36 denotes a characteristic that the insulating layer 27 is obtained by an element having a thickness four times that of the insulating layer 26. The electrical characteristic indicated by the curve 36 is most marked by the change in the drain current due to the change in the input voltage of the gate electrode 22, and the electrical characteristic indicated by the curve 34 is the change in the drain current due to the change in the input voltage of the gate electrode 22. Is the calmest. The characteristics of commonly used field effect transistors are close to those shown by curve 35.

In the element in which the curve 34 is obtained, the thicknesses of the insulating layer 26 and the insulating layer 27 are equal, and it is often advantageous from the viewpoint of manufacturing the element. In particular, a process of simultaneously manufacturing the insulating layer 26 and the insulating layer 27 is employed. This structure is extremely advantageous. In addition, since the element that obtains the curve 34 can perform the fastest logic operation by applying the same input to the gate electrode 22 and the gate electrode 23, the device that uses the same input to the gate electrode 22 and the gate electrode 23 is used. This is advantageous when the device is manufactured by the same process as the device to be processed. However, when the gate electrode 23 is used as the transistor characteristic control electrode and only the gate electrode 22 is used as the signal input, the change in the drain current due to the change in the gate voltage of the gate electrode 22 is gentle. The signal amplitude for obtaining the ON / OFF current ratio becomes the largest.
In the element from which the curve 36 is obtained, the change in the drain current due to the change in the gate voltage of the gate electrode 22 is significant, so that the signal amplitude for obtaining a constant ON / OFF current ratio is the smallest. The element from which the curve 35 is obtained has intermediate characteristics.

  FIG. 14 schematically shows the electrical characteristics of the double gate field effect transistor shown in FIG. 11 with respect to three types of drain voltage conditions. The vertical axis of the figure represents the drain current as a logarithmic axis, and the horizontal axis of the figure represents the input voltage of the gate electrode 22. A curve 37 in the figure is a characteristic when the input voltage of the gate electrode 23 is a negative value, a curve 38 is a characteristic when the input voltage of the gate electrode 23 is 0 V, and a curve 39 is the characteristic of the gate electrode 23. This is a characteristic when the input voltage is set to a positive value. In the case where the substrate 21 is in contact with the transistor with an insulating material, the voltage applied to the gate electrode 23 can be freely increased as long as the source region, the drain region, and the substrate do not break down.

As qualitatively shown by the three curves 37 to 39 shown in the figure, when the voltage of the gate electrode 23 changes in the positive direction, the drain current flowing at the same input voltage at the gate electrode 22 increases, and the gate When the voltage at the electrode 23 changes in the negative direction, the drain current flowing at the same input voltage at the gate electrode 22 decreases. The drain current performs a logic operation determined by the gate signal by driving the load ahead of the output line connected to the drain terminal. At that time, if more drain current can be obtained with the same gate electrode voltage, the delay time associated with the logic operation becomes smaller. Therefore, by controlling the voltage of the gate electrode 23, the logic delay of the transistor can be changed.
Since the positional relationship between the gate electrode 22 and the gate electrode 23 is not related to the operation principle, the electrode for controlling the transistor characteristics is the gate electrode 22 in the upper portion of the element, and the electrode for performing the logical operation is the gate electrode 23 in the lower portion of the element. Is of course possible.

  Even if a field effect transistor is used as described above or a double gate field effect transistor is used, the same effect can be obtained in principle. However, in the field effect transistor, the pn junction between the source region and the drain region and the substrate is a load for a signal to the electrode 19, whereas in the double gate field effect transistor, the source region, the drain region, and the gate electrode Since there is only a slight overlap capacity with respect to 23, the amount of power required for control differs greatly, and the latter is significantly more advantageous. It is also important that the voltage range of the control signal is largely limited on the positive voltage side in the field effect transistor, but not limited in the double gate field effect transistor.

  The delay time control described above is performed in exactly the same manner even if the target is a P-type field effect transistor or a P-type double gate field effect transistor. However, the sign of the control signal is inverted. That is, in order to control to shorten the delay time, the input voltage of the electrode 19 or the gate electrode 23 is changed in the negative direction, and to control to increase the delay time, the electrode 19 or the gate electrode in the positive direction. What is necessary is just to change the input voltage of 23.

In order to perform the same control in the CMOS circuit, it is necessary to control the N-type and P-type transistors at the same time. Therefore, it is necessary to use two voltage signals having opposite polarities.
FIG. 3 illustrates transistor symbols used in the following description. In the description, a field effect transistor having a substrate potential control terminal and a double gate field effect transistor will be described using common symbols. 3A is a symbol representing an N-type field effect transistor or an N-type double gate field effect transistor, and FIG. 3B is a symbol representing a P-type field effect transistor or a P-type double gate field effect transistor. is there. In the figure, 41 represents a source terminal, 42 represents a drain terminal, and 43 represents a gate electrode. Reference numeral 44 denotes a substrate potential control electrode in a field effect transistor, and a gate terminal for controlling transistor characteristics in a double gate field effect transistor.

  An example of a NOT circuit (logic inversion circuit) using CMOS is shown in FIG. In the figure, 51 is an input terminal, 52 is an output terminal, 53 is a power supply terminal, and 54 is a ground terminal. Although 55 is an N-type transistor and 56 is a P-type transistor, both may be field effect transistors or double gate field effect transistors. Reference numerals 57 and 58 denote delay control terminals provided in the transistors 55 and 56, respectively, which are the substrate potential control electrodes 19 when the transistors are field effect transistors, and when the transistors are double gate field effect transistors. Is a gate electrode 23.

  The operation of this NOT circuit will be described with reference to FIG. In the figure, 61 represents the time variation of the voltage of the delay control terminal 57, 62 represents the time variation of the voltage of the delay control terminal 58, 63 represents the time variation of the voltage of the input terminal 51, and 64 represents the voltage of the output terminal 52. The time change of is shown. The voltage amplitude of the voltage waveforms 63 and 64 is the amplitude of the logic signal and is equal to the power supply voltage in the CMOS circuit. The voltage waveforms 61 and 62 are inverted in polarity, but their voltage amplitudes are not necessarily the same. Also, the voltage levels need not match. In particular, when a field effect transistor is used, the voltage level of 61 is generally set in a negative voltage region than the ground voltage, and swinging to a positive voltage of 0.5 V or more from the ground voltage causes many problems. In general, the voltage level 62 is set in the positive voltage region rather than the power supply voltage. Since a negative voltage of 0.5 V or more from the power supply voltage causes many problems, a common voltage level is adopted. I can't. There is no such problem in the double gate field effect transistor.

  FIG. 2A shows the voltage change of the output terminal when a signal is applied to the input terminal when the delay control terminal gives a signal that increases the delay of the circuit most. The delay is maximized. FIG. 2B shows the voltage change of the output terminal when a signal is applied to the input terminal when the delay control terminal gives a signal that reduces the delay of the circuit the most. Delay is minimized. An intermediate voltage of the signals shown in FIGS. 2A and 2B can be applied to the delay control terminal. At that time, the delay from the input to the output shows an intermediate value.

  The average of the maximum delay time and the minimum delay time is represented by T, and the difference between the maximum delay time and the average delay time T or the same, but the difference between the average delay time and the minimum delay time is In terms of ΔT, in the case of FIG. 2A, a delay of T + ΔT occurs from input to output, and in the case of FIG. 2B, a delay of T−ΔT occurs from input to output.

  FIG. 2C shows a case where arrival times of the input signals of the NOT circuit vary. In the example of the figure, the voltage at the delay time control terminal changes from a state where the delay time is large as shown in FIG. 2A to a state where the delay time is small as shown in FIG. As a result, when the input signal arrives the earliest, the result is reflected in the output with a delay of T + ΔT, and when the input signal arrives the latest, the result is reflected in the output with a delay of T−ΔT. Therefore, the time variation of the output signal is reduced by 2ΔT compared to the time variation of the input signal, and the variation is reduced.

Actually, the NOT circuit itself also causes new variations in delay time. That is, even when the arrival time of the input is determined without variation and the signal at the delay time control terminal is constant, the variation in the time at which the result is output can be ± δT. However, due to the effect of the delay time control terminal, as long as δT is smaller than ΔT, the variation in arrival time is reduced as a whole.
From these, by providing an appropriate signal to the delay time control terminal, not only can the arrival time variation of the signal reaching the circuit be reduced, but also the next stage due to the delay time variation newly generated by the element. It can be seen that it is possible to compensate for the arrival variation of the signal.

In the above example, the case where the data input signal changes from 1 to 0 has been described. However, since the cause of the delay time change is a change in the driving capability of the transistor, the same is true even when the data input signal is from 0 to 1. It is clear that the effect can be expected.
FIG. 1 shows the effect of delay time control in a general logic circuit 65. The logic circuit 65 may be any one of a NOT circuit, an AND circuit, an OR circuit, a composite circuit thereof, and a pass transistor circuit. In FIG. 1A, 66 represents a data input terminal, and 67 represents a data output terminal.

  FIG. 1B shows the voltage change of the output terminal when a signal is applied to the input terminal when the delay control terminal gives a signal that increases the delay of the circuit. In an actual use state, the timing at which data is applied to the input terminal varies even at one input terminal, and also varies among a plurality of terminals, and thus is determined after a certain time width. In the case of the figure, the variation at the output terminal is the same as the variation at the input terminal, and there is no new cause of variation. In the case of FIG. 1B, there is a delay of T + ΔT from input to output. FIG. 1C shows a change in the voltage at the output terminal when a signal is applied to the input terminal when the delay control terminal gives a signal for reducing the delay of the circuit. The time variation of the input terminal and the output terminal is the same as in FIG. In the case of FIG. 1C, there is a delay of T-ΔT from input to output.

  In FIG. 1D, the voltage at the delay time control terminal changes from the state where the delay time is large as shown in FIG. 1B to the state where the delay time is small as shown in FIG. Indicates. In the case of FIG. 1D, the result is reflected in the output with a delay of T + ΔT when the input signal is applied earliest, and the result with a delay of T−ΔT when the input signal is applied latest. Is reflected in the output. Therefore, the time variation of the output signal is reduced by 2ΔT compared to the time variation of the input signal, and the variation is reduced.

In practice, the logic circuit 65 itself also causes new delay time variations. That is, the variation of ΔT is newly added to the variation of the arrival time of the input. However, as in the case of the NOT circuit described with reference to FIG. 2, due to the effect of the delay time control terminal, as long as δT is smaller than 2ΔT, the variation in arrival time is reduced as a whole.
From these facts, by giving an appropriate signal to the delay time control terminal, not only can the time variation of the data output signal of the logic circuit 65 be reduced, but also the next due to the delay time variation newly generated by the logic circuit. It can be seen that it is possible to compensate for the arrival variation of the signal to the stage.

If the purpose is only to reduce the output time variation of the signal output from the logic circuit 65, δT does not need to be smaller than 2ΔT. That is, at the time when the input signal is applied earliest, a control signal that increases the logic delay is given, and at the time when the input signal is applied latest, the control signal that gives a smaller logic delay is given. If the control signal is switched at an intermediate point, the output time variation of the output signal is surely reduced as compared with the case where the control signal is not changed, and the object can be achieved.
On the other hand, if it is intended that the output time variation of the signal output from the logic circuit 65 does not become larger than the input time variation of the input signal, δT needs to be smaller than 2ΔT.

  In actual use, circuits corresponding to the logic circuit 65 are connected in multiple stages. In that case, the same effect can be obtained in each logic circuit 65 if the control signals of each stage are applied in a coordinated manner. Specifically, the target delay time of each stage is calculated, and if the target delay time of a specific logic circuit 65 is T, the subsequent logic circuit 65 that receives the output signal of that logic circuit receives the control signal. It is only necessary to cooperate so that the switching time is delayed by T compared to the specific logic circuit 65.

  As the target delay time T, an average delay time can be adopted, but the target delay time T is smaller than the largest delay time when a control signal that increases the logical delay is given without being precisely matched to the average delay time. If the control signal is selected to be greater than the smallest delay time when a control signal with a small delay is given, the control signal switching time is later than the earliest input application time and latest input application time. Is guaranteed to be faster.

  Thus, in order to apply the present invention to a large-scale logic circuit and configure a delay control logic circuit that reduces variations in signal propagation delay in the logic circuit, all the logic elements in the conventional logic circuit are configured. Or, if necessary, not only replace a part with a transistor having a delay control terminal, but also configure a delay circuit that simulates a target delay time in order to give a control signal to each transistor at an appropriate timing. The timing between the control signals may be adjusted. In addition, in order to synchronize the input timing of the signal input to the logic circuit and the operation start timing of the delay circuit, the signal for controlling the timing of applying the signal to the input terminal of the first stage logic circuit and the operation of the delay circuit The signals for controlling the start may be the same signal or controlled by a common signal.

  A logic circuit including a transistor having a control terminal for controlling the magnitude of the logic delay; a delay circuit that generates a plurality of delay signals and inputs them to the control terminal; and an input signal timing of the logic circuit and a delay circuit In the delay control logic circuit having a signal input terminal that synchronizes the operation start timing of the signal, the variation in the propagation delay of the signal is reduced, and the control width of the magnitude of the logic delay is larger than the generation amount of the variation in the logic delay. In this way, even after the signal has propagated through an arbitrary number of stages, the signal propagation delay variation remains within a certain range, so all the latch circuits provided for the purpose of eliminating the signal propagation delay variation are omitted. It becomes possible.

In the present invention, a logic circuit is configured using a field effect transistor having a substrate potential control electrode, a double gate field effect transistor, or both, and in the case of a field effect transistor, the substrate potential control electrode is In the case of a double gate field effect transistor, one electrode of the transistor is used as a terminal for delay time control, and there is an effect of reducing variation in signal propagation delay in the logic circuit.
In the delay control logic circuit according to the present invention, it is necessary to add a delay control terminal to a conventional logic circuit and provide a delay control signal generation circuit such as a delay circuit to generate a signal to be supplied to the delay control terminal. Of the temporary storage circuits required for data processing synchronization, the temporary storage circuits 2 and 5 existing in the interface portion between the target logic circuit and the external circuit are provided in the logic circuit. The temporary storage circuit 7 that has been used can be omitted.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

  FIG. 5 shows an example of implementation of the present invention. In FIG. 5, a partial logic circuit 71 is obtained by dividing a logic circuit into a small number of logic stages and connecting them in series with a plurality of signal lines. The internal configuration of the partial logic circuit 71 may be a set of logic circuits that are not connected to each other by logic signal lines as shown in FIG. 5B, for example. Compared to the partial logic circuit 6, the partial logic circuit 71 is composed of a logical face having one or a very small number of logical stages. Reference numeral 72 denotes a delay circuit which gives a target delay time in each partial logic circuit based on the signal supplied from the clock signal line 3. The delay time of the delay circuit 72 is designed separately for each stage according to the target propagation delay time of the corresponding partial logic circuit 71. As shown in FIG. 5C, in this embodiment, the target delay time is created by the serial connection of NOT circuits, but other methods may of course be used. A circuit 73 amplifies the signal supplied from the delay circuit. The amplifying circuit 73 provides a driving capability for driving the delay time control terminals 57 and 58 of the elements in the partial logic circuit 71 and at the same time adjusts the voltage level. This can be omitted if voltage level adjustment is not necessary and drive capability does not need to be increased. The signal applied to the delay control terminal 57 and the signal applied to the delay control terminal 58 have a time difference corresponding to one stage of the NOT circuit. However, this may be left as long as extremely small delay time variations are not targeted, and the amplifier circuit. You may adjust by 73. It is naturally possible to configure the circuit so that the amplifier circuit 73 is an inverting amplifier. The delay time control signal may be applied to all the logic elements in the partial logic circuit 71, or may be applied only to a point where the signal propagation time varies greatly and needs to be converged.

  The signal supplied from the temporary storage circuit 2 propagates through the partial logic circuit 71 to perform information processing. In any stage, the signal that arrives earlier than the target time is controlled by the delay time control supplied from the delay circuit 72. Information must be processed with a large logic delay by the action of the signal. On the other hand, a signal that arrives later than the target time is processed by a logic circuit with a small logic delay by the action of the delay time control signal supplied from the delay circuit 72. Thereby, the signal propagating through the logic circuit does not deviate greatly from the target propagation speed defined by the delay circuit 72.

  The signal propagating through the delay circuit 73 may also deviate from a periodic signal according to the propagation. However, since the delay circuit is configured by a NOT circuit with a constant load, the variation is in series with the partial logic circuit 71. It is much smaller than the original variation of the connection, so the variation in delay time is greatly improved.

  FIG. 6 shows another embodiment 2 of the present invention. The same components as those in FIG. 5 will be described with the same numbers. In the figure, reference numeral 74 denotes a multi-phase clock generation circuit, which generates a plurality of clock signals whose phases are shifted in addition to the clock supplied to the temporary storage circuit 2. Each clock signal is amplified, adjusted in voltage level, and finely adjusted by the amplifier circuit 73 as in the embodiment of FIG. Although a three-phase clock circuit is shown in the figure, the number of clock phases can be freely increased.

  In this embodiment, not only the delay time at each stage is controlled, but also the arrival time at the temporary storage circuit 5 is synchronized with the clock for driving the temporary storage circuit 5. Not only can the contents of the temporary storage circuit 5 be updated reliably, but the total propagation time defined by the clock cycle can be distributed to each stage without waste. In FIG. 6, a clock having the same phase as that of the temporary storage circuit 2 is also supplied to two intermediate logic stages. In such a case, the clock cycle can be shortened to one third of the total delay time of the logic circuit.

FIG. 7 shows a third embodiment in which the present invention is applied when pipelines having different numbers of stages are parallel. The same components as those in FIG. 6 will be described with the same numbers. In the figure, it is assumed that a pair of signal lines labeled A, B, and C are connected to each other. The internal configuration of each partial logic circuit 71 in the drawing may be a set of logic circuits that are not connected to each other by logic signal lines as shown in FIG. 5B.
In this embodiment, a path for processing a signal with a delay of three clock cycles and a path for processing a signal with a delay of two clock cycles are parallel from the temporary storage circuit 2 to the temporary storage circuit 5. Therefore, since a shift of one clock cycle occurs at the place where both paths merge, it is necessary that the partial logic circuit after the merge be configured in consideration of the circumstances.

In such a pipeline configuration, processing with different calculation amounts, for example, integer addition processing that can be processed with a relatively short pipeline, and integer multiplication processing that requires a relatively long pipeline are performed in parallel. Occurs in some cases. Both routes may be used at the same time, or a usage method in which one route is always selected at a specific time.
The present invention can also be applied to such a pipeline.

  FIG. 8 shows a fourth embodiment in which the present invention is applied to a pipeline circuit having a feedback loop. The same components as those in FIG. 7 will be described with the same numbers. In this figure, it is assumed that a pair of signal lines labeled A, B, and C are connected to each other. The internal configuration of each partial logic circuit 71 in the drawing may be a set of logic circuits that are not connected to each other by logic signal lines as shown in FIG. 5B.

In this embodiment, a circuit branched from the middle of the pipeline flow composed of partial logic circuits joins upstream of the pipeline to form a feedback loop. Such a circuit configuration is used when iterative information processing is required or when canceling processing based on prediction such as branch prediction or speculative execution. As is apparent from the figure, even when such a loop exists, it is possible to configure the pipeline by omitting the temporary storage circuit at the branch point and the junction.
Considering the circuit configurations in the second and third embodiments, in the circuit configuration in the present invention, the temporary storage circuit 7 required in the conventional pipeline is replaced with another circuit using a circuit configuration not according to the present invention. Except for the interface, it can be omitted in most cases, and it can be seen that the high information processing capability that the wave pipeline has aimed for can be realized very easily.

It is a figure explaining operation | movement of the logic circuit provided with the delay time control terminal. It is a figure explaining operation | movement of the NOT circuit provided with the delay time control terminal. It is a figure explaining the circuit symbol of a transistor. It is a figure of the NOT circuit by CMOS provided with the delay time control terminal. FIG. 6 is a diagram of an embodiment of a delay control logic circuit (using a delay circuit to generate a delay time control signal). FIG. 6 is a diagram of an embodiment of a delay control logic circuit that uses a multiphase clock circuit (for generating a delay time control signal). FIG. 6 is a diagram of an embodiment of a delay control logic circuit including (applied to) pipelines with different path lengths. FIG. 4 is a diagram of an example of a delay control logic circuit (applied to a circuit) including a feedback loop. It is a figure showing a clock synchronous logic circuit. It is a figure showing the cross-section of a field effect transistor. It is a figure showing the cross section of a double gate field effect transistor. It is a figure showing the effect of substrate potential control of a field effect transistor. It is a figure showing the transistor characteristic when one gate electrode of a double gate field effect transistor is fixed. It is a figure showing the effect of the transistor characteristic control by one gate electrode of a double gate field effect transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Logic circuit 2 ... Temporary memory circuit 3 which supplies data to the logic circuit 1 ... Clock signal line 4 ... Multiple data lines 5 ... Temporary memory which receives result data from the logic circuit 1 Circuit that is the same as or different from the temporary storage circuit 2 6... Partial logic circuit 7 obtained by partitioning the logic circuit 1... Temporary storage circuit inserted at the boundary where the logic circuit 1 is divided 11. substrate 12 gate electrode 13 source region 14 drain region 15 channel layer 16 insulating layer 17 well region 18 having a well structure double well structure Outer well region 19... Electrode 21 provided in well region 17... Substrate 22 of double gate field effect transistor... Upper gate electrode 23 of double gate field effect transistor. Lower gate electrode 24 of effect transistor, source region 25, drain region 26, insulating layer 27 of gate electrode 22, insulating layer 28 of gate electrode 23, channel layer 31 of double gate field effect transistor, substrate Electrical characteristics 32 when the potential is set to a negative value ... Electrical characteristics 33 when the substrate potential is set to OV ... Electrical characteristics 34 when the substrate potential is set to a positive value 34 ... The insulating layer 26 and the insulating layer 27 Electrical characteristics obtained with elements having the same thickness 35... Electrical characteristics obtained with elements whose insulating layer 27 is twice as thick as the insulating layer 26... Insulating layer 27 is four times as thick as the insulating layer 26 Electrical characteristics 37 obtained by the element of FIG. 37. Electrical characteristics 38 when the gate electrode 23 is set to a negative voltage 38 Electrical characteristics 39 when the gate electrode 23 is set to OV When the gate electrode 23 is set to a positive voltage Electrical characteristics of 41 ・Source terminal 42 ..Drain terminal 43 ..Gate electrode 44 ..Substrate potential control electrode of field effect transistor or gate terminal 51 for delay time control of double gate field effect transistor ..Input terminal 52 ..Output terminal 53. Power terminal 54 .. Ground terminal 55.. N-type field effect transistor or N-type double gate field effect transistor 56... P-type field effect transistor or P-type double gate field effect transistor 57. Terminal 58 .. delay time control terminal 61 of transistor 56 .. time change 62 of voltage at delay time control terminal 57 .. time change 63 of voltage at delay time control terminal 58 .. time change 64 of voltage at input terminal 51. The time change 65 of the voltage of the output terminal 52. The logic circuit 66. The data input terminal 67. Time change 69 of the state of the output terminal 68... Time change 71 of the state of the data input terminal 67... Partial logic circuit 72 divided into a small number of logic stages. Circuit 74... Multiphase clock circuit A... Control signal pair B connected to each other. Control signal pair C connected to each other. Control signal pair connected to each other.

Claims (12)

  In a method for controlling a logic circuit including a transistor having a control terminal for controlling the magnitude of the logic delay, at the time when the input signal arrives earlier, a control signal for increasing the logic delay is given to the control terminal, and the input signal A control method for a logic circuit, wherein a control signal that reduces a logic delay is given to the control terminal at a time when the signal arrives late.   The logic circuit control method according to claim 1, wherein the magnitude of the logic delay is set so that the transition time from the control signal in which the logic delay increases to the control signal in which the logic delay decreases is delayed as the logic stage advances. A control method of a logic circuit, wherein a control signal is applied to a plurality of transistors having the control terminal to be controlled.   3. The method of controlling a logic circuit according to claim 2, wherein a logic delay in a next logic stage is large from a transition time from a control signal in which a logic delay is large to a control signal in which a logic delay is small in an arbitrary logic stage. The time from the control signal to the transition time to the control signal where the logic delay becomes smaller is smaller than the maximum propagation delay time from the arbitrary logic stage to the next logic stage under the control signal where the logic delay becomes larger, Deviation in transition time between the two control signals and the two logic stages so as to be larger than the minimum propagation delay time from the arbitrary logic stage to the next logic stage under the control signal where the logic delay becomes small A method for controlling a logic circuit, characterized by:   4. The method of controlling a logic circuit according to claim 2, wherein a transition time from a control signal having a large logic delay to a control signal having a small logic delay is applied so that the transition time is delayed as the logic stage advances. Are simultaneously generated at positions separated by a plurality of logic stages, whereby a plurality of logic operations are simultaneously performed in the same circuit.   5. The method of controlling a logic circuit according to claim 1, wherein a field effect transistor having a substrate potential control electrode is used as a transistor having a control terminal for controlling the magnitude of logic delay, and the substrate potential is controlled. A method for controlling a logic circuit, wherein the control electrode is used as a control terminal for controlling the magnitude of logic delay.   5. The method of controlling a logic circuit according to claim 1, wherein a double gate field effect transistor is used as a transistor having a control terminal for controlling the magnitude of the logic delay, and two of the two gate electrodes are used. One of the above is used as a control terminal for controlling the magnitude of the logic delay.   A logic circuit including a transistor having a control terminal for controlling the magnitude of the logic delay; a delay circuit that generates a plurality of delay signals and inputs the signals to the control terminal; and a time at which the input signal is given to the logic circuit And a signal input terminal for synchronizing a time at which an input signal is given to the delay circuit.   The delay control logic circuit according to claim 7, wherein the input signal arrives early at a time when the transistor having the control terminal for controlling the magnitude of the logic delay in an arbitrary logic stage of the delay control logic circuit is reached. The control in the delay control logic circuit is provided such that a control signal for increasing the logic delay is applied to the control terminal, and a control signal for decreasing the logic delay is applied to the control terminal at a time when the input signal arrives late. A delay control logic circuit characterized by selecting a delay amount of a signal.   9. The delay control logic circuit according to claim 8, wherein, in an arbitrary logic stage of the delay control logic circuit, from a transition time from a control signal with a large logic delay to a control signal with a small logic delay, in a next logic stage. The maximum propagation delay from the arbitrary logical stage to the next logical stage under the control signal where the logic delay increases is the time from the control signal where the logical delay increases to the control signal where the logic delay decreases Between the two control signals and the two logic stages so as to be greater than the minimum propagation delay time from the arbitrary logic stage to the next logic stage under a control signal that is smaller than the time and has a smaller logic delay. A delay control logic circuit characterized by selecting a delay amount.   10. The delay control logic circuit according to claim 9, wherein a plurality of signal sequences are applied so that a transition time from a control signal with a large logic delay to a control signal with a small logic delay is delayed as the logic stage advances. The delay control logic circuit is characterized in that a plurality of logic operations are simultaneously performed in the same circuit by causing them to occur simultaneously at positions separated by the logic stage.   11. The delay control logic circuit according to claim 7, wherein a field effect transistor having a substrate potential control electrode is used as a transistor having a control terminal for controlling the magnitude of the logic delay, and the substrate potential control is performed. A delay control logic circuit characterized in that an electrode is used as a control terminal for controlling the magnitude of a logic delay.   11. The method of controlling a logic circuit according to claim 7, wherein a double gate field effect transistor is used as a transistor having a control terminal for controlling the magnitude of the logic delay, and two of the gate electrodes are used. One of these is used as a control terminal for controlling the magnitude of the logic delay.

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