JP2005070951A - Program processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a program processing apparatus for improving the efficiency of software debug. <P>SOLUTION: A back trace circuit 22 monitors an internal bus 26 of a CPU core 21 which executes a program, and monitors a previously designated branch instruction in the program. Then, when branch is generated in the program, the branch origin address value is acquired from a program counter 32 through the internal bus 26, and stored in an internal register in the order of the generation of branch. A debug tool 14 receives the branch origin address value stored in the internal register from the CPU core 21 through a debug I/F 23, and calculates the execution path of the program based on the address value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a program processing apparatus, and more particularly to a control LSI suitable for use when performing operation verification of embedded software (firmware) or the like.

In recent years, LSIs such as microcomputers with built-in CPUs are used for embedded applications, and evaluation chips (hereinafter referred to as “evaluation chips”) are generally used for software development. In the evaluation chip, in addition to the CPU mounted on the target system, an interface circuit that supports software debugging is mounted. Software debugging is performed by connecting an in-circuit emulator (ICE (R)) to an evaluation chip mounted on the user board and giving a debugging command from the ICE to the CPU. For example, Patent Document 1 is known as a prior art related to a debugging system using an evaluation chip.
JP-A-11-282712

  By the way, in an SOC (System On a Chip) or the like in which peripheral circuits including a CPU are mounted on one chip to realize a system level function, the CPU bus and control signals are concentrated inside the chip. There was a problem that debugging efficiency was lowered. That is, in such software development in SOC, since it is necessary to perform debugging by placing the CPU on the evaluation board individually, the development cost for finally making one chip is required, and the design period becomes longer and TAT becomes longer. There was a problem of lowering (Turn Around Time).

  In addition, it is required to reduce the test cost of such software debugging as much as possible, and the number of terminals that can be used for debugging is limited to a small number. For this reason, there has been a problem that debugging cannot be performed efficiently.

  At present, in the software development stage, breakpoints are set in advance in the source code of the program, and debugging is performed by stopping the execution of the program when passing through it. However, this method has a problem that debugging work is complicated because it is necessary to rewrite the program memory to set a breakpoint.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a program processing apparatus capable of improving the efficiency of software debugging.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a program processing device comprising: a CPU for executing a program; and the CPU integrated on the same semiconductor substrate as the CPU. The internal bus used for access and the internal bus are monitored to monitor one or more pre-designated branch instructions in the program, and the branch source address value is stored when a branch occurs in the program A back trace circuit. According to this configuration, the execution path of the program can be traced from the branch source address value of the branch instruction monitored by the back trace circuit while the CPU is mounted on the chip. Thereby, debugging work can be performed efficiently.

  According to a second aspect of the present invention, a program processing device includes a CPU that executes a program and an internal bus that is integrated on the same semiconductor substrate as the CPU and that is used when the CPU accesses a memory space. And a backtrace circuit that monitors the internal bus, monitors a plurality of pre-designated branch instructions in the program, and stores a branch source address value when a branch occurs in the program, and The back trace circuit includes an internal register that holds a plurality of branch source address values in the order of branch generation. According to this configuration, the execution path of the program can be traced from the branch source address value of the branch instruction monitored by the back trace circuit while the CPU is mounted on the chip. In this configuration, even when a new branch occurs when the internal register overflows, the oldest branch source address value held in the internal register is erased and the new branch source address value is held. The As a result, it is possible to efficiently perform debugging work while preventing loss of trace information.

  According to a third aspect of the present invention, the backtrace circuit includes a condition setting register in which the type of branch instruction to be monitored is set in advance. According to this configuration, a branch instruction to be traced can be arbitrarily set.

  According to the present invention, it is possible to provide a program processing apparatus capable of improving the efficiency of software debugging.

  Hereinafter, an embodiment in which a program processing apparatus according to the present invention is applied to a control LSI for debugging firmware, for example, will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a debugging system 11 according to this embodiment. The debug system 11 includes a control LSI 12 as a program processing device and a personal computer (hereinafter referred to as PC) 13 as a debug device connected to the control LSI 12 via a tool bus. As will be described later, the control LSI 12 is a system LSI that implements system-level functions by mounting peripheral circuits including a CPU on one chip. The PC 13 has a debugging tool 14 made of, for example, ICE (R) or the like.

  More specifically, the control LSI 12 includes a debugging terminal (not shown), and a tool bus bus cable 15 is connected to the debugging terminal. In order to reduce the influence on the chip size of the control LSI 12, the debugging terminals are provided in a small number (for example, 2 pins in this embodiment), and the control LSI 12 performs serial communication with the debug tool 14 via the bus cable 15. In this embodiment, a clock bus and a data bus are connected to the two debugging terminals, respectively, and data transfer (bidirectional) between the control LSI 12 and the debug tool 14 is performed in synchronization with the clock. ing.

  The control LSI 12 includes a CPU core 21, a back trace circuit 22, a debug interface (hereinafter referred to as a debug I / F) 23, an external bus interface (hereinafter referred to as an external bus I / F) 24, and an internal RAM 25 as a peripheral circuit on the same semiconductor substrate. Have. The control LSI 12 also has a signal processing circuit whose operation is controlled by the CPU core 21 (not shown).

  The CPU core 21, the back trace circuit 22, the external bus I / F 24, and the internal RAM 25 are connected to each other via an internal bus 26. The CPU core 21 and the back trace circuit 22 are connected via an internal bus 27, and the CPU core 21 and the debug I / F 23 are connected via an internal bus 28.

  A program memory 30 is connected to the external bus I / F 24 via an external bus 29. In this embodiment, the program memory 30 is configured by a flash memory, for example, and firmware to be debugged is stored in a form that can be executed by the CPU core 21. Specifically, firmware (program) described in a high-level language such as C language is subjected to compile processing and link processing, converted into a machine language instruction sequence that can be executed by the CPU core 21, and stored. ing.

  The CPU core 21 includes a state machine 31 and a program counter 32. The state machine 31 reads a program (instruction) stored in the program memory 30 using the program counter 32 and decodes the read instruction. Various processes according to the decoding result are executed by accessing an area (memory space) mapped to the memory map of the CPU core 21. In this embodiment, the memory space accessed by the CPU core 21 includes a memory space such as a peripheral circuit (not shown) connected via the external bus 29 in addition to the internal RAM 25 connected via the internal bus 26. Including.

  The program counter 32 stores the address value of the instruction currently being executed by the CPU core 21. The state machine 31 reads an instruction according to the program counter 32 and increments the address value stored in the counter 32 every time the instruction is read.

  The back trace circuit 22 monitors the internal bus 26 used when the CPU core 21 accesses the memory space, and monitors which program the CPU core 21 is currently executing. Then, when a branch occurs in the program executed by the CPU core 21, the back trace circuit 22 acquires the address value of the branch source instruction (hereinafter referred to as the branch source address value) from the program counter 32 through the internal bus 26, Store in the internal register 41 (FIG. 2).

  As shown in FIG. 2, the internal register 41 of the present embodiment can store, for example, 16 branch source address values. The branch source address value acquired by the back trace circuit 22 is the monitor data “MON0”. To MON15 "in the order of branch occurrence. In the present embodiment, the branch source address value is stored as 8-bit data (24 bits in total) in the first, second, and third registers “ADRH”, “ADRM”, and “ADRL”, respectively. It has become.

  For example, when the back trace circuit 22 detects that a branch has occurred in the program being executed, the first, second, and third registers “ADRH”, “ADRM”, and “ADRL” shown in FIG. : 0000h ”,“ 03: 0001h ”,“ 03: 0002h ”, a total of 24 bits of branch source address values are stored as monitor data“ MON0 ”. Thereafter, the back trace circuit 22 stores the branch source address value as monitor data “MON1,” “MON2,”... MON15 every time a branch occurs in the program, and after capturing the monitor data “MON15” The branch source address values are stored again as monitor data “MON0”, “MON1”. That is, when the internal register 41 reaches the overflow, the back trace circuit 22 erases the oldest branch source address value stored in the register 41 and stores the newly acquired branch source address value. It has become.

As shown in FIG. 3, the back trace circuit 22 has a condition setting in which the type of branch instruction monitored by the back trace circuit 22 (stores the branch source address value) in the instruction set of the CPU core 21 is set in advance. A register 51 is provided. The branch instruction is an instruction that causes a program branch, and the branch instruction includes a conditional branch instruction, an unconditional branch instruction, a call instruction, and a return instruction.

  For example, in the case of the INTEL CPU 80251, the condition setting register 51 shown in FIG. ”And“ RET ”are set.

  Incidentally, in the present embodiment, the following branch instruction is specifically set by setting the condition setting register 51 as described above.

"AJMP" ... AJMP, ACALL
"LJMP" ... LJMP, LCALL
"EJMP" ... EJMP, ECALL, ERET, RETI
"JMP" ... JMP
"REL" ... JB, JBC, JNB, JC, JE, JG, JLE, JNC, JNE, JNZ, JSG, JSGE, JSL, JSLE, JZ, CJNE, DJNZ, SJMP
"RET" ... RET
Note that the type of branch instruction described here shows a specific example, and is not limited to this example. Moreover, you may limit to some of these branch instructions.

  When the branch instruction set in the condition setting register 51 is read into the CPU core 21, the back trace circuit 22 monitors whether or not a program branch occurs in the branch instruction through the internal bus 26. When a branch occurs, the branch source address value is acquired from the program counter 32 and stored in the internal register 41.

  When debugging is performed using the control LSI 12 including such a backtrace circuit 22, the debug tool 14 executes a program based on an instruction from a developer (user) input from an input device (not shown) of the PC 13. The operation of the CPU core 21 (execution of the program) is interrupted at any arbitrary position. Then, the debug tool 14 receives the branch source address value stored in the internal register 41 of the backtrace circuit 22 from the control LSI 12. Specifically, the CPU core 21 reads the branch source address value stored in the internal register 41 via the internal bus 27 and reads the branch source address value from the debug I / F 23 via the bus cable 15. 14 to send. At this time, in this embodiment, since the bus cable 15 has two pins, serial data is transmitted.

  The debug tool 14 calculates an execution path of the program based on the branch source address value received from the control LSI 12, and displays the display device (for example, C language or assembler) of the PC 13 at a source level (for example, C language or assembler). (Not shown). As a result, the user confirms the operating state of the program, corrects bugs, etc., and proceeds with debugging.

  According to this embodiment described above, the following effects are obtained.

  (1) When a branch occurs in the program, the back trace circuit 22 acquires the branch source address value from the program counter 32 through the internal bus 26 and stores it in the internal register 41. According to this configuration, the execution path of the program can be traced from the branch source address value of the branch instruction monitored by the back trace circuit 22 while the CPU core 21 is mounted in the chip (control LSI 12). Thereby, debugging work can be performed efficiently.

  (2) In the present embodiment, the function of the debug tool 14 can be used to stop the program at any point of the user and proceed with debugging. Thereby, debugging work can be performed efficiently.

  (3) In the present embodiment, the branch occurrence location in the program is monitored, and debugging is performed based on the branch source address values sequentially transmitted serially from the control LSI 12. In this method, debugging can be realized by two bus cables 15 of a clock bus and a data bus. Thus, by reducing the number of debugging terminals, it is possible to efficiently perform debugging work while suppressing an increase in the chip size of the control LSI 12.

  (4) In this embodiment, since the user can estimate the execution path of the program from the branch source address value, the frequency of setting a breakpoint for debugging in the source code of the program can be reduced as compared with the prior art. For this reason, the rewriting work of the program memory for setting a breakpoint can be greatly reduced.

  (5) In this embodiment, in software development such as a microcomputer, software debugging can be performed with the CPU (CPU core 21) mounted. Thereby, software development efficiency can be improved and development cost can be reduced. As a result, the TAT can be improved by shortening the design period.

  The above embodiment may be modified as follows.

  In the present embodiment, the control LSI 12 (system LSI) includes the internal RAM 25, but the peripheral circuit mounted together with the CPU core 21 in the chip is not limited to the present embodiment.

  The configuration of the internal register 41 of the back trace circuit 22 is not limited to the mode shown in FIG. That is, the acquisition of the branch source address value is not necessarily performed in 24 bits. Further, the number of branch source address values held as monitor data is not limited to the number exemplified in this embodiment.

  The configuration of the condition setting register 51 of the back trace circuit 22 is not limited to the mode shown in FIG.

  In the present embodiment, the present invention is applied when firmware is debugged. However, the present embodiment is not limited to this application example.

The technical idea that can be grasped from the above embodiment will be described below.
(B) The CPU has a program counter for storing the address value of the instruction currently being executed,
The back trace circuit is
4. The program processing apparatus according to claim 1, wherein when a branch occurs in the program, the branch source address value is acquired from the program counter through the internal bus. 5.
(B) The CPU executing the program and the internal bus used when the CPU accesses the memory space are monitored to monitor one or more pre-designated branch instructions in the program, and a branch occurs in the program A backtrace circuit that stores the branch source address value when the program processing device is provided on the same chip,
A debugging system connected to the program processing device and receiving a branch source address value taken in by the backtrace circuit and calculating an execution path of the program from the branch source address value .

1 is a block diagram illustrating a schematic configuration of a debugging system according to an embodiment. FIG. It is explanatory drawing which shows the internal register of a back trace circuit. It is explanatory drawing which shows the condition setting register | resistor of a back trace circuit.

Explanation of symbols

  12: Control LSI as program processing device, 13: Personal computer (PC) as debug device, 21: CPU core as CPU, 22: Back trace circuit, 25: Internal RAM as peripheral circuit, 26: Internal bus, 41: Internal register, 51: Condition setting register.

Claims (3)

A CPU for executing the program;
An internal bus used when the CPU integrated on the same semiconductor substrate as the CPU accesses the memory space;
A back trace circuit that monitors the internal bus and monitors one or more pre-designated branch instructions in the program, and stores a branch source address value when a branch occurs in the program;
A program processing apparatus comprising: A CPU for executing the program;
An internal bus used when the CPU integrated on the same semiconductor substrate as the CPU accesses the memory space;
A backtrace circuit that monitors the internal bus and monitors a plurality of pre-designated branch instructions in the program, and stores the branch source address value when a branch occurs in the program, and
The back trace circuit includes an internal register for holding a plurality of branch source address values in the order of branch generation. The back trace circuit includes
3. The program processing apparatus according to claim 1, further comprising a condition setting register in which a type of branch instruction to be monitored is set in advance.

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