JP2005064345A - Semiconductor device - Google Patents

Abstract

In a semiconductor device to which a resurf structure is applied, an ESD resistance is increased and an on-resistance is decreased.
An n ⁺ drain region is brought into contact with an n offset region, and the n offset region is brought into contact with an n well region, whereby an n ⁺ drain region and an n offset region are provided immediately below a drain electrode. And a parasitic pn diode in which an n region composed of an n well region 22 and a p region composed of a p-type semiconductor substrate 21 are joined to form a parasitic pn diode when a high ESD voltage is applied to the drain electrode 31. A reverse bias is applied to cause a breakdown current to flow between the drain electrode 31 and the back electrode 33.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device used as a switching device, and in particular, forms a lateral insulated gate field effect transistor (hereinafter referred to as a MOSFET) having high surge resistance such as ESD resistance and low on-resistance per unit area. The present invention relates to a semiconductor device.

FIG. 8 is a cross-sectional view showing a unit structure of an n-channel lateral MOSFET which is one of conventional switching devices. Note that in this specification, a layer or region bearing n or p is a layer or region having electrons and holes as majority carriers, respectively. Further, n ⁺ and p ⁺ no ⁺ means that a relatively high concentration.

In FIG. 8, an n-well region 2 is formed on the surface layer of a p-type semiconductor substrate 1, and an n-well electrode 14 in contact with the surface of the n-well region 2 is provided. A p well region 3 is formed in the surface layer of the n well region 2, and an n ⁺ source region 4 and a p ⁺ contact region 5 are formed in the surface layer of the p well region 3. A source electrode 10 in common contact is provided on the surfaces of the n ⁺ source region 4 and the p ⁺ contact region 5.

Further, an n ⁺ drain region 8 is formed in a portion of the surface layer of the p well region 3 away from the n ⁺ source region 4, and a drain electrode 11 is provided on the surface thereof. The drain electrode 11 is normally connected to the same potential as the n-well electrode 14. An n offset region 9 is formed in the surface layer of the p well region 3 between the n ⁺ drain region 8 and the n ⁺ source region 4 so as to include the n ⁺ drain region 8.

A gate electrode 7 is formed on the surface of the p well region 3 sandwiched between the n offset region 9 and the n ⁺ source region 4 via a gate oxide film 6. A LOCOS oxide film 12 is formed between the drain side end of the gate electrode 7 and the n ⁺ drain region 8 for the purpose of relaxing the electric field directly under the gate electrode on the n ⁺ drain region 8 side. In addition, a back electrode 13 that is normally connected to the same potential as the source electrode 10 is formed on the back surface of the p-type semiconductor substrate 1.

In FIG. 8, when a positive voltage is applied to the drain electrode 11 with respect to the source electrode 10 and a voltage equal to or lower than the gate threshold is applied to the gate electrode 7, between the p well region 3 and the n offset region 9. Since the pn junction is in a reverse-biased state, no current flows. On the other hand, when a voltage higher than the gate threshold is applied to the gate electrode 7, an inversion layer is formed on the surface of the p well region 3 immediately below the gate electrode 7, and the n ⁺ drain region 8 to the n offset region 9 and the p well region 3 A current flows along a path that reaches the n ⁺ source region 4 through the surface inversion layer in order, and a well-known MOSFET switching operation can be performed.

In the MOSFET having such a structure, the n offset region 9 in the p-well region 3 is used as a drift region in which the main current of the MOSFET flows. However, since it is necessary to deplete at the time of reverse bias, the depth of the drift region is reduced. It is difficult to take enough. Therefore, it is effective to apply a so-called RESURF structure that makes the total amount of impurities per unit area appropriate even in the case of a high breakdown voltage of several hundreds V or more and a relatively low breakdown voltage of several tens of V or less. is there. In this case, the total amount of impurities per unit area of the n offset region 9 is about 1 × 10 ¹² cm ⁻² which is a so-called RESURF condition.

If the p-well region 3 cannot be formed sufficiently deep, the depletion layers extending from the pn junction between the p-well region 3 and the n-n offset region 9 and between the p-well region 3 and the n-well region 2 are directly below the n-offset region 9. It is effective to use a so-called double resurf condition in which the p-well region 3 is completely depleted. In this case, the total amount of impurities in the p well region 3 immediately below the n offset region 9 is about 2 × 10 ¹² cm ⁻² . The lateral MOSFET having such a structure can be isolated from the substrate in the n-well region 2 and has a high degree of freedom with respect to the potentials of the drain electrode 11 and the source electrode 10, so that a plurality of high-side MOSFETs and low-side MOSFETs are provided. This is effective in the case of integrating them in the same chip.

  However, in the conventional lateral MOSFET shown in FIG. 8, although not clearly understood, the n-well has the same potential as the drain, but a potential difference is likely to occur due to the n-well resistance at a location away from the contact portion. As a result, it is considered that some parasitic operation has occurred and destroyed, and the ESD tolerance and surge noise tolerance are very small, and the required value when mounted on a power IC or the like cannot be satisfied. In particular, the ESD tolerance required for in-vehicle elements is as extremely large as 10 to 15 kV or more. In order to realize this required value, it has been studied to form a protective element such as a diode on the same substrate, but sufficient ESD tolerance has not been obtained in the experiments so far.

Further, as described above, when the RESURF structure is applied, the total amount of impurities per unit area of the offset region is the above-described RESURF condition regardless of the breakdown voltage. For example, when the thickness of the offset region is 0.5 μm, the impurity concentration of the offset region is 2 × 10 ¹⁶ cm ⁻³ , which is not suitable for obtaining a low on-resistance particularly in a relatively low breakdown voltage region.

Therefore, the present inventors, for example, in the case of an n-channel MOSFET, in addition to the normal current path from the n offset region to the n ⁺ source region through the inversion layer on the surface of the p well region, A semiconductor device provided with a second current path leading to the n ⁺ source region through the surface inversion layer has been filed earlier (Japanese Patent Application No. 2002-183402). According to this prior application, a semiconductor device with low on-resistance can be obtained while applying the RESURF structure.

  An object of the present invention is to provide a semiconductor device having one or both of a high ESD resistance and a low on-resistance while applying a RESURF structure in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the invention includes a second conductive semiconductor substrate, a first conductive semiconductor layer in contact with the second conductive semiconductor substrate, A second conductivity type semiconductor region formed in a surface layer of the first conductivity type semiconductor layer; a first conductivity type source region formed in the second conductivity type semiconductor region; the first conductivity type source region; A source electrode electrically connected to the second conductivity type semiconductor region, and formed on a surface layer of the second conductivity type semiconductor region away from the first conductivity type source region and in contact with the first conductivity type semiconductor layer A first conductivity type offset region; a first conductivity type drain region in contact with the first conductivity type offset region outside the second conductivity type semiconductor region; and a drain electrode electrically connected to the first conductivity type drain region. And before A gate insulating film formed on the surface of the second conductive type semiconductor region sandwiched between the first conductive type offset region and the first conductive type source region; a gate electrode formed on the gate insulating film; It is characterized by providing.

  According to a second aspect of the present invention, there is provided a semiconductor device according to a second conductive semiconductor substrate, a first conductive semiconductor layer in contact with the second conductive semiconductor substrate, and a surface layer of the first conductive semiconductor layer. Electrically connected to the formed second conductive type semiconductor region, the first conductive type source region formed in the second conductive type semiconductor region, the first conductive type source region and the second conductive type semiconductor region A first conductive type offset region formed in the second conductive type semiconductor region away from the first conductive type source region, and the first conductive type offset in the second conductive type semiconductor region A first conductivity type drain region in contact with the region and in contact with the first conductivity type semiconductor layer outside the second conductivity type semiconductor region; a drain electrode electrically connected to the first conductivity type drain region; First conductivity type A gate insulating film formed on a surface of the second conductive type semiconductor region sandwiched between the set region and the first conductive type source region, and a gate electrode formed on the gate insulating film. Features.

  According to the first or second aspect of the present invention, when ESD or a high surge voltage is applied to the drain electrode, the energy is generated by the parasitic pn diode including the second conductive type semiconductor substrate and the first conductive type semiconductor layer. Absorbed.

  According to a third aspect of the present invention, there is provided a semiconductor device including first and second second conductivity type semiconductor regions formed in a surface layer of a first conductivity type semiconductor layer, and the first second conductivity type semiconductor region. A first first conductivity type source region formed therein, a second first conductivity type source region formed in the second second conductivity type semiconductor region, and the first first conductivity type. A first source electrode electrically connected to the source region and the first second conductivity type semiconductor region, and an electrical connection to the second first conductivity type source region and the second second conductivity type semiconductor region A first source electrode connected to the first conductive type semiconductor layer and a first conductive type formed on a surface layer of the second conductive type semiconductor region away from the first first conductive type source region and in contact with the first conductive type semiconductor layer A first offset region and an outer side of the first second conductivity type semiconductor region. A first conductivity type drain region in contact with the conductivity type offset region; a drain electrode electrically connected to the first conductivity type drain region; the first conductivity type offset region; and the first first conductivity type source region. A first gate insulating film formed on a surface of the sandwiched first second conductivity type semiconductor region; a first gate electrode formed on the first gate insulating film; Formed on the surfaces of the first and second conductivity type semiconductor regions and the first conductivity type semiconductor layer sandwiched between the first conductivity type source region and the second first conductivity type source region. A second gate insulating film, and a second gate electrode formed on the second gate insulating film.

  According to a fourth aspect of the present invention, there is provided a semiconductor device including first and second second conductivity type semiconductor regions formed in a surface layer of a first conductivity type semiconductor layer, and the first second conductivity type semiconductor region. A first first conductivity type source region formed therein, a second first conductivity type source region formed in the second second conductivity type semiconductor region, and the first first conductivity type. A first source electrode electrically connected to the source region and the first second conductivity type semiconductor region, and an electrical connection to the second first conductivity type source region and the second second conductivity type semiconductor region A second source electrode connected to the first conductive type, a first conductive type offset region formed in the second conductive type semiconductor region away from the first first conductive type source region, and the first second conductive type A first conductive type offset region in the type semiconductor region and the second conductive type A first conductivity type drain region in contact with the first conductivity type semiconductor layer outside the type semiconductor region; a drain electrode electrically connected to the first conductivity type drain region; the first conductivity type offset region; A first gate insulating film formed on the surface of the first second conductive type semiconductor region sandwiched between the first first conductive type source regions, and a first gate insulating film formed on the first gate insulating film. 1 gate electrode, the first first conductivity type source region, the first and second second conductivity type semiconductor regions sandwiched between the second first conductivity type source region, and the first conductivity type. And a second gate insulating film formed on the surface of the semiconductor layer, and a second gate electrode formed on the second gate insulating film.

  According to the third or fourth aspect of the present invention, the first conductive type source region is normally reached from the first conductive type offset region through the inversion layer on the surface of the first second conductive type semiconductor region during the ON operation. In addition to the current path, a second current path from the first conductivity type semiconductor layer to the second first conductivity type source region through the inversion layer on the surface of the second second conductivity type semiconductor region is formed. Both the first conductivity type offset region and the first conductivity type semiconductor layer can be used as the drift region.

  According to a fifth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, the first conductive type semiconductor layer is formed in contact with a second conductive type semiconductor substrate. .

  According to a sixth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, the first conductive semiconductor layer is formed on a substrate via an insulating layer.

  According to these fifth and sixth aspects of the invention, since a plurality of semiconductor devices can be insulated for each element, a large number of semiconductor elements can be integrated.

  According to the semiconductor device of the present invention, the ESD or high surge voltage energy applied to the drain electrode is absorbed by the parasitic pn diode composed of the second conductive semiconductor substrate and the first conductive semiconductor layer. The ESD resistance and surge noise resistance can be improved. Also, according to the semiconductor device of the present invention, since both the first conductivity type offset region and the first conductivity type semiconductor layer can be used as the drift region, the current per unit area can be increased without increasing the on-voltage. There is an effect that the density can be increased.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, an n-channel MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type will be described. However, the first conductivity type is p-type and the second conductivity type is n-type. The same applies to the p-channel MOSFET.

(Embodiment 1)
FIG. 3 is a plan view showing the state of the semiconductor surface in the unit structure of the n-channel lateral MOSFET according to the first embodiment of the present invention. 1 and 2 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 3, respectively.

As shown in FIG. 3, on the semiconductor surface, one side of the n offset region 29 is a p-well region 23 to be a second conductivity type semiconductor region. On the semiconductor surface of the region surrounded by the p-well region 23, a part of the n-well region 22 which is the first conductivity type semiconductor layer, the first n ⁺ source region 24a, and the second n ⁺ source region 24b are formed. The first and second n ⁺ source regions 24a and 24b are exposed apart from each other so that the n-well region 22 is sandwiched between the first and second n ⁺ source regions 24a and 24b.

The semiconductor surface of the region surrounded by the first n ⁺ source region 24a is the first p ⁺ contact region 25a, and the semiconductor surface of the region surrounded by the second n ⁺ source region 24b is the second p ⁺ contact region 25b. p ⁺ contact region 25b. A first gate electrode 27a indicated by a two-dot chain line in FIG. 3 is provided on the p well region 23 between the n offset region 29 and the first and second n ⁺ source regions 24a and 24b.

In FIG. 3, second gate electrode 27b indicated by a two-dot chain line is arranged on n well region 22 and p well region 23 sandwiched between first n ⁺ source region 24a and second n ⁺ source region 24b. Is done. The first gate electrode 27a and the second gate electrode 27b may be integrated as illustrated, or may be provided separately and connected to the same potential.

The first source electrode 30a is disposed on the first n ⁺ source region 24a and the first p ⁺ contact region 25a. Second source electrode 30b is arranged on second n ⁺ source region 24b and second p ⁺ contact region 25b. The first and second source electrodes 30a and 30b are connected to the same potential. On the opposite side of the p well region 23 across the n offset region 29 is an n ⁺ drain region 28 on which the drain electrode 31 is disposed.

The cross-sectional configuration in FIG. 3A-A ′ will be described with reference to FIG. This cross-sectional configuration is almost the same as the conventional configuration shown in FIG. 8, but differs from the configuration shown in FIG. 8 in that p-well region 23 does not extend below n ⁺ drain region 28. That is, the n offset region 29 extending from the p well region 23 is immediately below the n ⁺ drain region 28, and the portion of the n offset region 29 immediately below the n ⁺ drain region 28 is in direct contact with the n well region 22. .

That is, as shown in FIG. 1, an n-well region 22 is formed in the surface layer of the p-type semiconductor substrate 21, and a p-well region 23 is formed in the surface layer of the n-well region 22. The second n ⁺ source region 24 b and the second p ⁺ contact region 25 b are selectively formed in the surface layer of the p well region 23. Second source electrode 30b is in common contact with second n ⁺ source region 24b and second p ⁺ contact region 25b. The n ⁺ drain region 28 is formed outside the p well region 23, and the drain electrode 31 is provided on the surface thereof.

The drain electrode 31 is normally connected to the same potential as the n-well electrode 34 in contact with the surface of the n-well region 22. The n offset region 29 extends along the surface layer of the p well region 23 between the n ⁺ drain region 28 and the second n ⁺ source region 24 b and extends from the p well region 23 to form the n ⁺ drain region 28. It is formed to include.

A first gate electrode 27a is formed on the surface of the p well region 23 sandwiched between the n offset region 29 and the second n ⁺ source region 24b via a first gate oxide film 26a. Further, a LOCOS oxide film 32 for electric field relaxation is formed between the drain side end of the first gate electrode 27 a and the n ⁺ drain region 28. On the back surface of the p-type semiconductor substrate 21, a back electrode 33 that is normally connected to the same potential as the second source electrode 30b is formed. The cross-sectional configuration of FIG. 1 described above is the same in a cross-section passing through the first n ⁺ source region 24a, the first p ⁺ contact region 25a, and the first source electrode 30a and parallel to AA ′.

With the above configuration, as shown in FIG. 1, an n region comprising an n ⁺ drain region 28, an n offset region 29 and an n well region 22 immediately below the drain electrode 31, and a p region comprising the p-type semiconductor substrate 21. Is formed as a parasitic pn diode. Therefore, when a high ESD voltage is applied to the drain electrode 31, a reverse bias is applied to the parasitic pn diode, and a breakdown current flows between the drain electrode 31 and the back electrode 33. As a result, the high voltage energy of ESD can be absorbed, and the ESD tolerance is increased.

The cross-sectional configuration in FIG. 3B-B ′ will be described with reference to FIG. As shown in FIG. 2, in the BB ′ cross section, an n well region 22 is formed in the surface layer of the p-type semiconductor substrate 21, and a p well region 23 is separately formed in the surface layer of the n well region 22. Yes. For convenience, the p-well region 23 including the first n ⁺ source region 24a is distinguished as the first p-well region 23a, and the p-well region 23 including the second n ⁺ source region 24b is distinguished as the second p-well region 23b. To do.

The second gate electrode 27b includes a first p well region 23a, an n well region 22 and a second p well region 23b sandwiched between the first n ⁺ source region 24a and the second n ⁺ source region 24b. Is provided via a second gate oxide film 26b. The first n ⁺ source region 24a and the first p ⁺ contact region 25a are selectively formed in the surface layer of the first p well region 23a. The first source electrode 30a is in common contact with the first n ⁺ source region 24a and the first p ⁺ contact region 25a. The second n ⁺ source region 24b, the second p ⁺ contact region 25b, and the second source electrode 30b are as described with reference to FIG.

  In the MOSFET configured as described above, when a positive voltage is applied to the drain electrode 31 with respect to the source electrodes 30a and 30b, and a voltage lower than the gate threshold is applied to the gate electrodes 27a and 27b, the p-well region Since the pn junction between the N and the n offset region 29 is reverse-biased, no current flows. When a voltage equal to or higher than the gate threshold is applied to the gate electrodes 27a and 27b, an inversion layer is formed on the surfaces of the p-well regions 23a and 23b immediately below the gate electrodes 27a and 27b.

Accordingly, the n ⁺ source region 24a, 24b is usually reached from the n ⁺ drain region 28 through the n offset region 29 and the surface inversion layers of the p well regions 23a, 23b below the first gate electrode 27a in this order. Current flows through the path. Separately from this normal path, the n ⁺ drain region 28 passes through the n offset region 29 to reach the n well region 22 and flows in the n well region 22 toward the n ⁺ source regions 24a and 24b, and the second gate. A current also flows through the path leading to the n ⁺ source regions 24a and 24b via the surface inversion layers of the p well regions 23a and 23b immediately below the electrode 27b. Therefore, since the amount of current during the on operation increases without increasing the pitch of the elements, the amount of current per unit area can be increased.

When the RESURF conditions are followed, the total amount of impurities per unit area of the n offset region 29 is about 1 × 10 ¹² cm ⁻² , and thus, for example, the impurity concentration of the n offset region 29 having a depth, that is, a thickness of 0.5 μm. Is about 2 × 10 ¹⁶ cm ⁻³ . When the double resurf condition is followed, the total amount of impurities per unit area of the p well regions 23a and 23b is about 2 × 10 ¹² cm ⁻² , so that the depth of the p well regions 23a and 23b is 1.5 μm, for example. Then, the thickness is 1 μm, and therefore the impurity concentration is about 2 × 10 ¹⁶ cm ⁻³ . Further, since the total amount of impurities per unit area of the n-well region 22 is about 2 × 10 ¹² cm ⁻² , for example, when the depth is 6.0 μm, the thickness is 4.5 μm, and the impurity concentration is about 4.4 × 10 ¹⁵ cm ⁻³ .

FIG. 4 is a diagram illustrating another example of the cross-sectional configuration in FIG. 3A-A ′. As shown in FIG. 4, n offset region 29 becomes terminated with n ⁺ drain region 28, since there is no n offset region 29 immediately below the n ⁺ drain region 28, n ⁺ drain region 28 is in contact with the n-well region 22 constituting It is good.

(Embodiment 2)
In the second embodiment, only a normal current path passing through the n offset region 29 is provided without providing a current path passing through the n well region 22. That is, in the second embodiment, the source side configuration as shown in FIG. 3 is not provided. Therefore, when there is no need to increase the amount of current per unit area, there is an advantage that the configuration on the source side is simplified compared to the first embodiment.

FIG. 5 is a cross-sectional view showing a configuration example of the unit structure of the n-channel lateral MOSFET according to the second embodiment, which is approximately the same as the configuration of FIG. FIG. 6 is a diagram showing another cross-sectional configuration of the second embodiment, which is approximately the same as the configuration of FIG. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. In the second embodiment, n ⁺ source region 24c and p ⁺ contact region 25c are formed in stripes parallel to n ⁺ drain region 28.

n offset region 29, n ⁺ drain region 28 and the n ⁺ source along the surface layer of the p-well region 23 between the regions 24c, n ⁺ drain region 28 extends from within the p-well region 23 in the example shown in FIG. 5 It is formed so that it may contain. In contrast, in the example shown in FIG. 6, the n offset region 29 terminates at the n ⁺ drain region 28.

Gate electrode 27c is formed on the surface of p well region 23 sandwiched between n offset region 29 and n ⁺ source region 24c via gate oxide film 26c. The LOCOS oxide film 32 is formed between the drain side end of the gate electrode 27 c and the n ⁺ drain region 28. The back electrode 33 is normally connected to the same potential as the source electrode 30c.

(Dependence of ESD resistance on active area)
FIG. 7 is a characteristic diagram showing the active area dependence of the ESD tolerance of the lateral MOSFET according to the above-described embodiment. In FIG. 7, the embodiment is a MOSFET configured as shown in FIG. 5, and the conventional example is a MOSFET configured as shown in FIG. The active area dependency of the ESD tolerance of the MOSFETs configured in FIGS. 1 to 3, the MOSFET configured in FIG. 4 and the MOSFET configured in FIG. 6 is the same as the characteristics of the MOSFET configured in FIG.

As shown in FIG. 7, the ESD tolerance of the MOSFET of the example is high. Further, since the larger energy can be absorbed when the active area becomes larger, the ESD tolerance becomes higher as the active area increases. For example, the ESD resistance when the active area is 0.5 mm ² , 1.0 mm ² and 1.5 mm ² is about 4 kV, about 7 kV and about 12 kV, respectively. On the other hand, the ESD tolerance of the conventional example is extremely low regardless of the active area, and is about several hundred volts.

  As described above, according to the lateral MOSFET of the embodiment, when ESD or a high surge voltage is applied to the drain electrode 31, the energy is a parasitic pn composed of the p-type semiconductor substrate 21 and the n-well region 22. Since it is absorbed by the diode, it is possible to improve the ESD tolerance and surge noise tolerance. Further, since both the n offset region 29 and the n well region 22 can be used as the drift region, the current density per unit area can be increased without increasing the on-voltage, and so-called on-resistance Ron · A A low lateral MOSFET.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the back electrode 33 is not provided, and a location where the n-well region 22 is not formed is provided, the p-type semiconductor substrate 21 is exposed to the semiconductor surface at that location, contacts are made, and the source electrodes 30a, 30b, 30c It is good also as a structure electrically connected. If it is sufficient to increase the current density per unit area, a so-called SOI (silicon-on-insulator) in which an n-well region 22 is provided on a support substrate made of a semiconductor or the like via an insulating layer. A substrate may be used.

  As described above, the semiconductor device according to the present invention is useful for a power MOSFET having a high ESD tolerance and a low on-resistance. In particular, an on-vehicle switching device in which a plurality of high-side MOSFETs and low-side MOSFETs are integrated in the same chip. Suitable for power MOSFETs used as

FIG. 3 is a cross-sectional view showing an example of a unit structure in FIG. 3A-A ′ of the lateral MOSFET according to the first exemplary embodiment of the present invention; It is sectional drawing which shows an example of the unit structure in FIG. 3B-B 'of the horizontal MOSFET concerning Embodiment 1 of this invention. It is a top view which shows an example of the state of the semiconductor surface in the unit structure of the horizontal MOSFET concerning Embodiment 1 of this invention. It is sectional drawing which shows another example of the unit structure in FIG. 3A-A 'of horizontal MOSFET concerning Embodiment 1 of this invention. It is sectional drawing which shows an example of the unit structure of the horizontal MOSFET concerning Embodiment 2 of this invention. It is sectional drawing which shows another example of the unit structure of the horizontal MOSFET concerning Embodiment 2 of this invention. It is a characteristic view which shows the relationship between the active area and ESD tolerance of the lateral MOSFET concerning embodiment of this invention. It is sectional drawing which shows the structure of the conventional horizontal MOSFET.

Explanation of symbols

21 Second conductivity type semiconductor substrate (p-type semiconductor substrate)
22 First conductivity type semiconductor layer (n-well region)
23, 23a, 23b Second conductivity type semiconductor region (p-well region)
24a, 24b, 24c First conductivity type source region 26a, 26b, 26c Gate insulating film (gate oxide film)
27a, 27b, 27c Gate electrode 28 First conductivity type drain region (n ⁺ drain region)
29 First conductivity type offset region (n offset region)
30a, 30b Source electrode 31 Drain electrode

Claims (6)

A second conductivity type semiconductor substrate;
A first conductive semiconductor layer in contact with the second conductive semiconductor substrate;
A second conductivity type semiconductor region formed in a surface layer of the first conductivity type semiconductor layer;
A first conductivity type source region formed in the second conductivity type semiconductor region;
A source electrode electrically connected to the first conductive type source region and the second conductive type semiconductor region;
A first conductivity type offset region formed on a surface layer of the second conductivity type semiconductor region away from the first conductivity type source region and in contact with the first conductivity type semiconductor layer;
A first conductivity type drain region in contact with the first conductivity type offset region outside the second conductivity type semiconductor region;
A drain electrode electrically connected to the first conductivity type drain region;
A gate insulating film formed on a surface of the second conductivity type semiconductor region sandwiched between the first conductivity type offset region and the first conductivity type source region;
A gate electrode formed on the gate insulating film;
A semiconductor device comprising: A second conductivity type semiconductor substrate;
A first conductive semiconductor layer in contact with the second conductive semiconductor substrate;
A second conductivity type semiconductor region formed in a surface layer of the first conductivity type semiconductor layer;
A first conductivity type source region formed in the second conductivity type semiconductor region;
A source electrode electrically connected to the first conductive type source region and the second conductive type semiconductor region;
A first conductivity type offset region formed in the second conductivity type semiconductor region away from the first conductivity type source region;
A first conductivity type drain region in contact with the first conductivity type offset region in the second conductivity type semiconductor region and in contact with the first conductivity type semiconductor layer outside the second conductivity type semiconductor region;
A drain electrode electrically connected to the first conductivity type drain region;
A gate insulating film formed on a surface of the second conductivity type semiconductor region sandwiched between the first conductivity type offset region and the first conductivity type source region;
A gate electrode formed on the gate insulating film;
A semiconductor device comprising: A first second conductivity type semiconductor region formed in a surface layer of the first conductivity type semiconductor layer;
A first first conductivity type source region formed in the second conductivity type semiconductor region;
A second second conductivity type semiconductor region formed in the first conductivity type semiconductor layer;
A second first conductivity type source region formed in the second second conductivity type semiconductor region;
A first source electrode electrically connected to the first first conductivity type source region and the first second conductivity type semiconductor region;
A second source electrode electrically connected to the second first conductivity type source region and the second second conductivity type semiconductor region;
A first conductivity type offset region formed on a surface layer of the first second conductivity type semiconductor region away from the first first conductivity type source region and in contact with the first conductivity type semiconductor layer;
A first conductivity type drain region in contact with the first conductivity type offset region outside the first second conductivity type semiconductor region;
A drain electrode electrically connected to the first conductivity type drain region;
A first gate insulating film formed on a surface of the first second conductivity type semiconductor region sandwiched between the first conductivity type offset region and the first first conductivity type source region;
A first gate electrode formed on the first gate insulating film;
On the surfaces of the first and second conductivity type semiconductor regions and the first conductivity type semiconductor layer sandwiched between the first first conductivity type source region and the second first conductivity type source region. A formed second gate insulating film;
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising: A first second conductivity type semiconductor region formed in a surface layer of the first conductivity type semiconductor layer;
A first first conductivity type source region formed in the second conductivity type semiconductor region;
A second second conductivity type semiconductor region formed in the first conductivity type semiconductor layer;
A second first conductivity type source region formed in the second second conductivity type semiconductor region;
A first source electrode electrically connected to the first first conductivity type source region and the first second conductivity type semiconductor region;
A second source electrode electrically connected to the second first conductivity type source region and the second second conductivity type semiconductor region;
A first conductivity type offset region formed in the first second conductivity type semiconductor region away from the first first conductivity type source region;
A first conductivity type drain region in contact with the first conductivity type offset region in the first second conductivity type semiconductor region and in contact with the first conductivity type semiconductor layer outside the second conductivity type semiconductor region;
A drain electrode electrically connected to the first conductivity type drain region;
A first gate insulating film formed on a surface of the first second conductivity type semiconductor region sandwiched between the first conductivity type offset region and the first first conductivity type source region;
A first gate electrode formed on the first gate insulating film;
On the surfaces of the first and second conductivity type semiconductor regions and the first conductivity type semiconductor layer sandwiched between the first first conductivity type source region and the second first conductivity type source region. A formed second gate insulating film;
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising:   5. The semiconductor device according to claim 3, wherein the first conductive type semiconductor layer is formed in contact with a second conductive type semiconductor substrate. 5. The semiconductor device according to claim 3, wherein the first conductivity type semiconductor layer is formed on a substrate via an insulating layer. 6.

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