JP2004335778A - Semiconductor device - Google Patents

Abstract

A chip can be formed so as to have a small chip area while reducing the resistance of a gate electrode, thereby reducing gate-drain parasitic capacitance.
A plurality of gate electrodes are formed in parallel on a semiconductor region via a gate insulating film, and a plurality of gate electrodes are formed in a surface region of the semiconductor region in parallel with a longitudinal direction of the gate electrode. A drain region and a source region, a first drain line and a source line 17 formed on the drain region and the source region, and formed in a direction perpendicular to a longitudinal direction of the gate electrode 11. A gate wiring 12 connected via a gate contact 13 provided on the gate electrode 11 and a drain formed in a direction perpendicular to the longitudinal direction of the gate electrode 11 and provided on the first drain wiring; This is a semiconductor device including a second drain wiring 15 connected via a contact 16.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a high-power semiconductor device for high frequency use, and more particularly to a semiconductor device having a plurality of field effect transistors.
[0002]
[Prior art]
As a conventional high-power semiconductor device for high-frequency applications, for example, in a field-effect transistor, a large number of field-effect transistors having relatively small gate widths are connected in parallel to operate at high efficiency. Field effect transistor can be obtained.
[0003]
FIG. 3 shows a plan view of a conventional high-power field effect transistor for high frequency use. Here, a MOSFET of a field effect transistor will be described as an example.
[0004]
As shown in FIG. 3, a plurality of gate electrodes 51 are formed. On the gate electrode 51, a plurality of gate electrodes 51 are connected in parallel, and a gate wiring 52 patterned so that two adjacent electrodes form a pair is formed. The gate wiring 52 has a comb shape together with the plurality of gate electrodes 51. Further, a plurality of drain regions are connected in parallel, and a comb-shaped drain wiring 53 provided between two paired gate electrodes 51 and a source region formed between the paired gate electrodes 51. The source wiring 54 is formed thereon. The gate electrode 51 and the gate wiring 52 are electrically connected via a gate contact 55.
[0005]
The plurality of field effect transistors are arranged in a direction (y direction) perpendicular to a longitudinal direction (x direction) in which the gate electrode 51 is formed, and the gate wiring 52 and the drain wiring 53 are parallel to the x direction. , And each is pulled out in the opposite direction. Since the resistance of the gate electrode affects the high-frequency characteristics, the gate pads 56 and the drain pads 57 are alternately arranged in the longitudinal direction so that the length of each comb becomes short ( See Patent Document 1.).
[0006]
FIG. 4 is a plan view of another conventional high-power field-effect transistor for high-frequency use. Here, a MOSFET will be described as an example of the field-effect transistor. A plurality of gate electrodes 61 are formed side by side, and a gate wiring 62 formed by connecting the plurality of gate electrodes 61 in parallel is formed on the gate electrodes 61. The gate wiring 62 has a comb-like shape together with the plurality of gate electrodes 61, and a plurality of wirings are also formed in a direction (y direction) perpendicular to a longitudinal direction (x direction) of the gate electrode 61. .
[0007]
The gate electrode 61 and the gate wiring 62 provided above the gate electrode 61 are provided at the intersection of the first gate contact 63 provided at the end of the gate electrode 61 and the gate electrode 61 and the gate wiring 62. It is electrically connected via the second gate contact 64 provided. Since the resistance of the gate electrode affects the high-frequency characteristics, the second gate contact 64 is provided so that the actual comb length is shortened, and a plurality of gate contacts are formed on one comb. .
[0008]
A lower first drain wiring (not shown) is formed on the drain region formed between the paired gate electrodes 61 in parallel with the x direction. On a source region formed between the pair of gate electrodes 61, a source wiring 66 is formed. A second drain wiring 67 having a comb shape is formed on the first drain wiring so as to connect a plurality of drain regions in parallel. The second drain wiring 67 is formed so as to cross over the gate wiring 62 formed in the y direction via an interlayer insulating film.
[0009]
The plurality of field effect transistors are arranged in the y direction, and the gate wiring 62 and the second drain wiring 67 are drawn in parallel to the x direction and in the opposite directions. The gate pad 68 and the drain pad 69 are arranged at their ends.
[0010]
FIGS. 5A and 5B are cross-sectional views of main parts of the semiconductor device shown in FIG. 4 along BB and CC. A P ⁻ -type first semiconductor region 72 such as an epitaxial growth layer is formed on a P ⁺ -type semiconductor substrate 71, and a gate electrode 61 is formed on the first semiconductor region 72 via a gate insulating film 76. ing. In the surface region, an N ⁺ type drain region 73, an N ⁺ type source region 74, and a P ⁺ type second semiconductor region 75 are formed. On N ⁺ -type drain region 73 are formed first drain wiring 65 and the second drain line 67, on the N ⁺ -type source region 74 and the second semiconductor region 75 of the source wiring 66 is formed ing. The second drain wiring 67 intersects the gate wiring 62 formed in the direction (y direction) perpendicular to the longitudinal direction (x direction) of the gate electrode 61 via the interlayer insulating film 81. Is formed.
[0011]
[Patent Document 1]
JP-A-2002-110988 (FIG. 5)
[0012]
[Problems to be solved by the invention]
In the semiconductor device shown in FIG. 3, since the resistance of the gate electrode affects high-frequency characteristics, the gate pads 56 and the drain pads 57 are alternately formed so that the length of the comb is shortened. With such a configuration, there is a problem that an unnecessary empty area is formed around the pad, and the chip area is increased.
[0013]
Further, in the semiconductor device shown in FIG. 4, since the resistance of the gate electrode affects the high-frequency characteristics, one comb is used so that the substantial comb length of the long comb electrode 61 is reduced. A plurality of gate contacts are provided. However, in such a configuration, when the drain wiring is drawn to the pad, the second drain wiring 67 crosses over the gate wiring 62 provided above the gate electrode 61 and is drawn perpendicularly to the gate wiring. Therefore, there is a problem that the gate-drain parasitic capacitance at the intersection of the gate wiring and the drain wiring increases. When the parasitic capacitance between the gate and the drain increases, an output signal is fed back, which causes a problem that a gain cannot be extracted and oscillation occurs.
[0014]
The present invention has been made to solve the above problems, and can be formed so as to reduce the chip area while reducing the resistance of the gate electrode, and to reduce the gate-drain parasitic capacitance. It is an object to provide a possible semiconductor device.
[0015]
[Means for Solving the Problems]
One embodiment of the semiconductor device of the present invention for achieving the above object includes a semiconductor region formed over a substrate,
On the semiconductor region, a gate electrode formed through a gate insulating film, a plurality of gate electrodes formed in parallel,
In the surface region of the semiconductor region, in parallel to the longitudinal direction of the gate electrode, a plurality of formed drain region and source region,
A first drain wiring formed on the drain region;
Source wiring formed on the source region;
A gate wiring formed in a direction perpendicular to the longitudinal direction of the gate electrode and connected via a gate contact provided on the gate electrode;
A second drain wiring formed in a direction perpendicular to the longitudinal direction of the gate electrode and connected via a drain contact provided on the first drain wiring;
It is characterized by having.
[0016]
According to one embodiment of the present invention described above, the gate electrode can be formed to have a small chip area while reducing the resistance of the gate electrode, and the parasitic capacitance between the gate and the drain can be reduced.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First Embodiment)
1 and 2 show a semiconductor device according to a first embodiment of the present invention.
First, FIG. 1 shows a plan view of a high-power field-effect transistor for high frequency use according to the present embodiment. FIG. 1A shows an enlarged view of a main part, and FIG. 1B shows a schematic view. Here, a MOSFET of a field effect transistor will be described as an example, but the present invention is not particularly limited to this, and a J-FET, MESFET, or the like may be used. A plurality of gate electrodes 11 are formed, and a gate wiring 12 in which the plurality of gate electrodes 11 are connected in parallel is formed on the gate electrodes 11. As shown in FIG. 1B, the gate wiring 12 has a plurality of wirings formed in the longitudinal direction (x direction) and the vertical direction (y direction) of the gate electrode 11 and has a comb-like shape. I have.
[0018]
The gate electrode 11 and the gate wiring 12 are electrically connected via a gate contact 13 provided at the intersection of the gate electrode 11 and the gate wiring 12. Since the resistance of the gate electrode affects the high-frequency characteristics, the gate contact 13 is provided so that the actual comb length is shortened, and a plurality of gate contacts are formed on one comb.
[0019]
A lower first drain wiring 14 is formed on the drain region formed between the paired gate electrodes 11 in parallel with the gate electrode 11. A source line 17 is formed on the source region and the gate electrode 11 formed between the pair of gate electrodes 11.
[0020]
Further, on the first drain wiring 14 and the source wiring 17, an upper-layer second drain wiring 15 is formed in parallel with the gate wiring 12. That is, the second drain wiring 15 is formed above the gate electrode 11, and the source wiring 17 is provided between the gate electrode 11 and the second drain wiring 15. The first drain wiring 14 and the second drain wiring 15 are electrically connected via a drain contact 16 provided at the intersection of the first drain wiring 14 and the second drain wiring 15. .
[0021]
The plurality of field effect transistors are arranged in the y direction, and the gate wiring 12 and the two-layer drain wiring 15 are led out in the y direction in opposite directions. The gate pad 18 and the drain pad 19 are arranged at the ends.
[0022]
FIG. 2 is a cross-sectional view of a main part taken along line AA of the semiconductor device of FIG. On a relatively high-concentration P ⁺ -type semiconductor substrate 21, a P ⁻ -type first semiconductor region 22 formed by epitaxial growth is formed. An N ⁺ -type drain region 23 and an N ⁺ -type source region 24 are formed in a surface region of the first semiconductor region 22. The N ⁺ -type source region 24 has a relatively high concentration of a P ⁺ -type second region. In contact with the second semiconductor region 25.
[0023]
The gate electrode 11 is formed between the source region 24 and the drain region 23 via a gate insulating film 26. On the drain region 23, a lower first drain wiring 14 is formed. Further, the source wiring 17 is formed on the source region 24 and the second semiconductor region 25. The field effect transistor described in this embodiment has a configuration in which a source electrode is taken out from the back surface, and the source region 24 and the second semiconductor region 25 are short-circuited so that a parasitic diode is not formed. The end of the source wiring 17 is formed on the gate electrode 11 via an interlayer insulating film 31. The source wiring is supplied with a fixed potential, and is grounded here.
[0024]
On the first drain wiring 14, a second drain wiring 15 in an upper layer is formed in a direction perpendicular to the first drain wiring 14, and the first drain wiring 14 and the second drain wiring 15 They are electrically connected via drain contacts 32 of through holes. The second drain wiring 15 is formed on the source wiring 17 via an interlayer insulating film 31. Therefore, between the gate electrode 11 and the second drain wiring 15, the source wiring 17 to which the fixed potential (ground potential in this case) is supplied exists via the interlayer insulating film 31, and the shielding effect works. , And the parasitic capacitance can be further reduced. Further, the example in which the second semiconductor region 25 short-circuited to the source region 24 is formed has been described, but the present invention is not particularly limited to this.
[0025]
According to the present embodiment, the gate wiring 12 and the second drain wiring 15 are formed in parallel, and when the second drain wiring 15 is drawn out to the pad, the gate wiring 12 and the second drain wiring 15 are formed. Since they do not intersect, the parasitic capacitance between the gate and the drain can be reduced. Since the resistance of the gate electrode affects the high-frequency characteristics, a single comb is provided with a plurality of gate contacts so that the substantial comb length of the long comb electrode is reduced. Therefore, it is possible to reduce the chip area while reducing the resistance of the gate electrode, and to reduce the gate-drain parasitic capacitance.
[0026]
In addition, in the related art shown in FIGS. 3 and 4, as shown in FIG. 5, the drain-source parasitic capacitance formed by the drain region 73 and the semiconductor region below the drain region 73 is reduced. When the width of the region 73 is reduced, the drain region and the drain wiring are formed in parallel, so that the width of the drain wiring also needs to be reduced. Since the drain wiring of a high-power field-effect transistor originally has a large amount of current, if the width of the drain wiring is reduced, the current density increases and electromigration occurs.
[0027]
On the other hand, in the present embodiment, in order to reduce the drain-source parasitic capacitance formed by the drain region 23 and the semiconductor region below the drain region 23, even if the width of the drain region 23 is reduced, Since the drain wiring is formed vertically, it is not necessary to form the drain wiring narrow. Therefore, even if the width of the drain region is reduced to reduce the drain-source parasitic capacitance, the current density increases and electromigration does not occur.
[0028]
【The invention's effect】
As described in detail above, according to the present invention, the chip area can be reduced while the resistance of the gate electrode is reduced, and the parasitic capacitance between the gate and the drain can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a principal part along AA of FIG. 1 showing the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a plan view showing a conventional semiconductor device.
FIG. 4 is a plan view showing another conventional semiconductor device.
5 is a cross-sectional view of a principal part of another conventional semiconductor device taken along line BB and CC in FIG. 4;
[Explanation of symbols]
11, 51, 61 Gate electrode 12, 52, 62 Gate wiring 13, 55 Gate contact 14, 65 First drain wiring 15, 67 Second drain wiring 16 Drain contact 17, 54, 66 Source wiring 18, 56, 68 Gate pads 19, 57, 69 Drain pads 21, 71 P ⁺ -type semiconductor substrate 22, 72 P ⁻ -type first semiconductor region 23, 73 N ⁺ -type drain region 24, 74 N ⁺ -type source region 25, 75 P ⁺ -type second semiconductor regions 26 and 76 Gate insulating films 31 and 81 Interlayer insulating film 53 Drain wiring 63 First gate contact 64 Second gate contact

Claims (8)

A semiconductor region formed on the substrate,
On the semiconductor region, a gate electrode formed through a gate insulating film, a plurality of gate electrodes formed in parallel,
In the surface region of the semiconductor region, in parallel to the longitudinal direction of the gate electrode, a plurality of formed drain region and source region,
A first drain wiring formed on the drain region;
Source wiring formed on the source region;
A gate wiring formed in a direction perpendicular to the longitudinal direction of the gate electrode and connected via a gate contact provided on the gate electrode;
A second drain wiring formed in a direction perpendicular to the longitudinal direction of the gate electrode and connected via a drain contact provided on the first drain wiring;
A semiconductor device comprising: The gate wiring and the second drain wiring are drawn out in opposite directions in a direction perpendicular to the longitudinal direction of the gate electrode, and a gate pad and a drain pad are provided at ends. 3. The semiconductor device according to 2. 3. The semiconductor according to claim 1, wherein the gate electrode is connected in parallel by the gate wiring, and the drain region is connected in parallel by the second drain wiring. 4. apparatus. 4. The semiconductor device according to claim 1, wherein the source wiring has an end portion formed to extend above the gate electrode. 5. 5. The semiconductor device according to claim 4, wherein the source wiring is supplied with a fixed potential. The semiconductor device according to claim 5, wherein the fixed potential is a ground potential. The semiconductor device further includes a second semiconductor region formed in contact with the substrate and the source region in the semiconductor region, and the source wiring is formed to short-circuit the source region and the second semiconductor region. The semiconductor device according to claim 4, wherein: A plurality of the field effect transistors having the gate electrode, the drain region and the source region are arranged in a direction perpendicular to a longitudinal direction of the gate electrode, and the drain region and the source region are adjacent to each other. The semiconductor device according to claim 1, wherein the semiconductor device is shared between the field effect transistors.

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