JP2004334794A - Microcomputer with built-in pll - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer with a built-in PLL, having a simple structure and a small exclusive circuit area, being capable of stopping input of a clock signal from an external oscillation circuit when detecting stop of the external oscillation circuit. <P>SOLUTION: The microcomputer is equipped with an edge detection circuit 20, a PLL circuit 10, a counter 30, a detection part 50 of an external generation clock signal stop and a circuit of the external generation clock signal stop for stopping input of the external generation clock signal to the edge detection circuit 20 and a PLL circuit 10 while the external clock stop detection signal is output. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microcomputer with a built-in PLL that is connected to the outside of a microcomputer and that does not receive oscillation from the external oscillation circuit when detecting that oscillation of an external oscillation circuit serving as a clock source of the microcomputer has stopped. Things.
[0002]
[Prior art]
In microcomputer systems used for machines related to human life such as automobiles, the concept of fail-safe as well as high reliability is important. Fail safe is to detect when a part of the system becomes abnormal and to switch to an appropriate auxiliary means. As one of such abnormal situations, there is an oscillation stop of an external oscillation circuit of a microcomputer (hereinafter referred to as a microcomputer). The oscillation stop of the external oscillation circuit occurs, for example, when the external oscillation circuit is opened or short-circuited.
[0003]
The microcomputer detects when such external oscillation circuit oscillation stops and switches the internal clock from the connection terminal side of the external oscillation circuit to the internal oscillation circuit such as the internal ring oscillator. Have been.
[0004]
This oscillation stop detection circuit is built in the microcomputer chip. The oscillation stop detection circuit detects the edge of the externally generated clock signal input from the connection terminal of the external oscillation circuit, and charges and discharges in response to this detection. A clock edge detection circuit for generating a control pulse signal is provided.
[0005]
The oscillation stop detection circuit includes an operation of gradually charging a charging circuit having an RC time constant, and a charging / discharging circuit for performing a discharging operation by a charging / discharging control pulse signal. When the externally generated clock signal oscillates normally, discharging by the charge / discharge control pulse signal is periodically performed before charging is completed. However, when the externally generated clock signal stops, the charge / discharge control pulse signal is not generated, so that the discharge is not performed in the charge / discharge circuit, and the charging is completed. The charge / discharge circuit detects the completion of the charging as the oscillation stop of the external oscillation circuit, and generates an oscillation stop interrupt or the like in response to the detection.
[0006]
Furthermore, the switching unit switches the main clock of the microcomputer from the externally generated clock signal to the oscillation signal of the internal ring oscillator by the oscillation stop interrupt signal, thereby enabling the microcomputer to operate even after the externally generated clock signal is stopped. I have. This makes it possible to execute necessary fail-safe processing.
[0007]
The charge / discharge circuit used in this conventional oscillation stop detection circuit is composed of a resistor R and a capacitor C. In particular, the capacitor C occupies a large area in layout, which hinders a reduction in chip area. . Further, an extra ring oscillator circuit as an internally generated clock oscillation source, which is used only when the oscillation stop is detected, is required. In addition, since the time constant due to RC greatly changes due to fluctuations in the semiconductor manufacturing process and operating conditions, it is necessary to tune the design with extreme care in order to detect an accurate oscillation stop. , Which can easily cause design errors.
[0008]
The abnormal oscillation detection circuit described in Patent Document 1 includes a reference oscillation circuit section, a counter, a storage circuit section, and a comparison circuit section, and detects an abnormality in the oscillation frequency of the system clock whose oscillation frequency has been changed. I have.
[0009]
In this abnormal oscillation detection circuit, a reference oscillation circuit section generates and outputs a reference clock having an oscillation frequency set in advance. The counter counts the reference clock signal output from the reference oscillation circuit unit, outputs the count value at each time, inputs the system clock signal, and clears the count value based on the system clock signal. .
[0010]
Further, a prescribed value corresponding to the oscillation frequency of the reference clock signal is preset in the storage circuit unit, and the comparison circuit unit compares the count value output from the counter with the prescribed value stored in the storage circuit unit. And outputs a detection signal based on the comparison result. Then, the abnormality of the oscillation frequency is detected by the detection signal.
[0011]
[Patent Document 1]
JP-A-8-76877 (pages 1, 3, 7)
[0012]
[Problems to be solved by the invention]
As described above, in the former conventional technique, there is a problem that the time constant due to RC varies greatly depending on the semiconductor manufacturing process and use conditions. In addition, there is a problem that the layout area increases because a large CR time constant is required and a dedicated internally generated clock generation source must be built in.
[0013]
Further, according to the latter conventional technique, the circuit configuration for detecting an abnormality in the oscillation frequency becomes large, the occupied circuit area increases, and it becomes difficult to reduce the area of the chip. Furthermore, there is no disclosure of a method of stopping oscillation of a clock whose oscillation frequency has been changed after detecting an abnormality in the oscillation frequency.
[0014]
The present invention has been made in view of the above, and has a simple configuration and a small occupied circuit area, and when a stop of an external oscillation circuit is detected, stopping the input of an (externally generated) clock signal from the external oscillation circuit. It is an object of the present invention to obtain a microcomputer with a built-in PLL capable of performing the following.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object, in a microcomputer with a built-in PLL according to the present invention, an edge detection circuit for detecting an edge of an input externally generated clock signal; A PLL circuit for synchronizing a signal with a clock signal that outputs the signal by itself and multiplying the phase-synchronized signal by n to output the signal as an internal clock signal used inside the microcomputer; A counter that performs a count operation using an internal clock signal output from a PLL circuit as a count source; and, when the output of the counter exceeds a predetermined set value, detects this as a stop of the externally generated clock signal. An externally generated clock signal stop detector that keeps outputting signals, and an external clock To between the externally generated clock stop circuit for stopping the input of the externally generated clock signal to the edge detection circuit and the PLL circuit, comprising: a the stop detection signal is outputted.
[0016]
According to the present invention, the input of the externally generated clock signal XIN from the external oscillation circuit to the microcomputer can be stopped when the stop of the external oscillation circuit is detected with a simple configuration and a small dedicated circuit area.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a microcomputer with a built-in PLL according to the present invention will be described in detail with reference to the accompanying drawings. The invention is not limited by the embodiment.
[0018]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of the oscillation stop detection circuit in the microcomputer with a built-in PLL according to the first embodiment of the present invention. The oscillation stop detection circuit shown in FIG. 1 is mounted on a one-chip microcomputer having a built-in PLL.
[0019]
The oscillation stop detection circuit shown in FIG. 1 includes an oscillation stop detection circuit 100 that detects the stop of the externally generated clock signal XIN from an external oscillation circuit (not shown), a clock signal that outputs the externally generated clock signal XIN by itself, A PLL circuit 10 that synchronizes the phase and multiplies the phase-synchronized signal by n; and an external generation circuit that stops the externally generated clock signal XIN input from the external oscillation circuit to the oscillation stop detection circuit 100 when the external oscillation circuit is detected to be stopped. It comprises a clock stop circuit 200.
[0020]
The externally generated clock stop circuit 200 includes a knot circuit 60 for inverting the external clock stop detection signal CT11 output from the oscillation stop detection circuit 100 when the externally generated clock signal XIN stops, an externally generated clock signal XIN and the knot circuit 60. And a NOT circuit 80 for inverting a signal output from the NAND circuit 70.
[0021]
When the externally generated clock signal XIN is stopped and the output “H” of the external clock stop detection signal CT11 is generated, the knot circuit 60 inverts the output “H” and inputs the output “L” to the NAND circuit 70. . On the other hand, when the externally generated clock signal XIN is operating and the output of the external clock stop detection signal CT11 is “L”, the output “L” is inverted and the output “H” is input to the NAND circuit 70.
[0022]
The NAND circuit 70 outputs “H” regardless of the input signal from the other externally generated clock signal XIN when the output “L” from the knot circuit 60 is input. When "H" is output from, this is inverted and "L" is output. On the other hand, when the output “H” from the knot circuit 60 is input to the NAND circuit 70, the NAND circuit 70 inverts the input signal from the externally generated clock signal XIN and outputs it.
[0023]
Therefore, when the external clock stop detection signal CT11 is generated, "L" is input to the PLL circuit 10, and the externally generated clock signal XIN is not completely input.
[0024]
FIG. 2 is a diagram showing a configuration of the oscillation stop detection circuit 100 in the microcomputer with a built-in PLL according to the present invention. The oscillation stop detection circuit 100 shown in FIG. 2 detects an edge of an externally generated clock signal XIN input from a connection terminal of the external oscillation circuit, and outputs an edge detection signal XEDGE, and an edge detection signal XEDGE. And an internal circuit signal SCLK output from the VCO 14 of the PLL circuit 10 is input to a count clock terminal as a count source, and an output CT_CLR of the OR circuit 40 is input to a clear terminal. And an AND circuit 51 for ANDing a 2-bit output of the counter 30 with an OR circuit 52 and a flip-flop 53 for temporarily storing 1-bit information output by the AND. And a clock signal stop detection unit 50. The externally generated clock signal XIN input from the connection terminal of the external oscillation circuit is input to the PLL circuit 10, and the internal clock signal SCLK output from the PLL circuit 10 is input to the counter 30.
[0025]
In this case, the edge detection circuit 20 has a delay circuit 21 for delaying the externally generated clock signal XIN, and an exclusive OR gate 22 for obtaining an exclusive OR of the externally generated clock signal XIN and the output of the delay circuit 21. With these configurations, both edges (falling edge and rising edge) of the externally generated clock signal XIN are detected, and an edge detection signal XEDGE which becomes, for example, "H" when both edges are detected is output.
[0026]
The OR circuit 40 performs a logical OR operation of the edge detection signal XEDGE and the initialization signal INITIAL asserted at the time of system reset, and inputs the output CT_CLR to the clear terminal of the counter 30.
[0027]
The PLL circuit 10 includes a phase comparator 11, a charge pump 12, a capacitor 13, a VCO (voltage controlled oscillator) 14, and a frequency divider 15. The phase comparator 11 compares the phase of the output clock CLK output from the frequency divider 15 of the PLL circuit 10 with the phase of the externally generated clock signal XIN input from the connection terminal of the external oscillation circuit. The phase comparator 11 outputs a phase advance signal or a phase delay signal according to the phase shift to the charge pump 12. The charge pump 12 charges / discharges the capacitor 13 with the phase lead / lag signal.
[0028]
As a result of the phase comparison by the phase comparator 11, when the oscillation frequency of the output clock CLK of the PLL circuit 10 is lower than the frequency of the externally generated clock signal XIN, the pair of the phase comparator 11 and the charge pump 12 In the direction of injecting charges into the capacitor 13 (increasing the potential VCNT of the output node). Conversely, when the oscillation frequency of the output clock CLK of the PLL circuit 10 is higher than the frequency of the externally generated clock signal XIN, the pair of the phase comparator 11 and the charge pump 12 extracts the charge from the capacitor 13 at the output node ( It operates in the direction of lowering the potential VCNT of the node).
[0029]
The VCO (voltage controlled oscillator) 14 is an oscillator that outputs a frequency according to the output voltage of the charge pump 12 (the potential VCNT at the output node). The VCO 14 outputs an oscillation signal whose oscillation frequency increases when the potential of the output node potential VCNT is high, and whose oscillation frequency decreases when the potential of the output node potential VCNT is low. This oscillation signal is output as an internal clock signal SCLK, and is used in each circuit such as a CPU (not shown) in the microcomputer. The internal clock signal SCLK output from the VCO 14 is frequency-divided by n (n = 2 in this case) by the frequency divider 15 and then input to the phase comparator 11, where the phase is compared with the externally generated clock signal XIN.
[0030]
In this feedback loop, a frequency divider 15 for dividing the output of the VCO 14 by n is inserted. Therefore, the phase comparator 11 uses a signal having a frequency of 1 / n of the output of the VCO 14 as a comparison signal and outputs an externally generated clock signal. XIN will be compared and these phases will be synchronized. As a result, the internal clock signal SCLK synchronously oscillated at the frequency of n (in this case, n = 2) times the externally generated clock signal XIN can be finally obtained from the VCO 14.
[0031]
The graph of FIG. 3 shows general characteristics of the VCO 14. It should be noted that the VCO 14 continues to oscillate at a low specific frequency fc even when the potential VCNT of the output node becomes the ground level. Therefore, even if the externally generated clock signal XIN is stopped, an oscillation signal having a specific frequency fc can be extracted from the PLL circuit 10.
[0032]
In this case, the counter 30 is configured by a 2-bit counter. The counter 30 counts up using the internal clock signal SCLK as a count source, and is cleared by an edge of XIN or an initialization signal INITIAL asserted at the time of system reset. In this case, the VCO 14 generates an internal clock signal SCLK that is twice the externally generated clock signal XIN, and the edge detection circuit 20 detects both edges of the externally generated clock signal XIN. The edge detection signal XEDGE (CT_CLR) from the circuit 20 is generated once in one cycle of the internal clock signal SCLK.
[0033]
The externally generated clock signal stop detection unit 50 includes an AND circuit 51, an OR circuit 52, and a flip-flop 53. The AND circuit 51 calculates the logical product of the two-bit output of the counter 30, and the OR circuit 52 and the flip-flop 53 temporarily store the 1-bit information output from the AND circuit 51 and generate the external clock stop detection signal CT11. Output. In this case, when both the 2-bit outputs of the counter 30 become "H", the external clock stop detection signal CT11 is output. When the external clock stop detection signal CT11 is generated, it is determined that the externally generated clock signal XIN stops. The externally generated clock stop circuit 200 uses this external clock stop detection signal CT11 to input “L” to the PLL circuit 10 to completely stop the externally generated clock signal XIN. Further, the oscillation of the externally generated clock signal XIN is stopped by using the external clock stop detection signal CT11 to set a readable state flag from the CPU or to generate a reset interrupt to the CPU. Can be notified to the CPU.
[0034]
Next, the operation of each unit in FIGS. 1 and 2 will be described according to the time charts shown in FIGS. First, an operation when the externally generated clock signal XIN oscillates normally will be described with reference to FIG.
[0035]
As shown in FIG. 4, the VCO 14 generates an internal clock signal SCLK that is twice the externally generated clock signal XIN, and the edge detection circuit 20 detects both edges of the externally generated clock signal XIN. The edge detection signal XEDGE (CT_CLR) from the detection circuit 20 is generated once in one cycle of the internal clock signal SCLK. Therefore, the counter 30 makes a transition from 00 to 01, and repeats the operation of being cleared immediately after the transition to 01. Since the external clock stop detection signal CT11 is a signal which becomes “H” when the value of the counter 30 becomes “11”, it is always “L” when the externally generated clock signal XIN shown in FIG. 4 is normal. is there.
[0036]
Next, the operation when the externally generated clock signal XIN stops will be described with reference to FIG. When the oscillation of the externally generated clock signal XIN stops, the charge pump 12 operates in the direction of decreasing the potential of the potential VCNT of the output node. However, as shown in the graph of FIG. Even if the voltage drops to the ground level, the internal clock signal SCLK does not stop, and the counter 30 continues counting up. Then, after a certain time (in this case, three clocks after XIN stop), the counter output becomes “11” and the external clock stop detection signal becomes “H”.
[0037]
When the output “H” of the external clock stop detection signal CT11 is generated from the AND circuit 51, the OR circuit 52 and the flip-flop 53 maintain the state in which the output “H” is temporarily stored, and detect the external clock stop. The signal CT11 is output. Then, the output “H” of the external clock stop detection signal CT11 is inverted by the knot circuit 60 and the output “L” is input to the NAND circuit 70. As a result, the NAND circuit 70 maintains the "H" output, and the knot circuit 80 maintains the "L" output.
[0038]
As described above, when the output “H” of the external clock stop detection signal CT11 occurs, the state where the “L” from the knot circuit 80 is input to the PLL circuit 10 continues. As a result, the externally generated clock signal XIN is not input to the PLL circuit 10. The VCO 14 outputs an internal clock signal SCLK multiplied by n to the internal clock of the microcomputer.
[0039]
The external clock stop detection signal CT11 is used to set a readable state flag from the CPU, or to generate a reset interrupt to the CPU to notify the CPU that the externally generated clock signal XIN has stopped. You can let me know.
[0040]
Furthermore, even if the externally generated clock signal XIN oscillates abnormally thereafter, the externally generated clock signal XIN is not input to the PLL circuit 10, so that the PLL circuit 10 is stably specified without being affected by the externally generated clock signal XIN. The internal clock signal SCLK having the frequency fc can be oscillated. Further, since the internal clock signal SCLK continues to oscillate, even if the externally generated clock signal XIN stops, the CPU can continue to operate without switching to another internal clock signal, and appropriate fail-safe measures can be taken. Can be taken.
[0041]
In the above-described first embodiment, an example has been described in which the external clock stop detection signal CT11 is generated three clocks after the XIN stop, but the number of bits of the counter is further increased to generate the external clock stop detection signal CT11 signal. Can be arbitrarily selected, an arbitrary number of clocks such as 4, 5, 6,... Can be set as the waiting time.
[0042]
The input of XIN may be stopped by a configuration in which a control signal is generated to the NAND circuit 70 of the externally generated clock stop circuit 200 by referring to the state flag or by interruption by software in the CPU (not shown).
[0043]
Further, the input of XIN may be stopped by referring to the status flag by a signal from an external terminal (not shown) or generating a control signal to the NAND circuit 70 of the externally generated clock stop circuit 200 by interruption.
[0044]
According to the first embodiment, when the external clock stop detection signal CT11 is output from the oscillation stop detection circuit 100, the externally generated clock stop circuit 200 continues to output “L”. XIN is not input to the PLL circuit 10. Therefore, voltage-controlled oscillator (VCO) 14 of PLL circuit 10 can output internal clock signal SCLK of specific frequency fc in a stable state without being affected by externally generated clock signal XIN.
[0045]
Further, in the microcomputer with a built-in PLL, when the externally generated clock signal XIN is stopped, the externally generated clock signal XIN is supplied to the PLL circuit 10 with a very simple configuration of the knot circuit 60, the NAND circuit 70, and the knot circuit 80 and a small occupied area. You can keep stopping the input.
[0046]
Further, the input of the externally generated clock signal XIN to the PLL circuit 10 can be continuously stopped without impairing the original functions of the PLL such as the phase synchronization and the generation of the multiplied signal. Further, without providing another reference transmission source inside, fail-safe measures when the externally generated clock signal XIN stops can be performed in a stable state.
[0047]
Embodiment 2 FIG.
Embodiment 2 of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of an oscillation stop detection circuit in a microcomputer with a built-in PLL according to a second embodiment of the present invention. Among the components shown in FIG. 6, the first embodiment shown in FIGS. Components that achieve the same function as the oscillation stop detecting circuit in the PLL built-in microcomputer of FIG.
[0048]
The oscillation stop detection circuit 101 shown in FIG. 6 is mounted on a one-chip microcomputer having a built-in PLL. 6, the oscillation stop detection circuit 101 includes a transistor 90 having one of a source and a drain grounded. When the externally generated clock signal XIN stops and the external clock stop detection signal CT11 outputs “H”, the transistor 90 inverts this signal and outputs a signal “L”. Further, the signal “L” is configured to be input to the capacitor 13 of the PLL circuit 10.
[0049]
Therefore, when the externally generated clock signal XIN is stopped and the output “H” of the external clock stop detection signal CT11 is generated from the externally generated clock signal stop detection unit 50, the signal “L” is output from the transistor 90 to the capacitor 13 of the PLL circuit 10. Continues, and the VCO 14 is not affected by the potential change of the potential VCNT of the output node. As a result, even if the clock frequency of the externally generated clock signal XIN is increased, the PLL circuit 10 is not affected by the increase, and can stably output the internal clock signal SCLK having the specific frequency fc.
[0050]
The function of the transistor 90 may be stopped by referring to the status flag by software in the CPU (not shown) or generating a control signal to the transistor 90 by interruption.
[0051]
Further, the function of the transistor 90 may be stopped by referring to a state flag by a signal from an external terminal (not shown) or generating a control signal to the transistor 90 by interruption.
[0052]
As described above, according to the second embodiment, when the external clock stop detection signal CT11 is output from the oscillation stop detection circuit 101, the transistor 90 continues to output “L”, so that the VCO 14 of the PLL circuit 10 An internal clock signal SCLK having a specific frequency fc can be output in a stable state without being affected.
[0053]
When the externally generated clock signal XIN is stopped in the microcomputer with a built-in PLL, the VCO 14 has an extremely simple configuration in which the microcomputer with a built-in PLL has a transistor 90 and has a small occupied area. You can continue to not receive.
[0054]
Further, the VCO 14 can be kept in a state where the VCO 14 is not affected by the potential change of the potential VCNT of the output node without impairing the original functions of the PLL such as the phase synchronization and the generation of the multiplied signal. Furthermore, the fail-safe measure when the externally generated clock signal XIN stops can be performed in a stable state without providing another reference transmission source inside.
[0055]
【The invention's effect】
As described above, according to the present invention, when the stop of the external oscillation circuit is detected with a simple configuration and with a small dedicated circuit area, the input of the externally generated clock signal XIN from the external oscillation circuit to the microcomputer is stopped. Therefore, there is an effect that a fail-safe measure can be taken in a stable state.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a microcomputer with a built-in PLL according to a first embodiment of the present invention;
FIG. 2 is a circuit block diagram illustrating an oscillation stop detection circuit.
FIG. 3 is a graph showing a relationship between a VCO input VCNT and a VCO output.
FIG. 4 is a time chart showing the operation of each unit when the externally generated clock signal XIN oscillates normally.
FIG. 5 is a time chart showing the operation of each unit when the externally generated clock signal XIN stops.
FIG. 6 is a block diagram illustrating a configuration of a microcomputer with a built-in PLL according to a second embodiment of the present invention;
[Explanation of symbols]
Reference Signs List 10 PLL circuit, 11 phase comparator, 12 charge pump, 13 capacitor, 14 voltage controlled oscillator (VCO), 15 divider, 20 edge detection circuit, 21 delay circuit, 22 exclusive OR gate, 30 counter, 40, 52 OR circuit, 50 externally generated clock signal stop detection section, 51 AND circuit, 53 flip-flop 60, 80 knot circuit, 70 NAND circuit, 90 transistor 90, 100 oscillation stop detection circuit, 200 externally generated clock stop circuit, CT11 external clock Stop detection signal, SCLK internal clock signal, XIN externally generated clock signal.

Claims (7)

An edge detection circuit for detecting an edge of the input externally generated clock signal;
A PLL circuit for synchronizing the input externally generated clock signal with a clock signal to be output by itself, multiplying the phase-synchronized signal by n, and outputting the multiplied signal as an internal clock signal used inside the microcomputer;
A counter that is cleared by an output of the edge detection circuit and performs a count operation using an internal clock signal output from the PLL circuit as a count source;
When the output of the counter exceeds a predetermined set value, an externally generated clock signal stop detection unit that detects this as a stop of the externally generated clock signal and continues to output an external clock stop detection signal,
An externally generated clock stop circuit that stops inputting an externally generated clock signal to the edge detection circuit and the PLL circuit while the external clock stop detection signal is being output;
A microcomputer with a built-in PLL, comprising: An edge detection circuit for detecting an edge of the input externally generated clock signal;
A PLL circuit for synchronizing the input externally generated clock signal with a clock signal to be output by itself, multiplying the phase-synchronized signal by n, and outputting the multiplied signal as an internal clock signal used inside the microcomputer;
A counter that is cleared by an output of the edge detection circuit and performs a count operation using an internal clock signal output from the PLL circuit as a count source;
When the output of the counter exceeds a predetermined set value, an externally generated clock signal stop detection unit that detects this as a stop of the externally generated clock signal and continues to output an external clock stop detection signal,
While the external clock stop detection signal is being output, a ground potential providing unit that sets the phase-synchronized signal to a ground potential,
A microcomputer with a built-in PLL, comprising: 3. The microcomputer with a built-in PLL according to claim 1, wherein a reset interrupt is generated by the external clock stop detection signal. 4. The microcomputer with a built-in PLL according to claim 1, wherein a predetermined state flag readable by a CPU is set by the external clock stop detection signal. The microcomputer with a built-in PLL according to any one of claims 1 to 4, wherein a set value in the externally generated clock signal stop detection unit can be set to an arbitrary value. The microcomputer with a built-in PLL according to any one of claims 1 to 3, further comprising software or an external terminal capable of selecting whether to use the externally generated clock stop circuit. The microcomputer with a built-in PLL according to any one of claims 2 to 5, further comprising software or an external terminal capable of selecting whether or not to use the ground potential providing unit.

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