JP2004328094A - Video signal processing apparatus and method - Google Patents

Abstract

Kind Code: A1 Two digital video signals are synchronized without using a PLL.
A phase detection circuit detects a phase difference between a synchronization signal indicating a start position of image data input from an asynchronous FIFO circuit and a synchronization signal indicating a start position of image data input from an asynchronous FIFO circuit. Then, the detection result is supplied to the selection circuit 41. The selection circuit 41 adjusts the phases of the image data from the asynchronous FIFO circuit 31 and the image data from the asynchronous FIFO circuit 35 based on the detection result supplied from the phase detection circuit 38 and outputs the same to the image synthesis circuit 7. Select terminal a, terminal b, or terminal c.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a video signal processing device and method, and more particularly, to a video signal processing device and method suitable for use in performing, for example, video signal synchronization processing.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a horizontal synchronization circuit in a television system, a horizontal synchronization signal is used as a comparison pulse, and an output of a VOC (Voltage Controlled Oscillator) is divided by N and a reference pulse is used as a reference pulse. Various phase pulses are generated by the system. The PLL is such that a reference signal input from the outside and an output of an oscillator (VOC) in a loop or a pulse signal obtained by dividing the output of the oscillator by N are the same in frequency and phase. Is an oscillation circuit that adjusts the oscillation frequency by performing feedback control on the oscillator in the loop.
[0003]
As described above, in the PLL system used in the television system, jitter is removed by removing noise or the like in the synchronization signal (see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-10-327333
[0005]
[Problems to be solved by the invention]
However, at present, so-called digital signal processing in which a video signal is not processed as an analog signal but is processed as a discrete numerical value is in use. Therefore, when a conventional PLL system for processing an analog signal receives an input of a digital video signal, the output of the oscillator (VOC) has a large amount of jitter.
[0006]
In the case where two digital video signals are generated by separate image generation circuits and are synthesized by the image synthesis circuit, the image synthesis circuit receives clocks output from the two image generation circuits. In addition, it is necessary to perform processing by switching to a clock used for image synthesis.
[0007]
However, the delay amount of the two image generation circuits is unknown or indeterminate, and no limitation can be given to the phase relationship between these two clocks, and it is difficult to synchronize two digital video signals. There was an issue.
[0008]
The present invention has been made in view of such a situation, and it is an object of the present invention to perform a synthesizing process or the like by synchronizing two digital video signals without using a PLL.
[0009]
[Means for Solving the Problems]
The video signal processing apparatus according to the present invention is configured such that a first input means for inputting first image data generated in synchronization with a first clock signal, and a phase difference between the first clock signal and an internal clock signal. A first output unit that outputs the first image data together with a synchronization signal of the first image data, and a second output unit that inputs the second image data generated in synchronization with the second clock signal. Input means, second output means for outputting second image data together with a synchronization signal of the second image data based on the phase difference between the second clock signal and the internal clock signal, and first image data Detecting means for detecting a phase difference between the synchronizing signal and the synchronizing signal of the second image data, and selecting means for selecting a delay amount of the second image data based on a detection result by the detecting means. And
[0010]
The image processing apparatus may further include a delay unit that delays the first image data output by the first output unit.
[0011]
The selecting means may select a delay amount for synchronizing the second image data with the first image data delayed by the delay means.
[0012]
The first and second clock signals and the internal clock may be at the same frequency.
[0013]
A video signal processing method according to the present invention includes a first input step of inputting first image data generated in synchronization with a first clock signal, and a phase difference between the first clock signal and an internal clock signal. A first output step of outputting the first image data together with a synchronization signal of the first image data, and a second output step of inputting the second image data generated in synchronization with the second clock signal. An input step, a second output step of outputting second image data together with a synchronization signal of the second image data based on a phase difference between the second clock signal and the internal clock signal, and a first image data A detecting step of detecting a phase difference between the synchronizing signal of the second image data and the synchronizing signal of the second image data, and a selecting step of selecting a delay amount of the second image data based on a detection result by the processing of the detecting step. And wherein the door.
[0014]
In the present invention, first image data generated in synchronization with a first clock signal is input, and the first image data is converted to a first image data based on a phase difference between the first clock signal and an internal clock. And the second image data generated in synchronization with the second clock signal is input, and the second image data is output based on the phase difference between the second clock and the internal clock. Is output together with the synchronization signal of the second image data, the phase difference between the synchronization signal of the first image data and the synchronization signal of the second image data is detected, and the second image data is Is selected.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below. The correspondence between constituent elements described in the claims and specific examples in the embodiments of the present invention is as follows. This description is for confirming that a specific example supporting the invention described in the claims is described in the embodiment of the invention. Therefore, even if there is a specific example which is described in the embodiment of the invention but is not described here as corresponding to the configuration requirement, the fact that the specific example is It does not mean that it does not correspond to the requirement. Conversely, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.
[0016]
Furthermore, this description does not mean that the invention corresponding to the specific examples described in the embodiments of the invention is all described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of the invention not described in the claims of this application, that is, It does not deny the existence of the invention added by the amendment.
[0017]
The video signal processing device according to claim 1 (for example, the video signal processing circuit 6 in FIG. 1) includes a first input unit that inputs first image data generated in synchronization with a first clock signal. For example, the first image data is output together with the synchronization signal of the first image data based on the data input terminal D2 of the asynchronous FIFO circuit 31 in FIG. 1 and the phase difference between the first clock signal and the internal clock signal. First output means (for example, the data output terminal Q2 and the synchronization signal output terminal Q1 of the asynchronous FIFO circuit 31 in FIG. 1) and the second image data generated in synchronization with the second clock signal are input. Based on the second input means (for example, the data input terminal D2 of the asynchronous FIFO circuit 35 in FIG. 1) and the phase difference between the second clock signal and the internal clock signal, the second image data is converted into the second image data. data A second output unit (for example, the data output terminal Q2 and the synchronization signal output terminal Q1 of the asynchronous FIFO circuit 35 in FIG. 1) that outputs the synchronization signal together with the synchronization signal, and the synchronization of the synchronization signal of the first image data and the second image data. Detecting means for detecting a phase difference between signals (for example, the phase detecting circuit 38 in FIG. 1), and selecting means for selecting a delay amount of the second image data based on a detection result by the detecting means (for example, FIG. 1) And a selection circuit 41).
[0018]
The video signal processing device according to claim 2 further includes a delay unit (for example, the delay circuit 34 in FIG. 1) that delays the first image data output by the first output unit.
[0019]
The selection means of the video signal processing device according to claim 3 selects a delay amount for synchronizing the second image data with the first image data delayed by the delay means (for example, the selection circuit 41 in FIG. 1). (Terminals a, b, and c) are selected).
[0020]
The first and second clock signals and the internal clock signal of the video signal processing device according to claim 4 have the same frequency (for example, at the same frequency as the clock signal generated by the clock generation circuit 1 in FIG. 1). ).
[0021]
The video signal processing method according to claim 5, wherein the first image data (for example, FIG. 2B, FIG. 3B, or FIG. 4B) is generated in synchronization with a first clock signal. A first input step of inputting the image data shown in FIG. 2C, FIG. 3C, or FIG. 4C; a first clock signal and an internal clock signal (for example, an internal processing clock signal shown in FIG. 2E, FIG. 3E, or FIG. 4E); ), The first image data (for example, the image data shown in FIG. 2F, FIG. 3F, or FIG. 4F) is converted to a synchronization signal of the first image data (FIG. 2G, FIG. 3G, or FIG. 4G). , And a second image data (for example, a clock signal shown in FIG. 2I, FIG. 3I, or FIG. 4I) generated in synchronization with a second clock signal (for example, the clock signal shown in FIG. For example, 2J, 3J, or 4J), a second input step, a second clock signal and an internal clock signal (for example, an internal processing clock signal shown in FIG. 2L, 3L, or 4L). ), The second image data (for example, the image data shown in FIG. 2M, FIG. 3M, or FIG. 4M) is converted into a synchronization signal (FIG. 2N, FIG. 3N, or FIG. 4N) of the second image data. (A synchronization signal shown in FIG. 3), a detection step of detecting a phase difference between a synchronization signal of the first image data and a synchronization signal of the second image data, and a detection result obtained by the processing of the detection step. And a selecting step of selecting a delay amount of the second image data based on the selection.
[0022]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 shows a configuration example of a video signal processing system to which the present invention is applied. As shown in FIG. 1, the video signal processing system includes a clock generation circuit 1, image generation circuits 2 and 3, an amplifier 4, a reset signal output circuit 5, a video signal processing circuit 6, an image synthesis circuit 7, and the like. The video signal processing circuit 6 includes asynchronous FIFO (First In First Out) circuits 31, 35, delay circuits 32, 36, AND circuits 33, 37, a delay circuit 34, a phase detection circuit 38, delay circuits 39, 40, And a selection circuit 41.
[0024]
The clock generation circuit 1 generates a high-frequency clock signal and outputs it to the amplifier 4, the image generation circuit 2, and the image generation circuit 3, respectively.
[0025]
The image generation circuit 2 amplifies the clock signal input from the clock generation circuit 1 with the amplifier 11 and outputs the amplified clock signal to the asynchronous FIFO circuit 31. The image generation circuit 2 also generates a digital image signal (hereinafter, referred to as image data) based on the clock signal input from the clock generation circuit 1, and generates a synchronization signal (for example, a start signal of the generated image data). , HDISP, etc.) to the asynchronous FIFO circuit 31.
[0026]
Similarly, the image generation circuit 3 amplifies the clock signal input from the clock generation circuit 1 by the amplifier 21 and outputs the amplified clock signal to the asynchronous FIFO circuit 35. The image generation circuit 3 also generates image data based on the clock signal input from the clock generation circuit 1 and outputs the image data to the asynchronous FIFO circuit 35 together with a synchronization signal indicating the start position.
[0027]
Note that the image generation circuits 2 and 3 operate with the same number of horizontal dots and the same number of vertical lines, and the image data generated by them is set up and held with respect to the clock signals output from the amplifiers 11 and 21. Are input to the asynchronous FIFO circuits 31 and 35, respectively.
[0028]
The amplifier 4 amplifies the clock signal input from the clock generation circuit 1 and outputs it to the asynchronous FIFO circuit 31, the asynchronous FIFO circuit 35, the delay circuit 34, and the image synthesizing circuit 7, respectively. The reset signal output circuit 5 outputs a reset signal to each of the asynchronous FIFO circuit 31 and the asynchronous FIFO circuit 35, and releases the reset at a predetermined timing.
[0029]
A clock signal from the image generation circuit 2 is input to a clock terminal wck of the asynchronous FIFO circuit 31, an internal processing clock signal is input from the amplifier 4 to a clock terminal rck, and a reset signal output circuit is input to the asynchronous reset terminal rst. 5, a reset signal is input.
[0030]
The asynchronous FIFO circuit 31 is reset by a reset signal input to the asynchronous reset terminal rst. When the reset is released at a predetermined timing, the image is output from the image generation circuit 2 to the data input terminal D2. Data is input, and a synchronization signal is input from the image generation circuit 2 to the synchronization signal input terminal D1.
[0031]
Further, in the asynchronous FIFO circuit 31, the status flag of the empty terminal / emp (negative logic) that has been enabled becomes invalid by inputting data after reset release. This signal is output as a read signal to the delay circuit 32 and supplied to one input of the AND circuit 33. The delay circuit 32 delays the read signal input to the input terminal D by one clock, and supplies the read signal from the output terminal Q to the other input of the AND circuit 33. The AND circuit 33 calculates the logical product of the output of the asynchronous FIFO circuit 31 and the output of the delay circuit 32, and outputs the calculation result to the asynchronous FIFO circuit 31.
[0032]
When the read signal is input to the read detection terminal RE, the asynchronous FIFO circuit 31 compares the phase of the clock signal input to the clock terminal wck with the phase of the internally processed clock signal input to the clock terminal rck, and compares the comparison result. Based on this, the image data in the asynchronous FIFO circuit 31 is read out, output from the data output terminal Q2 to the delay circuit 34, and a synchronization signal indicating the start position of the image data is output from the synchronization signal output terminal Q1 to the phase detection circuit 38. I do.
[0033]
That is, the asynchronous FIFO circuit 31 starts reading after the remaining amount of data in the asynchronous FIFO circuit 31 becomes at least 2 by delaying the read signal by one clock by the delay circuit 32. The above device.
[0034]
The delay circuit 34 delays the image data input from the asynchronous FIFO circuit 31 to the data input terminal D by one clock based on the internal processing clock signal input from the amplifier 4, and outputs the image data from the data output terminal Q to the image generation circuit 7. Output to
[0035]
A clock signal from the image generation circuit 3 is input to the clock terminal wck of the asynchronous FIFO circuit 35, an internal processing clock signal is input from the amplifier 4 to the clock terminal rck, and a reset signal output circuit is input to the asynchronous reset terminal rst. 5, a reset signal is input.
[0036]
The asynchronous FIFO circuit 35 is reset by the reset signal input to the asynchronous reset terminal rst. When the reset is released at a predetermined timing, the image is output from the image generation circuit 3 to the data input terminal D2. Data is input, and a synchronization signal is input from the image generation circuit 3 to the synchronization signal input terminal D1.
[0037]
Further, in the asynchronous FIFO circuit 35, when the data is input after the reset release, the status flag of the empty terminal / emp (negative logic) that has been enabled becomes invalid. This signal is output as a read signal to the delay circuit 36 and supplied to one input of an AND circuit 37. The delay circuit 36 delays the read signal input to the input terminal D by one clock, and supplies the read signal to the other input of the AND circuit 37 from the output terminal Q. The AND circuit 37 calculates the logical product of the output of the asynchronous FIFO circuit 35 and the output of the delay circuit 36, and outputs the calculation result to the asynchronous FIFO circuit 35.
[0038]
When the read signal is input to the read detection terminal RE, the asynchronous FIFO circuit 35 compares the phase of the clock signal input to the clock terminal wck with the phase of the internal processing clock signal input to the clock terminal rck, and compares the comparison result with the result of the comparison. The image data in the asynchronous FIFO circuit 35 is read out and output to the selection circuit 41 directly from the data output terminal Q2, to the selection circuit 41 via the delay circuit 39, or to the delay circuit 39 and the delay circuit Output to the selection circuit 41 via 40. The asynchronous FIFO circuit 35 outputs a synchronization signal indicating the start position of the image data output to the selection circuit 41 from the synchronization signal output terminal Q1 to the phase detection circuit 38.
[0039]
That is, the asynchronous FIFO circuit 35 is a device having a depth of 2 or more which starts reading after the remaining amount of data in the asynchronous FIFO circuit 35 becomes at least 2 by delaying the read signal by one clock by the delay circuit 36. is there.
[0040]
The phase detection circuit 38 detects the phase difference between the synchronization signals input from the asynchronous FIFO circuits 31 and 35, and supplies the detection result to the selection circuit 41. The selection circuit 41 selects the terminal a, the terminal b, or the terminal c based on the detection result (phase difference) supplied from the phase detection circuit 38.
[0041]
For example, when the start position of the synchronization signal input from the asynchronous FIFO circuit 31 is ahead of the synchronization signal input from the asynchronous FIFO circuit 35, the selection circuit 41 selects the terminal a. Thus, the image data output from the asynchronous FIFO circuit 35 is output from the output terminal d of the selection circuit 41 to the image synthesis circuit 7 as it is (without delay).
[0042]
In addition, for example, when the synchronization signal input from the asynchronous FIFO circuit 31 and the synchronization signal input from the asynchronous FIFO circuit 35 have the same phase, the selection circuit 41 selects the terminal b. As a result, the image data output from the asynchronous FIFO circuit 35 is delayed by one clock by the delay circuit 39, and output from the output terminal d of the selection circuit 41 to the image synthesis circuit 7.
[0043]
Further, for example, when the start position of the synchronization signal input from the asynchronous FIFO circuit 31 is later than that of the synchronization signal input from the asynchronous FIFO circuit 35, the selection circuit 41 selects the terminal c. Thus, the image data output from the asynchronous FIFO circuit 35 is delayed by one clock by the delay circuit 39, further delayed by one clock by the delay circuit 40, and transmitted from the output terminal d of the selection circuit 41 to the image synthesis circuit 7. Is output.
[0044]
The image synthesizing circuit 7 synthesizes and outputs the image data from the asynchronous FIFO circuit 31 and the image data from the asynchronous FIFO circuit 35 whose phases have been aligned based on the internal processing clock signal input from the amplifier 4.
[0045]
Next, the selection operation of the selection circuit 41 will be described with reference to the timing charts of FIGS. First, the operation when the terminal a of the selection circuit 41 is selected will be described with reference to the timing chart of FIG.
[0046]
In a state where the video signal processing circuit 6 is reset, the clock signals WA1 to WA5 amplified by the amplifier 11 of the image generation circuit 2 are input to the clock terminal wck of the asynchronous FIFO circuit 31 (FIG. 2B). Clock signals WB1 to WB5 amplified by the amplifier 21 of the image generation circuit 3 are input to a clock terminal wck of the FIFO circuit 35 (FIG. 2I). The clock signal rck of the asynchronous FIFO circuit 31 receives the internal processing clock signals RA1 to RA5 from the amplifier 4 (FIG. 2E), and the clock terminal rck of the asynchronous FIFO circuit 35 receives the internal processing clock signal RB1 from the amplifier 4. To RB5 are input (FIG. 2L).
[0047]
When the reset is released (FIG. 2A), the image data DA1 generated by the image generation circuit 2 based on the first clock signal WA2 immediately after the reset is released is supplied to the data input terminal D2 of the asynchronous FIFO circuit 31. Input is started (FIG. 2C), and a synchronization signal SA indicating the start position of the image data DA1 is input to the synchronization signal input terminal D1 (FIG. 2D). Further, input of image data DB1 generated by the image generation circuit 3 based on the first clock signal WB2 immediately after reset release is started to the data input terminal D2 of the asynchronous FIFO circuit 35 (FIG. 2J), and the synchronization signal The synchronization signal SB indicating the start position of the image data DB1 is input to the input terminal D1 (FIG. 2K).
[0048]
Here, the asynchronous FIFO circuit 31 compares the phases of the clock signal WA2 (FIG. 2B) input to the clock terminal wck and the internal processing clock signal RA2 (FIG. 2E) input to the clock terminal rck immediately after reset release. As shown in the figure, the start position of the clock signal WA2 is ahead of the start position of the internal processing clock signal RA2. In this case, the asynchronous FIFO circuit 31 immediately starts reading the image data input to the data input terminal D2, but since the read start position is delayed by one clock by the delay circuit 32, the remaining data amount is 2 The reading is started after reaching.
[0049]
That is, when the image data DA1 and the image data DA2 are accumulated in the asynchronous FIFO circuit 31 (FIG. 2C), they are read and output from the data output terminal Q2 to the delay circuit 34 (FIG. 2F). Further, a synchronization signal SA indicating the start position of the image data DA1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (FIG. 2G).
[0050]
Similarly, the asynchronous FIFO circuit 35 also compares the phases of the clock signal WB2 (FIG. 2I) input to the clock terminal wck and the internal processing clock signal RB2 (FIG. 2L) input to the clock terminal rck immediately after reset release. As shown in the figure, the start position of the clock signal WB2 is later than the start position of the internal processing clock signal RB2. In this case, since the reading start position is delayed by one clock by the delay circuit 36, the asynchronous FIFO circuit 35 starts reading after the remaining data amount becomes three.
[0051]
That is, when the image data DB1 to DB3 are accumulated in the asynchronous FIFO circuit 35 (FIG. 2J), they are read and output from the data output terminal Q2 to the selection circuit 41 (FIG. 2M). Further, a synchronization signal SB indicating the start position of the image data DB1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (FIG. 2N).
[0052]
The delay circuit 34 delays the image data input from the asynchronous FIFO circuit 31 by one clock, and outputs it to the image generation circuit 7 (FIG. 2H).
[0053]
The phase detection circuit 38 detects a phase difference between the synchronization signal SA (FIG. 2G) input from the asynchronous FIFO circuit 31 and the synchronization signal SB (FIG. 2N) input from the asynchronous FIFO circuit 35, and determines the detection result as a selection circuit 41. To supply. In this case, since the synchronization signal SA is ahead of the synchronization signal SB by one clock, the asynchronous FIFO circuit 31 reads image data one clock earlier than the asynchronous FIFO circuit 35.
[0054]
However, the image data DA1 whose reading has been started by the asynchronous FIFO circuit 31 is output to the image synthesizing circuit 7 after being delayed by one clock by the delay circuit 34, so that the reading is delayed by one clock from the asynchronous FIFO circuit 31. The started image data DB1 of the asynchronous FIFO circuit 35 is output to the image synthesizing circuit 7 at the same timing as the asynchronous FIFO circuit 31. Therefore, the selection circuit 41 selects the terminal a, and outputs the image data DB1 read out by the asynchronous FIFO circuit 35 directly to the image synthesis circuit 7 (without passing through a delay circuit) (FIG. 2O). Accordingly, the image data DA1 output from the asynchronous FIFO circuit 31 and the image data DB1 output from the asynchronous FIFO circuit 35 are input to the image synthesizing circuit 7 with the phases thereof aligned, so that the synthesizing process is easily performed. be able to.
[0055]
As described above, immediately after reset release, the start position of the clock signal WA2 (FIG. 2B) input to the clock terminal wck of the asynchronous FIFO circuit 31 is determined by the internal processing clock signal RA2 (FIG. 2E) input to the clock terminal rck. , And the start position of the clock signal WB2 (FIG. 2I) input to the clock terminal wck of the asynchronous FIFO circuit 35 is the internal processing clock signal RB2 (FIG. 21) input to the clock terminal rck. 2L), the selection circuit 41 selects the terminal a to align the phases of the image data generated by the image generation circuits 2 and 3 and supply the same to the image synthesis circuit 7. be able to.
[0056]
Next, an operation when the terminal b of the selection circuit 41 is selected will be described with reference to the timing chart of FIG.
[0057]
In a state where the video signal processing circuit 6 is reset, clock signals WA1 to WA5 amplified by the amplifier 11 of the image generation circuit 2 are input to the clock terminal wck of the asynchronous FIFO circuit 31 (FIG. 3B). Clock signals WB1 to WB5 amplified by the amplifier 21 of the image generation circuit 3 are input to the clock terminal wck of the FIFO circuit 35 (FIG. 3I). The clock signal rck of the asynchronous FIFO circuit 31 receives the internal processing clock signals RA1 to RA5 from the amplifier 4 (FIG. 3E), and the clock terminal rck of the asynchronous FIFO circuit 35 receives the internal processing clock signal RB1 from the amplifier 4. To RB5 are input (FIG. 3L).
[0058]
When the reset is released (FIG. 3A), the image data DA1 generated by the image generation circuit 2 based on the first clock signal WA2 immediately after the reset is released is supplied to the data input terminal D2 of the asynchronous FIFO circuit 31. Input is started (FIG. 3C), and a synchronization signal SA indicating the start position of the image data DA1 is input to the synchronization signal input terminal D1 (FIG. 3D). Further, input of the image data DB1 generated based on the first clock signal WB2 immediately after reset release by the image generation circuit 3 is started to the data input terminal D2 of the asynchronous FIFO circuit 35 (FIG. 3J), A synchronization signal SB indicating the start position of the image data DB1 is input to the input terminal D1 (FIG. 3K).
[0059]
Here, the asynchronous FIFO circuit 31 compares the phases of the clock signal WA2 (FIG. 3B) input to the clock terminal wck and the internal processing clock signal RA2 (FIG. 3E) input to the clock terminal rck immediately after the reset is released. As shown in the figure, the start position of the clock signal WA2 is ahead of the start position of the internal processing clock signal RA2. Therefore, as described above, the asynchronous FIFO circuit 31 starts reading after the remaining data amount becomes 2.
[0060]
That is, when the image data DA1 and the image data DA2 are accumulated in the asynchronous FIFO circuit 31 (FIG. 3C), they are read and output from the data output terminal Q2 to the delay circuit 34 (FIG. 3F). Further, a synchronization signal SA indicating the start position of the image data DA1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (FIG. 3G).
[0061]
Similarly, the asynchronous FIFO circuit 35 also compares the phases of the clock signal WB2 (FIG. 3I) input to the clock terminal wck and the internal processing clock signal RB2 (FIG. 3L) input to the clock terminal rck immediately after reset release. As shown in the figure, the start position of the clock signal WB2 is ahead of the start position of the internal processing clock signal RB2. Therefore, as in the case of the above-mentioned asynchronous FIFO circuit 31, reading is started after the remaining data amount becomes 2.
[0062]
That is, when the image data DB1 and the image data DB2 are accumulated in the asynchronous FIFO circuit 35 (FIG. 3J), they are read and output from the data output terminal Q2 to the selection circuit 41 (FIG. 3M). Further, a synchronization signal SB indicating the start position of the image data DB1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (N in FIG. 3).
[0063]
The delay circuit 34 delays the image data input from the asynchronous FIFO circuit 31 by one clock and outputs it to the image generation circuit 7 (FIG. 3H).
[0064]
The phase detection circuit 38 detects a phase difference between the synchronization signal SA (FIG. 3G) input from the asynchronous FIFO circuit 31 and the synchronization signal SB (FIG. 3N) input from the asynchronous FIFO circuit 35, and determines the detection result as a selection circuit 41. To supply. In this case, since the synchronizing signal SA and the synchronizing signal SB have the same phase, the asynchronous FIFO circuits 31 and 35 read image data at the same timing.
[0065]
However, as described above, the image data DA1 whose reading has been started by the asynchronous FIFO circuit 31 is output to the image synthesizing circuit 7 after being delayed by one clock in the delay circuit 34, and thus is the same as that of the asynchronous FIFO circuit 31. The image data DB1 of the asynchronous FIFO circuit 35 whose reading has been started at the timing is output to the image synthesizing circuit 7 one clock earlier than the asynchronous FIFO circuit 31. Accordingly, the selection circuit 41 selects the terminal b, delays the image data DB1 whose reading has been started by the asynchronous FIFO circuit 35 by one clock by the delay circuit 39, and then outputs the image data DB1 to the image synthesis circuit 7 (FIG. 3O). . Accordingly, the image data DA1 output from the asynchronous FIFO circuit 31 and the image data DB1 output from the asynchronous FIFO circuit 35 are input to the image synthesizing circuit 7 with the phases thereof aligned, so that the synthesizing process is easily performed. be able to.
[0066]
As described above, immediately after reset release, the start position of the clock signal WA2 (FIG. 3B) input to the clock terminal wck of the asynchronous FIFO circuit 31 is determined by the internal processing clock signal RA2 (FIG. 3E) input to the clock terminal rck. Of the clock signal WB2 (FIG. 3I) input to the clock terminal wck of the asynchronous FIFO circuit 35, and the internal processing clock signal RB2 (FIG. 3L), the selection circuit 41 selects the terminal b and aligns the phases of the image data generated by the image generation circuits 2 and 3 to supply the same to the image synthesis circuit 7. be able to.
[0067]
Immediately after reset release, the start position of the clock signal WA2 (FIG. 3B) input to the clock terminal wck of the asynchronous FIFO circuit 31 is changed to the start position of the internal processing clock signal RA2 (FIG. 3E) input to the clock terminal rck. And the start position of the clock signal WB2 (FIG. 3I) input to the clock terminal wck of the asynchronous FIFO circuit 35 is different from that of the internal processing clock signal RB2 (FIG. 3L) input to the clock terminal rck. The terminal b is also selected by the selection circuit 41 even when it is later than the start position. Therefore, also in this case, the image data generated by the image generating circuits 2 and 3 can be supplied to the image synthesizing circuit 7 with the phases thereof aligned.
[0068]
Next, an operation when the terminal c of the selection circuit 41 is selected will be described with reference to the timing chart of FIG.
[0069]
In a state where the video signal processing circuit 6 is reset, clock signals WA1 to WA6 amplified by the amplifier 11 of the image generation circuit 2 are input to the clock terminal wck of the asynchronous FIFO circuit 31 (FIG. 4B). Clock signals WB1 to WB6 amplified by the amplifier 21 of the image generation circuit 3 are input to a clock terminal wck of the FIFO circuit 35 (FIG. 4I). The clock signal rck of the asynchronous FIFO circuit 31 receives the internal processing clock signals RA1 to RA6 from the amplifier 4 (FIG. 4E), and the clock terminal rck of the asynchronous FIFO circuit 35 receives the internal processing clock signal RB1 from the amplifier 4. To RB6 are input (FIG. 4L).
[0070]
When the reset is released (FIG. 4A), the image data DA1 generated by the image generation circuit 2 based on the first clock signal WA2 immediately after the reset is released is supplied to the data input terminal D2 of the asynchronous FIFO circuit 31. Input is started (FIG. 4C), and a synchronization signal SA indicating the start position of the image data DA1 is input to the synchronization signal input terminal D1 (FIG. 4D). Further, input of image data DB1 generated by the image generation circuit 3 based on the first clock signal WB2 immediately after reset release is started to the data input terminal D2 of the asynchronous FIFO circuit 35 (FIG. 4J), and the synchronization signal A synchronization signal SB indicating the start position of the image data DB1 is input to the input terminal D1 (FIG. 4K).
[0071]
Here, the asynchronous FIFO circuit 31 compares the phases of the clock signal WA2 (FIG. 4B) input to the clock terminal wck and the internal processing clock signal RA2 (FIG. 4E) input to the clock terminal rck immediately after reset release. As shown in the figure, the start position of the clock signal WA2 is later than the start position of the internal processing clock signal RA2. Therefore, as described above, the asynchronous FIFO circuit 31 starts reading after the remaining data amount becomes three.
[0072]
That is, when the image data DA1 to DA3 are accumulated in the asynchronous FIFO circuit 31 (FIG. 4C), they are read and output from the data output terminal Q2 to the delay circuit 34 (FIG. 4F). Further, a synchronization signal SA indicating the start position of the image data DA1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (FIG. 4G).
[0073]
Similarly, the asynchronous FIFO circuit 35 also compares the phases of the clock signal WB2 (FIG. 3I) input to the clock terminal wck and the internal processing clock signal RB2 (FIG. 3L) input to the clock terminal rck immediately after reset release. As shown in the figure, the start position of the clock signal WB2 is ahead of the start position of the internal processing clock signal RB2. Therefore, as described above, reading is started after the remaining data amount becomes 2.
[0074]
That is, when the image data DB1 and the image data DB2 are accumulated in the asynchronous FIFO circuit 35 (FIG. 4J), they are read and output from the data output terminal Q2 to the selection circuit 41 (FIG. 4M). Further, a synchronization signal SB indicating the start position of the image data DB1 is output from the synchronization signal output terminal Q1 to the phase detection circuit 38 (N in FIG. 4).
[0075]
The delay circuit 34 delays the image data input from the asynchronous FIFO circuit 31 by one clock, and outputs the image data to the image generation circuit 7 (FIG. 4H).
[0076]
The phase detection circuit 38 detects a phase difference between the synchronization signal SA (FIG. 4G) input from the asynchronous FIFO circuit 31 and the synchronization signal SB (FIG. 4N) input from the asynchronous FIFO circuit 35, and determines the detection result as a selection circuit 41. To supply. In this case, since the synchronizing signal SA is delayed by one clock from the synchronizing signal SB, the asynchronous FIFO circuit 31 reads image data with a delay of one clock from the asynchronous FIFO circuit 35.
[0077]
However, as described above, since the image data DA1 whose reading has been started by the asynchronous FIFO circuit 31 is output to the image synthesizing circuit 7 after being delayed by one clock in the delay circuit 34, the asynchronous FIFO circuit 31 The image data DB1 of the asynchronous FIFO circuit 35 whose reading has been started one clock earlier is output to the image synthesizing circuit 7 two clocks earlier than the asynchronous FIFO circuit 31. Accordingly, the selection circuit 41 selects the terminal c, delays the image data DB1 read out by the asynchronous FIFO circuit 35 by one clock by the delay circuit 39, and further delays the image data DB1 by one clock by the delay circuit 40. , To the image synthesizing circuit 7 (FIG. 4O). Accordingly, the image data DA1 output from the asynchronous FIFO circuit 31 and the image data DB1 output from the asynchronous FIFO circuit 35 are input to the image synthesizing circuit 7 with the phases thereof aligned, so that the synthesizing process is easily performed. be able to.
[0078]
As described above, immediately after reset release, the start position of the clock signal WA2 (FIG. 4B) input to the clock terminal wck of the asynchronous FIFO circuit 31 is determined by the internal processing clock signal RA2 (FIG. 4E) input to the clock terminal rck. Of the clock signal WB2 (FIG. 4I) input to the clock terminal wck of the asynchronous FIFO circuit 35, the internal processing clock signal RB2 (FIG. 4L) input to the clock terminal rck. Is selected, the selection circuit 41 selects the terminal c so that the phases of the image data generated by the image generation circuits 2 and 3 are aligned and supplied to the image synthesis circuit 7. it can.
[0079]
In the above, the phase difference between the clock signal WA2 input to the clock terminal wck of the asynchronous FIFO circuit 31 and the internal processing clock signal RA2 input to the clock terminal rck, and the clock signal wck input to the clock terminal wck of the asynchronous FIFO circuit 35 The selection circuit 41 is selected according to a combination of the phase difference between the clock signal WB2 and the internal processing clock signal RB2 input to the clock terminal rck. The size (number) of image data input to the asynchronous FIFO circuits 31 and 35 and the size of image data output from the asynchronous FIFO circuits 31 and 35 are the same. Therefore, the selection circuit 41 can maintain the state where the phases of the image data are aligned without changing the selection after the reset is released (that is, by the circuit selected immediately after the reset is released).
[0080]
However, after a predetermined time has passed since the reset was released, the clock signal was input to the clock terminal wck of the asynchronous FIFO circuit 31 due to the temperature characteristics of the clock buffer of the amplifier 11 of the image generation circuit 2 and the amplifier 21 of the image generation circuit 3. When the phase relationship between the clock signal WA2 and the internal processing clock signal RA2 input to the clock terminal rck is reversed, or the clock signal WB2 input to the clock terminal wck of the asynchronous FIFO circuit 35 and the internal processing input to the clock terminal rck When the phase relationship of the clock signal RB2 is reversed, the number of image data stored in the asynchronous FIFO circuits 31 and 35 changes.
[0081]
For example, at the beginning of the reset, the start position of the clock signal WA2 input to the clock terminal wck of the asynchronous FIFO circuit 31 is advanced from the start position of the internal processing clock signal RA2 input to the clock terminal rck by a predetermined value. Is reversed (the start position of the clock signal WA2 is later than the start position of the internal processing clock signal RA2) after the lapse of time, the image data accumulated in the asynchronous FIFO circuit 31 is reduced by one. .
[0082]
Further, for example, at the beginning of the reset, the start position of the clock signal WA2 input to the clock terminal wck of the asynchronous FIFO circuit 31 is later than the start position of the internal processing clock signal RA2 input to the clock terminal rck. When the clock signal WA2 reverses after a predetermined time has elapsed (when the start position of the clock signal WA2 is advanced compared to the start position of the clock signal RA2), the image data stored in the asynchronous FIFO circuit 31 is increased by one.
[0083]
However, the clock signal WA2 input to the clock terminal wck and the internal processing clock signal RA2 input to the clock terminal rck are both generated from the clock generation circuit 1, and no further fluctuations can occur. It is sufficient for the asynchronous FIFO circuits 31 and 35 to start reading after two image data are accumulated immediately after reset.
[0084]
As described above, the clock skew which is a problem in the video signal processing system operating on the basis of the same oscillator can be solved without using the PLL. Further, in the case of using an LSI having a clock out terminal for data transmission over a plurality of LSIs, the effect can be particularly expected.
[0085]
The above-described series of processing can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer built into dedicated hardware or installing various programs. It is installed in a possible, for example, a general-purpose personal computer from a network or a recording medium.
[0086]
FIG. 5 is a diagram illustrating an example of the internal configuration of a general-purpose computer. A CPU (Central Processing Unit) 101 of the computer executes various processes according to a program stored in a ROM (Read Only Memory) 102 or a program loaded from a storage unit 108 into a RAM (Random Access Memory) 103. The RAM 103 also stores data necessary for the CPU 101 to execute various processes as appropriate.
[0087]
The CPU 101, the ROM 102, and the RAM 103 are mutually connected via a bus 104. The bus 104 is also connected to an input / output interface 105.
[0088]
The input / output interface 105 includes an input unit 106 including buttons, switches, a keyboard, a mouse, and the like, a display such as a CRT (Cathode Ray Tube) and an LCD (Liquid Crystal Display), and a speaker. An output unit 107, a storage unit 108 including a hard disk, and a communication unit 109 including a modem and a terminal adapter are connected. The communication unit 109 performs communication processing via a network including the Internet.
[0089]
A drive 110 is connected to the input / output interface 105 as necessary, and a removable medium 111 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately mounted. Is installed in the storage unit 108.
[0090]
As shown in FIG. 5, a recording medium that is installed in a computer and records a program that can be executed by the computer is provided separately from the main body of the apparatus to provide the program to a user. A recorded magnetic disk (including a flexible disk), an optical disk (including a CD-ROM (Compact Disc-Read Only Memory), a DVD (Digital Versatile Disc)), and a magneto-optical disk (MD (Mini-Disc) (registered trademark) ) Or a removable medium 111 formed of a semiconductor memory or the like, and provided to a user in a state where the program is stored in advance in the apparatus main body. It consists of the storage unit 108, such as.
[0091]
In this specification, the steps of describing a program stored in a program storage medium may be performed in chronological order according to the described order, or may be performed in parallel, even if not necessarily performed in chronological order. Alternatively, it also includes processing executed individually.
[0092]
Also, in this specification, a system represents the entire device including a plurality of devices.
[0093]
【The invention's effect】
As described above, according to the present invention, it is possible to synchronize two digital video signals. In particular, it is possible to construct a video signal processing system in which two digital video signals are synchronized without using a PLL and clock skew which is a problem when operating based on the same oscillator is solved. .
[Brief description of the drawings]
FIG. 1 shows a configuration example of a video signal processing system to which the present invention is applied.
FIG. 2 is a timing chart for explaining a selection operation of a selection circuit.
FIG. 3 is a timing chart for explaining another selection operation of the selection circuit.
FIG. 4 is a timing chart for explaining another selection operation of the selection circuit.
FIG. 5 is a diagram illustrating an example of the internal configuration of a general-purpose computer.
[Explanation of symbols]
Reference Signs List 1 clock generation circuit, 2, 3 image generation circuit, 4 amplifier, 5 reset signal output circuit, 6 video signal processing circuit, 7 image synthesis circuit, 11 and 21 amplifier, 31 asynchronous FIFO circuit, 34 delay circuit, 35 asynchronous FIFO circuit , 38 phase detection circuit, 39, 40 delay circuit, 41 selection circuit

Claims (5)

First input means for inputting first image data generated in synchronization with the first clock signal;
First output means for outputting the first image data together with a synchronization signal of the first image data based on a phase difference between the first clock signal and an internal clock signal;
Second input means for inputting second image data generated in synchronization with the second clock signal;
A second output unit that outputs the second image data together with a synchronization signal of the second image data based on a phase difference between the second clock signal and an internal clock signal;
Detecting means for detecting a phase difference between a synchronization signal of the first image data and a synchronization signal of the second image data;
A video signal processing device comprising: a selection unit that selects a delay amount of the second image data based on a detection result by the detection unit. 2. The video signal processing device according to claim 1, further comprising a delay unit that delays the first image data output by the first output unit. 3. The video signal processing apparatus according to claim 2, wherein the selection unit selects the delay amount for synchronizing the second image data with the first image data delayed by the delay unit. . The video signal processing device according to claim 1, wherein the first and second clock signals and the internal clock signal have the same frequency. A first input step of inputting first image data generated in synchronization with a first clock signal;
A first output step of outputting the first image data together with a synchronization signal of the first image data based on a phase difference between the first clock signal and an internal clock signal;
A second input step of inputting second image data generated in synchronization with a second clock signal;
A second output step of outputting the second image data together with a synchronization signal of the second image data based on a phase difference between the second clock signal and an internal clock signal;
A detection step of detecting a phase difference between a synchronization signal of the first image data and a synchronization signal of the second image data;
A selecting step of selecting a delay amount of the second image data based on a detection result obtained by the processing of the detecting step.

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