JP2004310059A - Circuit element, signal processing circuit, controller, display device, method of driving display device, circuit element, and the controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce electric power consumption by preventing a circuit element in a non-selected state from being affected by a signal supplied to the circuit element in a selected state. <P>SOLUTION: A circuit element 10 comprises a first lead wire 12; a second lead wire 14; a third lead wire 16; first and second rectifying elements D1 and D2 which are respectively connected in series in a forward direction between the first lead wire 12 and the second lead wire 14; and a load 20 which is connected between the third lead wire 16 and a connection point 18 between the first and second rectifying elements D1 and D2. V1≥V2 is set over an entire operating period provided that V1 represents an electric potential of the first lead wires 12, V2 represents an electric potential of the second lead wire 14 and V3 represents a voltage of the connection point 18. V2≤V3≤V1 is set in a period in which a current is blocked and does not flow into the load 20. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention provides a circuit element that can be used for circuits for various applications with a simple configuration, a signal processing circuit including the circuit element, a control device including the circuit element, and a pixel including the circuit element. The present invention relates to an applied display device, a method for driving the display device, a method for driving the circuit element, and a method for driving a control device.

  In general, when a large number of circuit elements are arranged in a matrix and any one of these circuit elements is selectively driven, a passive matrix driving method shown in FIG. 43 or a nonlinear resistance element 1000 shown in FIG. The used active matrix driving method or the like can be considered.

  These driving methods have a configuration in which circuit elements 1004 each having a capacitive load 1002 are arranged in a matrix. In the example of FIG. 43, one terminal of the capacitive load 1002 is connected to the selection line 1006, and the other terminal is connected to the signal line 1008. In the example of FIG. 44, one terminal of the capacitive load 1002 is connected to the selection line 1006 via the nonlinear resistance element 1000, and the other terminal is connected to the signal line 1008.

  A conventional system in which a passive matrix driving method is applied to a display device is described in, for example, Patent Document 1, and a conventional system in which an active matrix driving method is applied to a display device is described in, for example, Patent Document 2.

JP-A-2003-17245 (FIG. 1) JP-A-2002-108310 (FIG. 1)

  By the way, in the method shown in FIG. 43, the circuit element 1004 in the non-selected row is affected by the signal supplied to the circuit element 1004 in the selected row. This leads to an increase in power consumption. In addition, when applied as a display device, since pixels in a non-selected row are affected by signals to the pixels in the selected row, there is no memory effect (accumulation of charge in the capacitive load 1002) in each pixel. It is disadvantageous for high brightness and high contrast.

  In the method shown in FIG. 44, since the non-linear resistance element 1000 has the current-voltage characteristics shown in FIG. 45, the threshold voltage Vth is lower than the hold voltage for holding the voltage (charge accumulation) of the capacitive load 1002. It is necessary to prepare a nonlinear resistance element 1000 having a large value. Therefore, there is a problem that a high driving voltage is required and power consumption is increased.

  In addition, the required characteristics of the nonlinear resistance element 1000 are strict, such as a stable threshold voltage Vth, a steep nonlinear characteristic, and a small capacitance at the time of cutoff, which makes the fabrication difficult.

  In the circuit element 1004 in the non-selected row, the voltage is divided between the capacitance of the non-linear resistance element 1000 and the capacitance of the capacitive load 1002, and the voltage of the capacitive load 1002 decreases. Therefore, a larger charging voltage is required in consideration of the voltage drop at the time of non-selection, and the voltage level to the capacitive load 1002 due to the voltage division varies for each circuit element 1004. There is also a problem that a stable charging voltage cannot be applied.

  The present invention has been made in view of such a problem, and a circuit element in a non-selected state is not affected by a signal supplied to a circuit element in a selected state, and low power consumption is achieved. It is another object of the present invention to provide a circuit element, a signal processing circuit, and a control device which can be driven at a low voltage.

  Another object of the present invention is to realize a memory effect in each pixel without affecting a pixel in a non-selected state by a signal to the pixel in a selected state, thereby achieving high luminance and high contrast. And a method of driving the display device.

  Another object of the present invention is to reduce the power consumption of a circuit element in a non-selected state without being affected by a signal supplied to the circuit element in a selected state. It is an object of the present invention to provide a method for driving a circuit element capable of voltage driving and a method for driving a control device.

  The circuit element according to the present invention includes a first wiring, a second wiring, a third wiring, and a first wiring connected in series in a forward direction between the first wiring and the second wiring. It has a first and a second rectifying element, and a load connected between a connection point of the first and the second rectifying element and the third wiring.

  The present invention is applied to a system in which a plurality of circuit elements are arranged in a matrix. For example, when it is assumed that an arbitrary circuit element is selected / unselected by a signal from a first wiring, a non-selected state is assumed. With respect to the circuit element, the two rectifying elements are reverse biased, and can function to cut off the current. Therefore, a circuit element in a non-selected state is not affected by a signal supplied to a circuit element in a selected state. As a result, low power consumption can be achieved and low-voltage driving can be performed.

  Moreover, since the rectifying element only needs to have a very simple and general function of flowing a current in only one direction, stable characteristics can be easily obtained. Since the rectifier element has a small forward threshold voltage and a small equivalent capacitance in the reverse direction, the voltage applied to the load when it is not selected can be a highly accurate voltage (almost as designed). it can. Even if a rectifying element is inserted, there is almost no need to increase the drive voltage.

  Further, lower voltage driving is possible as compared with a conventional passive matrix driving method or an active matrix driving method using a non-linear resistance element. Further, as compared with a conventional active matrix driving method using a TFT (Thin Film Transistor), the circuit configuration is simple, which is advantageous for cost reduction. Moreover, the present invention can be applied to a case where a higher withstand voltage is required, which is difficult with a conventional TFT.

  When the potential of the first wiring is V1 and the potential of the second wiring is V2, it is preferable that V1 ≧ V2 throughout the entire operation period.

  Further, when a first period in which a current flows from the third wiring to the load is set in the operation period, when the potential of the connection point is V3, V1 < V3 is preferred.

  When a second period in which a current flows from the second wiring to the load is set in the operation period, it is preferable that V2> V3 in the second period.

  When a third period in which conduction to the load is prohibited is set in the operation period, it is preferable that V2 ≦ V3 ≦ V1 in the third period.

  The rectifying element may be a diode. In this case, the diode may be a thin-film diode. The thin film diode may be a MIM (Metal Insulator Metal) element. Further, a rectifying element may be formed using a three-terminal element such as a TFT, a bipolar transistor, or a MOS transistor.

  In particular, when the rectifying element is configured by the MIM element, it is particularly effective when a large number of circuit elements are arranged and integrated, or when a thin circuit element or device is configured. A large number of circuit elements may be formed on a ceramic substrate, a silicon wafer, or the like, or may be formed by connecting a rectifying element formed on those substrates and a load.

  Some element may exist between the first and second rectifying elements without departing from the spirit of the present invention. For example, a resistance element, an inductor, or the like may be inserted and connected for the purpose of protection when a through current occurs due to an abnormal voltage, the purpose of preventing inrush current, or reducing noise. This is between the first wiring and the first rectifier, the second wiring and the second rectifier, the third wiring and the load, the load and the first rectifier, or the load and the second rectifier. May be present.

  Further, when the potential of the second wiring is higher than the potential of the first wiring, a through current may flow and the circuit element may be destroyed. Separately, it is also preferable that elements such as a bypass capacitor, a zener diode, and a varistor are inserted between the first wiring and the second wiring to protect the circuit elements.

  Next, a signal processing circuit according to the present invention is a signal processing circuit having a circuit element and a control circuit, wherein (1) the circuit element includes a first wiring, a second wiring, and a third wiring. A wiring, first and second rectifying elements serially connected in a forward direction between the first wiring and the second wiring, and a connection point between the first and second rectifying elements. A load connected between the third wiring and the third wiring; and (2) the control circuit controls at least a potential of the first wiring and a potential of the second wiring.

  Thus, by using the signal processing circuit according to the present invention, low power consumption can be achieved and a system capable of low voltage driving can be constructed. In this case, it is possible to prepare a large number of circuit elements, arrange these circuit elements arbitrarily, and control the voltage and current of each circuit element.

  Further, the signal processing circuit according to the present invention can be applied to driving a large number of circuit elements arranged in a matrix. In particular, it is suitable for applications that require a current to flow in both directions. It is also suitable for driving a circuit element using a capacitive load as a load. That is, in the case of a capacitive load, the effect of both the feature of allowing a current to flow in both directions and the feature of retaining charges when not selected is high.

  The signal processing circuit according to the present invention is also suitable for a transmission system, for example, when applied to a transmission system that selects an arbitrary bus from a large number of buses and supplies a signal to the selected bus. In this case, it is possible to obtain a transmission system that can smoothly perform switching without using a switching circuit and without generating crosstalk between buses.

  Next, a control device according to the present invention is a control device having a plurality of circuit elements and a control circuit, wherein (1) the circuit element includes a first wiring, a second wiring, and a third wiring. A wiring, first and second rectifying elements serially connected in a forward direction between the first wiring and the second wiring, and a connection point between the first and second rectifying elements. And (2) the control circuit controls potentials of the first wiring, the second wiring, and the third wiring. And

  Thus, by using the control device according to the present invention, low power consumption can be achieved, and a system capable of low voltage driving can be constructed. In this case, it is possible to prepare a large number of circuit elements, arrange these circuit elements arbitrarily, and control the voltage and current of each circuit element.

  Further, the control device according to the present invention can be used for an optical switch, a MEMS (micro electro mechanical system), a memory, a printer, a position control element, a spatial light modulation element, and the like, in addition to a display device described later.

  When the potential of the first wiring is V1 and the potential of the second wiring is V2, it is preferable that V1 ≧ V2 throughout the entire operation period.

  In the operation period, a selection period and a non-selection period are set for each of the circuit elements, and when the potential of the connection point is set to V3, V2 ≦ V3 ≦ V1 is set in the non-selection period. It is preferable to satisfy. It is preferable that V1 <V3 or V2> V3 be satisfied during the selection period.

  Here, the meaning of “satisfiable” will be described. First, the selection period includes a period in which a circuit element is actually in a selected state. The relationship between the period in which the selection state is set and each time length of the selection period is the selection period ≧ the period in which the selection state is set. In this case, the start time of the selection period may be different from the start time of the period to be in the selected state, or the period to be in the selected state may be zero, that is, may not exist at all. The relationship of V1 <V3 or V2> V3, which is a feature of the present invention, indicates the potential relationship during the period of the selection state. That is, if the time length of the selection period and the period of the selection state are the same, it can be defined that V1 <V3 or V2> V3 is satisfied in the selection period, but the period of the selection state is longer than the selection period. If the target length is short or zero, it cannot always be defined that V1 <V3 or V2> V3 is satisfied in the selection period. Therefore, in the present invention, it is defined that "V1 <V3 or V2> V3 can be satisfied during the selection period".

  When a reset period is set for each of the circuit elements during the operation period, it is preferable that V1 <V3 or V2> V3 be satisfied during the reset period. Here, “satisfiable” has the same meaning as described above.

  The load may be a displacement control element that displaces a control target based on a voltage applied to the load. In this case, the displacement control element may have a piezoelectric element, or may have at least a pair of opposing electrodes, and use an electrostatic force that acts when a voltage is applied between the at least one pair of electrodes. You may make it. The displacement control element may include an inductor, and control the displacement of the controlled object by a magnetic force based on a voltage applied to the inductor. The inductor may have a characteristic in which a magnetic flux density-magnetic field characteristic curve has hysteresis, and a saturation magnetic flux density and a residual magnetic flux density are substantially the same.

  Next, the display device according to the present invention includes a display unit having a large number of pixels, a large number of selection lines for instructing selection / non-selection for each pixel, and a pixel for each pixel in a selected state. A plurality of signal lines for supplying signals, and a number of reset lines for supplying a reset signal to each pixel in a selected state, wherein each pixel includes the selection line, the signal line, and the reset line. Of the first and second rectifiers connected in series in the forward direction between any two lines, and between the connection point of the first and second rectifiers and the remaining lines. And a connected load. Here, the reset signal includes a signal for causing the load to perform discharging or charging, and the like, and includes a signal for setting the load to a certain reference state.

  This makes it possible for the two rectifying elements to be reverse-biased for the pixels in the non-selected rows, and to function to cut off the current. Therefore, the pixels in the non-selected row are not affected by the pixel signals supplied to the pixels in the selected row. As a result, low power consumption can be achieved and low-voltage driving can be performed. In addition, it is possible to drive each pixel with a memory effect, and to realize a display device with high luminance and high contrast.

  Of course, as described above, lower voltage driving is possible as compared with the conventional passive matrix driving method and the active matrix driving method using a non-linear resistance element. In addition, compared to the active matrix driving method using a conventional TFT, the circuit configuration is simple, which is advantageous for cost reduction. Applicable.

  Then, of the selection line, the signal line, and the reset line, a line to which a cathode of the first rectifier is connected is defined as a first line, and an anode of the second rectifier is connected. When the line is defined as a second line and the potential of the first line is V1 and the potential of the second line is V2, it is preferable that V1 ≧ V2 over the entire operation period.

  During the operation period, a selection period and a non-selection period are set for each of the pixels, and when the potential of the connection point is set to V3, V2 ≦ V3 ≦ V1 is satisfied during the non-selection period. Is preferred.

  It is preferable that V1 <V3 or V2> V3 be satisfied during the selection period. When a reset period is set for each of the pixels during the operation period, it is preferable that V1 <V3 or V2> V3 can be satisfied during the reset period.

  Next, the driving method of the display device according to the present invention includes a display unit having a large number of pixels, a large number of selection lines for instructing selection / non-selection for each pixel, and A plurality of signal lines that respectively supply pixel signals, and a number of reset lines that respectively supply a reset signal to each pixel in a selected state, wherein each of the pixels includes the selection line, the signal line, First and second rectifiers connected in series in the forward direction between any two of the reset lines, a connection point between the first and second rectifiers, and a remaining line; And a load connected between the select line, the signal line, and the reset line, a line to which a cathode of the first rectifying element is connected to a first line. The anode of the second rectifier element When a connected line is defined as a second line, and the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3, a selected line is selected from among the pixels. The pixels in the state are driven so as to satisfy V1 <V3 or V2> V3, and the pixels in the non-selected state are driven so as to satisfy V2 ≦ V3 ≦ V1.

  Thus, a memory effect in each pixel can be realized without affecting a pixel in a non-selected state by a signal to the pixel in a selected state, and high luminance and high contrast can be achieved.

  Then, a pixel having the following emission characteristics may be used as the pixel. That is, this pixel has a light emission characteristic in which light is emitted during the application period of the second voltage state by applying the first voltage state and the second voltage state to the load.

  In this case, the end point of the second voltage state is changed by modulating the pulse width of the pixel signal supplied to the pixel in accordance with the gradation level of the pixel, so that the light emission luminance of the pixel is changed. You may make it change according to the said gradation level.

  By controlling the amplitude of the pixel signal supplied to the pixel according to the gray level of the pixel, the amplitude of the second voltage state is changed, so that the light emission luminance of the pixel is changed to the gray level. You may make it change according to it.

  By modulating the phase of the trigger signal included in the pixel signal supplied to the pixel according to the gray level of the pixel, the start time of the second voltage state is changed, and the light emission luminance of the pixel is changed. May be changed according to the gradation level.

  By modulating the pulse width of the pixel signal supplied to the pixel in accordance with the gradation level of the pixel, thereby changing the amplitude of the second voltage state, the light emission luminance of the pixel is reduced to the gradation level. May be changed according to the condition.

  Further, when the pixel has a characteristic that a light amount changes in accordance with a duty ratio in a period of the first voltage state with respect to a predetermined period, a phase of a trigger signal included in the pixel signal supplied to the pixel is changed to a predetermined value. The light emission luminance of the pixel may be changed according to the gradation level by changing the pulse width of the first voltage state by modulating according to the gradation level of the pixel.

  When the pixel has a characteristic that a light amount changes according to an accumulation voltage in the first voltage state, a pulse width of the pixel signal supplied to the pixel is modulated according to a gradation level of the pixel. In this case, the luminance of the pixel may be changed according to the gray level by changing the amplitude of the first voltage state.

  Modulating the amplitude of the pixel signal supplied to the pixel according to the gradation level of the pixel, when the pixel has a characteristic in which the amount of light changes according to the accumulated voltage in the first voltage state. By changing the amplitude of the first voltage state, the light emission luminance of the pixel may be changed in accordance with the gradation level.

  In these cases, it is preferable to continuously apply the first voltage state and the second voltage state to the load, since stronger and stable light emission can be obtained.

  Further, a pixel having the following emission characteristics may be used as the pixel. That is, this pixel is configured to apply at least the first voltage state to the load by applying a first voltage state, a reference voltage state, and a second voltage state having a polarity opposite to the first voltage state. Light emission is performed during a state application period and during the second voltage state application period.

  In this case, by modulating the phase of the trigger signal included in the pixel signal supplied to the pixel according to the gray level of the pixel, the start point of the first voltage state and the start point of the second voltage state By changing the time point, the light emission luminance of the pixel may be changed according to the gradation level.

  The amplitude of the first voltage state and the amplitude of the second voltage state are changed by modulating a pulse width of the pixel signal supplied to the pixel in accordance with a gradation level of the pixel, whereby the pixel May be changed according to the gradation level.

  By modulating the amplitude of the pixel signal supplied to the pixel in accordance with the gray level of the pixel, the amplitude of the first voltage state and the amplitude of the second voltage state are changed, so that the The light emission luminance may be changed according to the gradation level.

  Next, a method for driving a circuit element according to the present invention includes a plurality of circuit elements, a plurality of first wirings, a plurality of second wirings, and a plurality of third wirings, And at least one of the second wiring and the second wiring are wirings for instructing selection / non-selection of each circuit element, and each of the circuit elements includes the first wiring and the second wiring. A first and a second rectifying element serially connected in a forward direction between any two of the wiring and the third wiring, and a connection point between the first and the second rectifying elements. A method for driving a circuit element having a load connected between the remaining wirings and the first wiring, the first wiring, the second wiring, and the third wiring. The line to which the cathode is connected is defined as a first line, and the line to which the anode of the second rectifier is connected is defined. 2, the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3. Are driven so that V1 <V3 or V2> V3, and the circuit elements in the non-selected state are driven so that V2 ≦ V3 ≦ V1.

  As a result, low power consumption of the circuit element can be achieved and low-voltage driving can be performed. Therefore, by applying this method of driving circuit elements to various applications, low power consumption and low voltage driving of these applications can be realized.

  Next, the driving method of the control device according to the present invention includes a plurality of circuit elements, a large number of selection lines for instructing selection / non-selection of each circuit element, and a plurality of selection lines. It has a number of signal lines for supplying signals, and a number of reset lines for supplying a reset signal to each circuit element in a selected state. Each of the circuit elements includes the selection line, the signal line and First and second rectifiers connected in series in the forward direction between any two of the reset lines, a connection point between the first and second rectifiers, and a remaining line; And a load connected between the select line, the signal line, and the reset line, wherein a line to which a cathode of the first rectifying element is connected is connected to a first line. The second rectifier element Is defined as a second line, and the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3. The circuit elements in the selected state are driven so as to satisfy V1 <V3 or V2> V3, and the circuit elements in the non-selected state are driven so as to satisfy V2 ≦ V3 ≦ V1.

  In this case, the load may include a piezoelectric element, and the displacement of the control target may be controlled by an inverse piezoelectric effect of the piezoelectric element. Alternatively, at least a pair of opposed electrodes may be provided, and the displacement of the control target may be controlled by an electrostatic force acting when a voltage is applied between the at least one pair of electrodes.

  In addition, the driving method of the control device according to the present invention includes a plurality of circuit elements, wherein each of the circuit elements includes a first wiring for selectively instructing a positive displacement and a first wiring for selectively instructing a negative displacement. A second wiring, a third wiring for indicating a displacement amount, and first and second rectifiers connected in series in a forward direction between the first wiring and the second wiring, respectively. A method for driving a control device, comprising: an element and a load connected between a connection point of the first and second rectifying elements and the third wiring, wherein the potential of the first wiring is V1 Assuming that the potential of the second wiring is V2 and the potential of the connection point of the load is V3, for the circuit element for which the positive displacement is selected and instructed, V1 ≧ V2 and V3> V1 at the displacement start time. The circuit element for which the negative displacement has been selected and instructed to open. Driven so that V1 ≧ V2 and V3 <V2 at the time, for the circuit elements of the non-selected state, and drives so that V2 ≦ V3 ≦ V1.

  In this case, the load may include an inductor, and the displacement of the control target may be controlled by magnetization of the inductor controlled by a current flowing through the inductor by a voltage. The inductor may have a characteristic in which a magnetic flux density-magnetic field characteristic curve has hysteresis, and a saturation magnetic flux density and a residual magnetic flux density are substantially the same. The load may include a piezoelectric element, and the displacement of the control target may be controlled by an inverse piezoelectric effect of the piezoelectric element. Alternatively, the load may include at least a pair of opposed electrodes, and the load may be applied between the at least one pair of electrodes. The displacement of the control target may be controlled by the electrostatic force acting when a voltage is applied to the control object.

  In the driving method of the control device described above, the circuit element in the non-selected state is not affected by the signal supplied to the circuit element in the selected state, and low power consumption can be achieved. Voltage drive becomes possible.

  As described above, according to the circuit element, the signal processing circuit, and the control device of the present invention, the circuit element in the non-selected state is not affected by the signal supplied to the circuit element in the selected state. In addition, low power consumption can be achieved, and low-voltage driving can be achieved.

  Further, according to the display device and the method for driving the display device of the present invention, a memory effect in each pixel can be realized without affecting a pixel in a non-selected state by a signal to the pixel in a selected state. Brightness and high contrast can be achieved.

  According to the method for driving a circuit element and the method for driving a control device according to the present invention, a circuit element in a non-selected state is not affected by a signal supplied to a circuit element in a selected state, so Power consumption can be improved, and low-voltage driving can be performed.

  Hereinafter, embodiments of a circuit element, a signal processing circuit, a control device, a display device, a method of driving a display device, a method of driving a circuit element, and a method of driving a control device according to the present invention will be described with reference to FIGS. I will explain it.

  As shown in FIG. 1, the circuit element 10 according to the present embodiment includes a first wiring 12, a second wiring 14, a third wiring 16, a first wiring 12, and a second wiring 14. And the first and second rectifiers D1 and D2 connected in series in the forward direction, respectively, and between the connection point 18 of the first and second rectifiers D1 and D2 and the third wiring 16. And a load 20 connected thereto.

  Further, the signal processing circuit 30 according to the present embodiment includes one or more circuit elements 10 described above and a control circuit 32, as shown in FIG. In the illustrated example, two circuit elements 10 and one control circuit 32 are shown.

  When the potential of the first wiring 12 is V1 and the potential of the second wiring 14 is V2, the control circuit 32 satisfies V1 ≧ V2 over the entire operation period as shown in FIG. Is controlled.

  The control circuit 32 controls V1 <V3 during a first period in which a current flows from the third wiring 16 to the load 20 during the operation period, and controls the load from the second wiring 14 to the load 20. In the second period in which current flows, control is performed such that V2> V3, and in the third period in which conduction to the load 20 is prohibited, control is performed so that V2 ≦ V3 ≦ V1.

  Here, for example, assuming a case where selection / non-selection of an arbitrary circuit element 10 is performed by a signal from the first wiring 12, the circuit element 10 in the non-selected state is included in the operation period of the above-described operation period. Since the period is 3, the two rectifying elements D1 and D2 are reverse biased, respectively, and can function to cut off the current. Note that the circuit element 10 in the selected state is in the first period or the second period. Therefore, the circuit element 10 in the non-selected state is not affected by the signal supplied to the circuit element 10 in the selected state. Therefore, in the circuit element 10 and the signal processing circuit 30 according to the present embodiment, low power consumption can be achieved and low-voltage driving can be performed.

  In addition, since the rectifying elements D1 and D2 only need to have a very simple and general function of flowing a current in only one direction, stable characteristics can be easily obtained. Since the rectifiers D1 and D2 have a small forward threshold voltage and a small equivalent capacitance in the reverse direction, the voltage applied to the load 20 when not selected is a highly accurate voltage (a voltage almost as designed). Can be Even if the rectifiers D1 and D2 are inserted, there is almost no need to increase the drive voltage.

  Further, lower voltage driving is possible as compared with a conventional passive matrix driving method or an active matrix driving method using a non-linear resistance element. Further, as compared with the conventional active matrix driving method using TFTs, the circuit configuration is simple, which is advantageous for cost reduction. Moreover, the present invention can be applied to a case where a higher withstand voltage is required, which is difficult with a conventional TFT.

  Further, in the signal processing circuit 30 according to the present embodiment, a large number of circuit elements 10 are prepared, and the voltage and current of each circuit element 10 can be controlled by arranging these circuit elements 10 arbitrarily. , Displacement, position, temperature, light, pressure and the like.

  The signal processing circuit 30 is also suitable for a transmission system, for example, when applied to a transmission system that selects an arbitrary bus from a large number of buses and supplies a signal to the selected bus. In this case, it is possible to obtain a transmission system that can smoothly perform switching without using a switching circuit (no noise is generated) and without generating crosstalk between buses.

  The first and second rectifiers D1 and D2 may be diodes. In this case, the diode may be a thin-film diode. The thin film diode may be a MIM element. Further, a rectifying element may be formed using a three-terminal element such as a TFT, a bipolar transistor, or a MOS transistor.

  In particular, when the first and second rectifying elements D1 and D2 are configured by MIM elements, particularly when a large number of circuit elements 10 are arranged and integrated, or when thin circuit elements 10 and devices are configured, It is effective. A large number of circuit elements 10 may be formed on a ceramic substrate, a silicon wafer, or the like, or a circuit in which the first and second rectifying elements D1 and D2 are formed on those substrates and the load 20 are connected. It is also preferable to form them.

  Some element may exist between the first and second rectifying elements D1 and D2 without departing from the spirit of the present invention. For example, a resistance element, an inductor, or the like may be inserted and connected for the purpose of protection when a through current occurs due to an abnormal voltage, the purpose of preventing inrush current, or reducing noise. This is because the first wiring 12 and the first rectifier D1, the second wiring 14 and the second rectifier D2, the third wiring 16 and the load 20, the load 20 and the first rectifier D1 or the load 20. And the second rectifier element D2.

  Also, when the potential of the second wiring 14 becomes higher than the potential of the first wiring 12, a through current may flow and the circuit element 10 may be destroyed. In addition to the element 10, it is also preferable to insert an element such as a bypass capacitor, a zener diode, and a varistor between the first wiring 12 and the second wiring 14 so as to protect the circuit element 10.

  Next, an embodiment in which the circuit element 10 and the signal processing circuit 30 according to the present embodiment are applied to a display device will be described with reference to FIGS. 4 to 29C.

  First, as shown in FIG. 4, the display device 40 </ b> A according to the first embodiment includes a display unit 44 in which a large number of pixels 42 are arranged in a matrix, and a display unit 44 having a number corresponding to the number of rows of the large number of pixels 42. It has a selection line 46, a number of signal lines 48 corresponding to the number of columns of many pixels 42, and a number of reset lines 50 corresponding to the number of columns of many pixels 42.

  The display device 40A has a vertical shift circuit 52, a horizontal shift circuit 54, and a signal control circuit 56.

  The vertical shift circuit 52 selectively supplies the selection signal Ss to the selection line 46, and sequentially selects the pixels 42 in units of one row. The horizontal shift circuit 54 outputs the pixel signal Sd to the signal line 48 in parallel. A common reset signal Sr is supplied to each reset line 50 through a signal control circuit 56.

  The pixel 42 has a connection point between the first and second rectifier elements D1 and D2, which are connected in series in the forward direction between the selection line 46 and the reset line 50, respectively, and the first and second rectifier elements D1 and D2. And a capacitive load 60 connected between the signal line 58 and the signal line 48.

  The relationship between the voltage Vc across the capacitive load 60 and the accumulated charge Q draws a hysteresis curve based on the voltage Vc = 0 (V) as shown in the characteristic of FIG. For example, when the terminal voltage Vc is changed from 100 V to −150 V, the voltage changes in the order of points P 1 → P 2 → P 3, and light emission is performed when the point P 3 is reached. Thereafter, when the voltage Vc between both ends is increased to 100 V, the voltage changes in the order of points P3 → P4 → P1 and returns to the original point P1.

  Here, the driving method of the display device 40A will be described with reference to FIG. 6, taking two-row scanning as an example. FIG. 6 shows a timing chart for the pixels in the first row.

  First, at a time point t0, a selection period Ts1 for the pixels 42 in the first row is entered. At this time, the reset signal Sr changes to a low level (for example, 0 V), the selection signal Ss maintains a high level (for example, 260 V), and the pixel signal Sd maintains a low level (for example, 0 V). The potential Va at the connection point 58 is 100V. This state is a state in which the first and second rectifying elements D1 and D2 are both reverse-biased and non-conductive, and a state in which a positive voltage (for example, 100 V) is applied to both ends of the capacitive load 60 ( (First voltage state) is maintained.

  At the next time point t1, when the pixel signal Sd changes to a high level (for example, 150 V), the potential Va at the connection point 58 rises to 250 V. However, since the selection signal Ss maintains the high level, the capacitive load 60 The terminal voltage Vc does not change.

  At the next time point t2, when the selection signal Ss changes to a low level (for example, 0V), the first rectifying element D1 is forward-biased and becomes conductive, and the potential Va at the connection point 58 drops sharply from 250V to 0V. As a result, the voltage Vc across the capacitive load 60 sharply decreases to -150 V, and light emission is performed by the capacitive load 60 at the same time. This light emitting state is maintained until the pixel signal Sd falls (until time t3). In other words, the capacitive load 60 has a light emission characteristic in which light emission starts at the start of the applied second voltage state Pn and ends at the end of the second voltage state Pn. Therefore, by modulating the pulse width of the pixel signal Sd, particularly the falling timing, according to the gradation level of the pixel 42 in the signal control circuit 56, the light emission luminance corresponding to the gradation level of the pixel 42 is increased. Obtainable.

  At the next time point t3, when the pixel signal Sd changes to a low level (for example, 0 V), the potential Va at the connection point 58 decreases to around -150 V, and accordingly, the second rectifying element D2 conducts, and the capacitance Vc increases. The voltage between both ends of the reactive load 60 becomes 0V.

  At the next time point t4, the reset period Tr1 of the pixel 42 in the first row is entered. At the subsequent time point t5, when the reset signal Sr changes to a high level (for example, 100 V), a time corresponding to the CR time constant of the pixel 42 is obtained. And the voltage Vc across the capacitive load 60 returns to 100V.

  Then, from the next time point t7, the selection period Ts2 of the pixels 42 of the second row and the reset period Tr2 (non-selection period of the pixels of the first row) are entered. In these periods Ts2 and Tr2, the selection signal Ss of the first row is obtained. Maintain the high level, even if the level of the pixel signal Sd changes and the potential Va of the connection point 58 changes, these levels become lower than the high level of the selection signal Ss in the first row. Therefore, a reverse bias is applied to the first and second rectifying elements D1 and D2 relating to the pixels 42 in the first row, and both are kept in a non-conductive state.

  Therefore, the pixels 42 in the first row are not affected by the pixel signal Sd for the pixels 42 in the second row. In the first row non-selection period, electric charge is held in the capacitive load 60 of the pixels 42 in the first row. Is almost zero. It depends only on the parasitic capacitance (<< load capacitance).

  The above-described driving method is particularly preferably used when light emission starts at the start of the second voltage state Pn and ends at the end. In addition, there is an effect even in a case where pulsed light emission characteristics are provided during the application period of the second voltage state Pn. In the case where the peak value and the duration of the pulse-like light emission characteristic change with the voltage value and the time width in the second voltage state Pn, the pulse width is more effectively used.

  When this driving method is applied to, for example, the case of four-row scanning, as shown in FIG. 7, when the display period of one image is one frame, the one frame is divided into four periods, and the first period is divided into four periods. A selection period and a reset period may be set, and a non-selection period (a period in which the selection signal Ss is maintained at a high level) and a reset period may be set in the remaining periods. In the example of FIG. 7, the reset period is inserted and set immediately after the selection period and immediately after the non-selection period in one frame. However, one or more reset periods may be thinned out in one frame.

  The gradation control of the pixel 42 includes a method based on pulse width modulation shown in FIGS. 8A to 8C and a method based on voltage control shown in FIGS. 9A to 9C.

  The pulse width modulation method modulates the pulse width of the pixel signal Sd in accordance with the gray level of the pixel (see FIG. 6), thereby changing the end point of the second voltage state Pn, so that the pixel 42 emits light. The luminance is changed according to the gradation level. In the light output waveform at this time, as shown in FIGS. 8B and 8C, the light output period TL changes according to the pulse width of the pixel signal Sd.

  The voltage control method controls the amplitude of the pixel signal Sd according to the gray level of the pixel, thereby changing the amplitude of the second voltage state Pn as shown in FIG. It is changed according to the gradation level. In the light output waveform at this time, as shown in FIGS. 9B and 9C, the light output level changes according to the amplitude of the pixel signal Sd.

  As described above, in the display device 40A according to the first embodiment, the first and second rectifying elements D1 and D2 are reverse-biased for the pixels 42 in the non-selected rows, respectively, so as to cut off the current. Function. Therefore, the pixels 42 in the non-selected row are not affected by the pixel signal Sd supplied to the pixels 42 in the selected row. As a result, low power consumption can be achieved and low-voltage driving can be performed. In addition, since each pixel 42 can be driven with a memory effect and a certain bias voltage can be applied when the pixel 42 is not selected, a stable operation independent of an image pattern can be performed.

  Of course, as described above, lower voltage driving is possible as compared with the conventional passive matrix driving method and the active matrix driving method using a non-linear resistance element. In addition, compared to the active matrix driving method using a conventional TFT, the circuit configuration is simple, which is advantageous for cost reduction. Applicable.

  Next, a display device 40B according to a second embodiment will be described with reference to FIGS.

  The display device 40B according to the second embodiment has substantially the same configuration as the display device 40A according to the above-described first embodiment, but as shown in FIG. The difference is that wiring is performed by the number corresponding to the number of rows, and the selection line 46 and the reset line 50 are paired. Each reset line 50 is supplied with a reset signal Sr for that row through a vertical shift circuit 52, for example. Further, the configuration of the pixel 42 and the light emission characteristics of the capacitive load 60 are slightly different.

  The pixel 42 has a connection point between the first and second rectifying elements D1 and D2, which are connected in series in the forward direction between the reset line 50 and the signal line 48, respectively, and the first and second rectifying elements D1 and D2. 58 and a capacitive load 60 connected between the select line 46.

  As shown in FIGS. 11A and 11B, the capacitive load 60 starts emitting light at the start of a second voltage state Pn (for example, −10 V) and ends at the end of the second voltage state Pn. And the light emission characteristic is such that the light emission ends.

  Here, the driving method of the display device 40B will be described with reference to FIG. FIG. 12 shows a timing chart for the pixels in the first row.

  First, at a time point t10, a selection period Ts1 of the pixel of the first row is entered. At this time, the reset signal Sr maintains a high level (for example, 140 V), the selection signal Ss changes to a low level (for example, 50 V), and the pixel signal Sd maintains a low level (for example, 0 V). This state is a state in which the first and second rectifying elements D1 and D2 are both reverse-biased and non-conductive, and the potential Va at the connection point 58 becomes the level (0 V) of the pixel signal Sd. A state in which a positive voltage (for example, 50 V) is applied to both ends of the capacitive load 60 is maintained.

  At the next time point t11, when the pixel signal Sd changes to a high level (for example, 60V), the second rectifying element D2 is forward-biased and becomes conductive, and the potential Va at the connection point 58 rises sharply from 0V to 60V. Accordingly, light is emitted from the capacitive load 60 at the same time as the voltage Vc across the capacitive load 60 sharply drops to −10V. This light emitting state is maintained until the reset signal Sr falls (until time t16).

  At the next time point t12, when the pixel signal Sd changes to a low level (0 V), the second rectifying element D2 is again reverse-biased and becomes non-conductive, and the potential Va at the connection point 58 maintains 60 V, The voltage Vc across the capacitive load 60 is also maintained at -10V.

  At the next time point t13, when the selection signal Ss changes to a high level (for example, 120V), the potential Va of the connection point 58 rises to 130V, but since the reset signal Sr maintains the high level, the capacitive load 60 The terminal voltage Vc does not change.

  Then, from the next time point t14, a selection period Ts2 (a non-selection period of the first row) of the pixels 42 of the second row is entered. In the selection period Ts2, the reset signal Sr of the first row is maintained at a high level. Therefore, even if the level of the pixel signal Sd changes, the potential Va at the connection point 58 does not change, and these levels are lower than the high level of the reset signal Sr in the first row. Reverse bias is applied to the first and second rectifying elements D1 and D2 for the pixels 42 in the row, and both are kept in a non-conductive state.

  Therefore, the pixels 42 in the first row are not affected by the pixel signal Sd for the pixels 42 in the second row. Moreover, the power consumed by the capacitive load 60 during the non-selection period is almost zero, and the effect of low power consumption is great. In addition, since the capacitive load 60 keeps holding the electric charge during the non-selection period, the light can be continuously emitted, and the high brightness and the high contrast can be realized. Note that even when the pixels on the first row remain quenched, the potential Va at the connection point 58 remains at 70 V during the selection period Ts2, and the first and second potentials of the pixels 42 on the first row are changed. A reverse bias is applied to the rectifying elements D1 and D2, and the non-conductive state is maintained.

  When the reset period Tr1 of the pixels in the first row starts at time t15 and the selection signal Ss changes to a low level, the potential Va at the connection point 58 drops to 60V. At this time, since the reset signal Sr maintains the high level, the voltage Vc across the capacitive load 60 does not change.

  At the next time point t16, when the reset signal Sr in the first row changes to a low level (for example, 0 V), the first rectifying element D1 is forward-biased and becomes conductive, and the potential Va at the connection point 58 changes from 60V to 0V. It drops sharply. As a result, the voltage Vc across the capacitive load 60 sharply rises to 50 V, and the first reset state is set.

  When this driving method is applied to, for example, four-row scanning, the method shown in FIG. 13A or the method shown in FIG. 13B can be adopted.

  The method shown in FIG. 13A divides one frame into four periods (subfields), and further divides one subfield into four periods. For the first three subfields, a selection period is set for the first period and a non-selection period is set for the remaining three periods for each subfield. For the remaining one subfield, a reset period is set in the first period, and a non-selection period is set in the remaining three periods. This method is suitable for time gradation control.

  On the other hand, in the method shown in FIG. 13B, one frame is divided into eight or more periods, a selection period is set in a first period of each frame, a reset period is set in a final period of each frame, and a remaining period is set. Set the non-selection period. According to this method, the extinction time in the non-selection period after the reset period is eliminated, and there is an effect of improving luminance.

  Note that the system shown in FIG. 13A and the system shown in FIG. 13B may be combined.

  14A to 14C, the pulse width modulation shown in FIGS. 15A to 15C, and the voltage shown in FIGS. 16A to 16C. There is a control method.

  The method based on the phase modulation modulates the phase of the trigger signal Pt included in the pixel signal Sd in accordance with the gray level of the pixel as shown in FIG. 16A, thereby obtaining the second voltage state as shown in FIG. 14B. The start time of Pn is changed. In the light output waveform at this time, as shown in FIG. 14C, the light output period TL changes according to the phase of the trigger signal Pt.

  The pulse width modulation method modulates the pulse width W of the pixel signal Sd according to the gray level of the pixel as shown in FIG. 15A, thereby changing the amplitude of the second voltage state Pn as shown in FIG. 15B. By changing the light emission luminance, the light emission luminance of the pixel is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 15C, the light output level changes according to the pulse width W of the pixel signal Sd.

  The voltage control method is to change the amplitude of the second voltage state Pn as shown in FIG. 16B by controlling the amplitude of the pixel signal Sd according to the gray level of the pixel as shown in FIG. 16A. Then, the light emission luminance of the pixel is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 16C, the light output level changes according to the amplitude of the pixel signal Sd. Note that the polarity of light emission / non-light emission and the second voltage state Pn may be opposite to the above-described example. Further, even in a pixel in which light emission / non-light emission can be controlled without inverting the polarity of the second voltage state Pn, the same effect can be obtained only by appropriately determining the voltage.

  Next, a display device 40C according to a third embodiment will be described with reference to FIGS.

  The display device 40C according to the third embodiment has substantially the same configuration as the display device 40B according to the above-described second embodiment, but has a capacitance instead of the reset line 50 as shown in FIG. The difference is that a discharge instruction line 70 for instructing the discharge of the sexual load 60 is provided in a number corresponding to the number of rows of pixels. Each discharge instruction line 70 is supplied with a discharge instruction signal Sh for the row through, for example, the vertical shift circuit 52. Further, the light emitting characteristics of the capacitive load 60 are slightly different.

  As shown in FIGS. 18 and 19B, this capacitive load 60 has a duty ratio ｛(τ / T) × 100 (%) of an output period τ of the first voltage state Pp with respect to a predetermined period (for example, one frame: T). ) It has the characteristic that the amount of light changes according to｝.

  Therefore, a method based on phase modulation can be easily applied as gradation control. That is, as shown in FIG. 19A, by modulating the phase of the trigger signal Pt included in the pixel signal Sd in accordance with the gray level of the pixel, the start point of the first voltage state Pp as shown in FIG. To change. In the light output waveform at this time, as shown in FIG. 19C, the output level of light output during the discharge period Th of the capacitive load 60 changes according to the phase of the trigger signal Pt.

  As the capacitive load 60, as shown in FIGS. 20 and 21B, a load having a characteristic in which the amount of light changes according to the accumulated voltage Vcs in the first voltage state Pp can be used.

  In this case, a method based on pulse width modulation shown in FIGS. 21A to 21C or a method based on voltage control shown in FIGS. 22A to 22C can be adopted.

  The pulse width modulation method modulates the pulse width W of the pixel signal Sd according to the gray level of the pixel as shown in FIG. 21A, thereby changing the amplitude of the first voltage state Pp as shown in FIG. 21B. By changing the light emission luminance, the light emission luminance of the pixel is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 21C, the output level of light output during the discharge period Th of the capacitive load 60 changes according to the pulse width W of the pixel signal Sd.

  The voltage control method is to change the amplitude of the first voltage state Pp as shown in FIG. 22B by controlling the amplitude of the pixel signal Sd according to the gray level of the pixel as shown in FIG. 22A. Then, the light emission luminance of the pixel is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 22C, the output level of light output during the discharge period Th of the capacitive load 60 changes according to the amplitude of the pixel signal Sd.

  Here, the driving method of the display device 40C will be described with reference to FIG. 23 by taking two-row scanning as an example. FIG. 23 shows a timing chart for the pixels in the first row.

  First, at time t20, the process enters the selection period Ts1 of the pixel in the first row. At this time, the discharge instruction signal Sh maintains a high level (for example, 260 V), the selection signal Ss maintains a high level (for example, 150 V), and the pixel signal Sd changes to a high level (for example, 100 V). In this state, both the first and second rectifying elements D1 and D2 are reverse-biased and are in a non-conductive state, and the potential Va at the connection point 58 becomes the level (150 V) of the selection signal Ss. A state where a reference voltage (for example, 0 V) is applied to both ends of the capacitive load 60 is maintained.

  At the next time point t21, when the selection signal Ss changes to a low level (for example, 0V), the first rectifying element D1 is forward-biased and becomes conductive, and the potential Va at the connection point 58 drops sharply from 150V to 0V. Subsequently, charging with the capacitive load 60 is started, and the potential Va at the connection point 58 gradually increases. This charging is performed until time t22 when the pixel signal Sd becomes low level. At this time point t22, for example, when the capacitive load 60 is charged with 100 V, the first rectifying element D1 is reverse-biased again, becomes non-conductive, and the potential Va at the connection point 58 also becomes 100V. This charged state is maintained until the discharge instruction signal Sh falls (until time t25).

  At the next time point t23, when the selection signal Ss changes to a high level (for example, 150V), the potential Va at the connection point 58 rises to 250V, but since the discharge instruction signal Sh maintains the high level, the capacitive load 60 Does not change.

  Then, from the next time point t24, the pixel enters the selection period Ts2 of the second row. In the selection period Ts2, the level of the pixel signal Sd is changed because the discharge instruction signal Sh of the first row is maintained at a high level. Even if it changes, the potential Va at the connection point 58 does not change, and these levels are lower than or equal to the high level of the discharge instruction signal Sh of the first row. A reverse bias is applied to the second rectifier elements D1 and D2, and both are kept in a non-conductive state.

  Therefore, the pixels 42 in the first row are not affected by the pixel signal Sd for the pixels 42 in the second row. Further, the power consumed by the capacitive load 60 during the non-selection period is almost zero, and the effect of low power consumption is great. Note that even when the pixel signal Sd of the first row remains at 0 V, the potential Va of the connection point 58 becomes 150 V during the selection period Ts2 of the second row, and the first and second pixels related to the pixels of the first row. Reverse bias is applied to the rectifiers D1 and D2, and both are kept in a non-conductive state.

  When the discharge instruction signal Sh of the first row changes to a low level (for example, 0 V) from the time t25 into the discharge period Th of the pixels 42 of the first row, the first rectifying element D1 is forward-biased and becomes conductive, and The potential Va at the connection point 58 drops sharply from 250 V to 0 V. As a result, light is emitted from the capacitive load 60 at the same time as the voltage Vc across the capacitive load 60 drops sharply to -150V. This light emitting state is maintained until the selection signal Ss falls (until time t26).

  At time t26, when the selection signal Ss in the first row changes to a low level (for example, 0 V), the second rectifying element D2 is forward-biased and becomes conductive, and the potential Va at the connection point 58 steeps from 0 V to -150 V. However, since charging with the capacitive load 60 is subsequently started, the potential Va at the connection point 58 gradually increases, and the voltage Vc across the connection point 58 and both ends of the capacitive load 60 becomes 0V.

  When this driving method is applied to, for example, four-row scanning, the above-described method shown in FIG. 13A or the method shown in FIG. 13B can be adopted.

  Next, a display device 40D according to a fourth embodiment will be described with reference to FIG.

  The display device 40D according to the fourth embodiment has substantially the same configuration as the display device 40B according to the above-described second embodiment, but differs in the following points.

  That is, the pixel 42 includes first and second rectifying elements D1 and D2 connected in series in the forward direction between the first line 80 and the second line 82, respectively, and the first and second rectifying elements. It has a capacitive load 60 connected between the connection point 58 of D1 and D2 and the signal line 48.

  As shown in FIG. 25 and FIGS. 27A to 27C, one frame is divided into two fields (first and second fields F1 and F2), and the first field F1 and the second field F2 Is controlled so that the pixel signal Sd is logically inverted.

  For example, as shown in FIG. 27B and FIG. 27C, in the first field F1, light emission is performed during the period when the second voltage state Pn is applied to the capacitive load 60, and in the second field F2, the light is emitted. Control is performed such that light emission is performed during a period in which the first voltage state Pp is applied to the load 60.

  Therefore, in the first field F1, the first line 80 functions as a selection line, and the second line 82 functions as a reset line. Conversely, in the second field F2, the first line 80 functions as a reset line, and the second line 82 functions as a selection line. Therefore, in the following description, the signal transmitted on the first line 80 is referred to as a first signal S1, and the signal transmitted on the second line 82 is referred to as a second signal S2.

  Here, the driving method of the display device 40D will be described with reference to FIG. 25 by taking two-row scanning as an example. FIG. 25 is a timing chart for the pixels in the first row.

  First, at time t30, the pixel enters a selection period Ts11 of a pixel in the first row in the first field F1. At this time, the first signal S1 changes to a low level (for example, 0 V), the second signal S2 maintains a low level (for example, -110 V), and the pixel signal Sd maintains a low level (for example, 0 V). I have. This state is a state in which the first and second rectifying elements D1 and D2 are both reverse-biased and non-conductive, and the potential Va at the connection point 58 becomes the level (0 V) of the pixel signal Sd. A state in which 0 V is applied to both ends of the capacitive load 60 is maintained.

  At the next time point t31, when the pixel signal Sd changes to a high level (for example, 100V), the first rectifying element D1 is forward-biased and becomes conductive, and the voltage Vc across the capacitive load 60 drops sharply to -100V. At the same time, light is emitted from the capacitive load 60. This light emitting state is maintained until the second signal S2 rises (until time t36).

  At the next time point t32, when the pixel signal Sd changes to a low level (0 V), the first rectifying element D1 is again reverse-biased and becomes non-conductive, and the potential Va at the connection point 58 changes to the capacitive load 60. It becomes -100 V, which is the same as the voltage Vc between both ends.

  Next, at time t33, the first signal S1 changes to a high level (for example, 210 V). This is to prevent the pixel signal Sd to the pixels 42 in the second row from affecting the pixels 42 in the first row in the next selection period Ts12 of the second row (non-selection period of the first row). Preparation processing.

  Then, the pixel enters a selection period Ts12 (non-selection period of the first row) of the pixels in the second row from the next time point t34. In the selection period Ts12, the first signal S1 in the first row maintains a high level. Therefore, even if the level of the pixel signal Sd changes and the potential Va of the connection point 58 changes, these levels are lower than the high level of the first signal S1 in the first row. Reverse bias is applied to the first and second rectifying elements D1 and D2 for the pixels 42 in the row, and both are kept in a non-conductive state.

  Therefore, the pixels 42 in the first row are not affected by the pixel signal Sd for the pixels 42 in the second row. Moreover, the power consumed by the capacitive load 60 during the non-selection period is almost zero, and the effect of low power consumption is great. In addition, since the capacitive load 60 keeps holding the electric charge during the non-selection period, the light can be continuously emitted, and the high brightness and the high contrast can be realized.

  When the reset period Tr11 of the pixels 42 in the first row enters the time period t35 and the pixel signal Sd changes to a high level (for example, 100 V), the potential Va at the connection point 58 increases to 0V. At this time, since the first signal S1 is maintained at a high level, the voltage Vc across the capacitive load 60 does not change.

  At the next time point t36, when the second signal S2 in the first row changes to a high level (for example, 100V), the second rectifying element D2 is forward-biased and becomes conductive, and the potential Va at the connection point 58 changes from 0V. It rises sharply to 100V. As a result, the voltage Vc across the capacitive load 60 sharply rises to 0 V, and the first reset state is set.

  At the next time point t37, when the second signal S2 in the first row changes to a low level (for example, −110 V), the second rectifying element D2 is reverse-biased again to be in a non-conductive state. The potential Va is maintained at 100V, and the voltage Vc across the capacitive load 60 is also maintained at 0V.

  After a reset period Tr12 for the pixels 42 in the next second row, at the next time point t38, a selection period Ts21 for the pixels 42 in the first row in the second field F2 is entered. At this time, the first signal S1 maintains a high level (for example, 210 V), the second signal S2 changes to a high level (for example, 100 V), and the pixel signal Sd maintains a high level (for example, 100 V). . In this state, the first and second rectifying elements D1 and D2 are both reverse-biased and are in a non-conductive state, and the potential Va at the connection point 58 becomes the level (100 V) of the pixel signal Sd. A state in which 0 V is applied to both ends of the capacitive load 60 is maintained.

  At the next time point t39, when the pixel signal Sd changes to a low level (for example, 0V), the second rectifying element D2 is forward-biased and becomes conductive, and when the voltage Vc across the capacitive load 60 sharply rises to 100V. At the same time, light is emitted from the capacitive load 60. This light emitting state is maintained until the first signal S1 falls (until time t44).

  At the next time point t40, when the pixel signal Sd changes to a high level (100 V), the second rectifying element D2 is again reverse-biased and becomes non-conductive, and the potential Va at the connection point 58 changes to the capacitive load 60. Becomes 200V, which is the same as the voltage obtained by adding the voltage of the pixel signal Sd to the voltage Vc across the terminal.

  At the next time point t41, the second signal S2 changes to a low level (for example, -110 V).

  Then, a selection period Ts22 (non-selection period of the first row) of the pixels of the second row is entered from the next time point t42. In the selection period Ts22, the first signal S1 of the first row is maintained at a high level. Therefore, even if the level of the pixel signal Sd changes and the potential Va of the connection point 58 changes, these levels are lower than the high level of the first signal S1 in the first row. Reverse bias is applied to the first and second rectifying elements D1 and D2 for the pixels 42 in the row, and both are kept in a non-conductive state.

  Therefore, the pixels 42 in the first row are not affected by the pixel signal Sd for the pixels 42 in the second row.

  When the reset period Tr21 of the pixel 42 in the first row enters from the time point t43 and the pixel signal Sd changes to a low level (for example, 0V), the potential Va of the connection point 58 drops to 100V. At this time, since the first signal S1 is maintained at a high level, the voltage Vc across the capacitive load 60 does not change.

  At the next time point t44, when the first signal S1 in the first row changes to a low level (for example, 0V), the first rectifying element D1 is forward-biased and becomes conductive, and the potential Va at the connection point 58 changes from 100V. It drops sharply to 0V. As a result, the voltage Vc across the capacitive load 60 drops sharply to 0 V, and a first reset state is set.

  At the next time point t45, when the first signal S1 in the first row changes to a high level (for example, 210 V), the first rectifying element D1 is reverse-biased again and becomes non-conductive, and the potential at the connection point 58 is changed. Va is maintained at 0V, and the voltage Vc across the capacitive load 60 is also maintained at 0V.

  When this driving method is applied to, for example, four-row scanning, the method shown in FIG. 26A or the method shown in FIG. 26B can be adopted.

  The method shown in FIG. 26A divides each of the first field F1 and the second field F2 into four periods (subfields), and further divides one subfield into four periods. In the first three subfields, for each subfield, a selection period is set in the first period, and a non-selection period is set in the remaining three periods. For the remaining subfields, a reset period is set in the first period, and a non-selection period is set in the remaining three periods. The second field F2 is set similarly. This method is suitable for time gradation control.

  On the other hand, the method shown in FIG. 26B divides each of the first field F1 and the second field F2 into eight or more periods. For example, in the first field F1, a selection period is set in the first period, a reset period is set in the last period of each frame, and a non-selection period is set in the remaining periods. The second field F2 is set similarly. According to this method, the extinction time in the non-selection period after the reset period is eliminated, and there is an effect of improving luminance.

  The method shown in FIG. 26A and the method shown in FIG. 26B may be combined.

  As the gradation control of the pixel, a method based on phase modulation (time gradation control) shown in FIGS. 27A to 27C, a method based on pulse width modulation shown in FIGS. 28A to 28C, and a voltage shown in FIGS. 29A to 29C are used. There is a control method.

  As shown in FIG. 27A, the phase modulation method modulates the phases of the positive trigger signal Pt1 and the negative trigger signal Pt2 included in the pixel signal Sd according to the gray level of the pixel. As shown in (1), the start point of the second voltage state Pn and the start point of the first voltage state Pp are changed. In the light output waveform at this time, as shown in FIG. 27C, the light output period changes according to the phases of the trigger signals Pt1 and Pt2.

  The pulse width modulation method modulates the pulse widths W1 and W2 of the pixel signal Sd in accordance with the gray level of the pixel as shown in FIG. 28A, and thereby, as shown in FIG. By changing the amplitude of the first voltage state Pp, the light emission luminance of the pixel is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 28C, the light output level changes according to the pulse width.

  The voltage control method controls the amplitude of the pixel signal Sd according to the gray level of the pixel as shown in FIG. 29A, and thereby the second voltage state Pn and the first voltage state as shown in FIG. 29B. By changing the amplitude of Pp, the light emission luminance of the pixel 42 is changed according to the gradation level. In the light output waveform at this time, as shown in FIG. 29C, the light output level changes according to the amplitude of the pixel signal Sd.

  In this voltage control method, when the ON level of the pixel signal Sd is, for example, 80 V and the OFF level is 0 V in the first field F1, it is logically inverted in the second field F2, and the ON level of the pixel signal Sd is changed, for example. Arbitrary gradations can be expressed, for example, 20 V and the OFF level is 100 V.

  In particular, in the display device 40D according to the fourth embodiment, when the second voltage state Pn is applied to the capacitive load 60 in the first field F1 to emit light, the second signal S2 is changed to the second signal S2. The light emission is maintained until it becomes a high level. Further, in the second field F2, when the first voltage state Pp is applied to the capacitive load 60 and light emission is performed, the first signal S1 becomes low. The light emission is maintained until it becomes. That is, a memory effect can be provided in the two fields F1 and F2.

  Therefore, it is more advantageous in achieving high luminance. Further, even when the light emission changes according to the effective value of the voltage, the dynamic range of the effective value can be widened, and higher luminance and higher contrast can be achieved. In addition, a liquid crystal cell can be preferably used as the capacitive load. In addition, since the voltage for obtaining the same effective value can be reduced, the voltage can be reduced. That is, in the matrix driving, a predetermined voltage is applied to each pixel while performing row scanning. However, in order to obtain a predetermined effective value only during a selection period of a row to which the pixel is connected, it is necessary to apply a predetermined voltage to the pixel. A high voltage is required as the voltage. On the other hand, in the display devices 40A to 40D according to the first to fourth embodiments, not only the row selection period but also the pixel keeps holding the voltage during the non-selection state. There is an advantage that the applied voltage (absolute value) can be small to obtain.

  The absolute value of the voltage value and the pulse width can be set to the same value for the first voltage and the second voltage, as described above, or it is easy to set different values and pulse widths. In other words, it is only necessary to control the pixel signal Sd in the first field F1 and the second field F2 so that they are logically inverted, as separate signals.

  In the display device 40B according to the second embodiment and the display device 40D according to the fourth embodiment described above, a resistor is connected in parallel to the capacitive load 60, and the electric charge charged in the capacitive load 60 at the time of selection. May be discharged through a resistor when not selected.

  In this case, the time constant of the capacitive load 60 and the resistance is appropriately set, and the discharge time is used effectively. For example, in the liquid crystal display element, the voltage is discharged during the non-selection period to return to zero, and the light transmittance also returns to the original value. In the above-described example, the time average value of the light transmittance charges during the selection period. Since control is possible by voltage (or by the number of times of charging during the selection period), gradation expression is possible. Moreover, there is an advantage that the charge charged in the capacitive load 60 can be returned to zero without providing a reset period.

  In the case of controlling displacement using a piezoelectric material, for example, the displacement-voltage characteristic has hysteresis, the displacement is generated by applying a voltage, and then the displacement is maintained even when the voltage is returned to zero. It is also effective in the case where it is done. Further, for example, in a liquid crystal display element, the present invention is also effective in a case where a voltage is applied to lower the light transmittance, and then the state where the light transmittance is lowered is maintained even when the voltage is returned to zero.

  Further, in the display devices 40A to 40D according to the first to fourth embodiments, a voltage can be alternately applied to the pixels. It is effectively used when it is desired to eliminate the DC component from the voltage applied to the pixel regardless of the image pattern. It is particularly preferably used for a display element utilizing an AC drive system, and is particularly suitable for a liquid crystal display element and an electroluminescence display element.

  Next, an embodiment in which the circuit element 10 and the signal processing circuit 30 according to the present embodiment are applied to a position control system device will be described with reference to FIGS. 30 to 35B.

  As shown in FIG. 30, the circuit element 10 of the position control device 90 according to this embodiment includes first and second serially connected first lines 80 and a second line 82 in the forward direction. 2 rectifiers D1 and D2, and a load 92 connected between the connection point 58 of the first and second rectifiers D1 and D2 and the signal line 48. The load 92 has a configuration in which an inductor 94 and a resistor 96 are connected in series.

  FIG. 31 shows a model 98 of a position control system composed of an inductor 94 and a resistor 96. This model shows that the position P of the control target 102 connected from the ceiling via the spring 100 is controlled by the magnetic field generated by the current i flowing through the inductor 94. That is, as shown in FIG. 32, the position P can be changed in the positive direction (upward) and the negative direction (downward) depending on the magnitude and direction of the current i flowing through the inductor 94. That is, at least the inductor 94 functions as a displacement control element to be controlled.

  The current i flowing through the inductor is determined by the voltage Vc across the load 92 and the resistance R. Except for the transient state, the voltage Vc is Vc = Ri.

  In the position control device 90, as shown in FIG. 33, for example, the selection period Ts1 of the circuit element 10 in the first row is divided into two periods (a positive direction period Ts1p and a negative direction period Ts1n), and the control object 102 is controlled. Is moved in the positive direction, the control target 102 is driven in the positive direction period Ts1p, and if the control target 102 is moved in the negative direction, the control target 102 is driven in the negative direction period Ts1n.

  Here, the driving method of the position control device 90 will be described with reference to FIGS. 33 and 34, taking two-row scanning as an example. The waveforms in FIGS. 33 and 34 are timing charts relating to the circuit elements 10 in the first row. In particular, FIG. 33 shows a timing chart when the control target is driven to be displaced in the positive direction. 4 shows a timing chart when a control target is driven to be displaced in a negative direction.

  First, at time t60 in FIG. 33, the operation enters the positive direction period Ts1p in the selection period Ts1 of the circuit element 10 in the first row. At this time, the first signal S1 maintains a high level (for example, 10 V), the second signal S2 maintains a low level (for example, 0 V), and the data signal SD maintains a high level (for example, 10 V). . In this state, the first and second rectifying elements D1 and D2 are both reverse-biased and are in a non-conductive state, and the potential Va at the connection point 58 becomes the same as the level (10 V) of the data signal SD. As a result, the voltage Vc across the load 92 is maintained at 0V.

  At the next time point t61, when the first signal S1 changes to a low level (for example, 0V), the first rectifying element D1 is forward-biased and becomes conductive, and when the potential Va of the connection point 58 drops sharply to 0V. At the same time, the voltage Vc across the load 92 sharply rises to a high level (for example, 10 V), whereby a current flows in the inductor 94 in the positive direction, and the control target 102 moves in the positive direction.

  At the next time point t62, when the first signal S1 changes to a high level (for example, 10 V), the first rectifying element D1 is reverse-biased again and becomes non-conductive, and the potential Va of the connection point 58 steeply reaches 10V. At the same time, the voltage Vc across the load 92 sharply drops to a low level (for example, 0 V), and the control target 102 moves toward the original position (zero point).

  At the next time point t63, the operation enters the negative direction period Ts1n of the circuit element 10 in the first row. In this period Ts1n, since the data signal SD maintains the high level (for example, 10 V), even if the second signal S2 changes to the high level (for example, 10 V) at the subsequent time point t64, the first signal and the second signal S2 change to the high level (for example, 10 V). Both the second rectifiers D1 and D2 remain non-conductive, and the voltage Vc across the load 92 is maintained at 0V. That is, the control target 102 remains stopped at the zero point.

  At the next time point t65, the selection period Ts2 (non-selection period of the first row) of the circuit element 10 of the second row is entered. In the selection period Ts2, the first signal S1 of the first row is maintained at a high level. Therefore, even if the level of the data signal SD changes and the potential Va of the connection point 58 changes, these levels are lower than the high level of the first signal S1 in the first row. The first and second rectifying elements D1 and D2 related to the circuit elements 10 in the first row are both kept in a non-conductive state.

  Therefore, the circuit elements 10 in the first row are not affected by the data signal SD for the circuit elements 10 in the second row. In addition, the current i flowing to the load 92 during the non-selection period is almost zero, and the power consumption can be reduced.

  Next, in the displacement control in the negative direction, first, at a time point t70 in FIG. 34, a selection period Ts1 of the circuit element 10 in the first row is entered. At this time point t70, the first signal S1 maintains a high level (for example, 10 V), the second signal S2 maintains a low level (for example, 0 V), and the data signal SD changes to a low level (for example, 0 V). . At this time, since the first and second rectifying elements D1 and D2 are both in a non-conductive state, the potential Va at the connection point drops sharply to 0V. As a result, the voltage Vc across the load 92 is maintained at 0V.

  At the next time point t71, even if the first signal S1 changes to a low level (for example, 0V), the potential Va at the connection point is still maintained at 0V, so that the voltage Vc across the load 92 is 0V. Will be maintained.

  At the next time point t72, when the first signal S1 changes to a high level, the first rectifying element D1 is reverse-biased and becomes non-conductive, the potential Va at the connection point is still maintained at 0 V, and the voltage across the load 92 is maintained. Vc is maintained at 0V.

  At the next time point t73, the negative direction period Ts1n of the circuit element 10 on the first row is entered. At the subsequent time point t74, when the second signal S2 changes to a high level (for example, 10 V), the second rectifier element D2 becomes conductive. In this state, the potential Va at the connection point 58 rises sharply to 10 V, and at the same time, the voltage Vc across the load 92 drops sharply to a low level (for example, −10 V), whereby a current flows in the inductor 94 in the negative direction. , The control target 102 moves in the negative direction.

  At the next time point t75, when the second signal S2 changes to a low level (for example, 0 V), the second rectifying element D2 is reverse-biased again and becomes non-conductive, and the potential Va of the connection point 58 steeply reaches 0V. Simultaneously, the voltage Vc across the load 92 sharply rises to a high level (for example, 0 V), and the control target 102 moves toward the original position (zero point).

  At the next time point t76, the selection period Ts2 (the non-selection period of the first row) of the circuit element 10 of the second row is entered. In the selection period Ts2, the first signal S1 of the first row maintains a high level. Therefore, even if the level of the data signal SD changes and the potential Va of the connection point 58 changes, these levels are lower than the high level of the first signal S1 in the first row. The first and second rectifying elements D1 and D2 related to the circuit elements 10 in the first row are both kept in a non-conductive state.

  Therefore, the circuit elements 10 in the first row are not affected by the data signal SD for the circuit elements 10 in the second row. In addition, the current i flowing to the load 92 during the non-selection period is almost zero, and the power consumption can be reduced.

  When this driving method is applied to, for example, the case of four-row scanning, the method shown in FIG. 35A or the method shown in FIG. 35B can be adopted.

  In the method shown in FIG. 35A, when the period in which the position control is completed for all four rows of circuit elements 10 is defined as one frame, the one frame is divided into four periods, and further, the positive direction is defined in the first period. A period and a negative direction period are set, and a non-selection period is set for the remaining three periods.

  On the other hand, the method shown in FIG. 35B separates one frame into two periods (first and second fields F1 and F2), and further separates the first and second fields F1 and F2 into four periods. I do. Then, for the first field F1, a forward period is set in the first period, and a non-selection period is set in the remaining three periods. For the second field F2, a negative direction period is set in the first period, and a non-selection period is set in the remaining three periods.

  As the position control of the control target 102, a method based on voltage control is preferably adopted. For example, when the control target 102 is moved in the positive direction to a position where the voltage Vc across the load 92 corresponds to 10 V, the level of the first signal S1 is set to 0 V and the level of the data signal SD is set to 10 V in the positive direction period. With this setting, as shown in FIG. 36A, the voltage Vc across the load 92 can be set to 10 V in the positive direction.

  On the other hand, when the control target 102 is moved in the negative direction to the position where the voltage Vc across the load 92 corresponds to 8 V, the level of the second signal S2 is set to 10 V and the level of the data signal SD is set to 2 V in the negative direction period. By setting, as shown in FIG. 36B, the voltage Vc across the load 92 can be set to 8 V in the negative direction (that is, −8 V).

  In the above-described example, as shown in FIG. 32, the case where the current-position characteristic changes linearly is shown. However, a characteristic that draws a hysteresis curve based on the current i = 0 may be used. For example, the present invention is effective when the magnetized coil has a residual magnetization even if the current is returned to zero. In this case, after moving to a predetermined position by the current flowing in the selection period, when the current becomes zero in the non-selection period, the predetermined position can be substantially held by the residual magnetization.

  Next, for example, as a displacement control element, displacement control and position control can be performed by using, as a capacitive load, an element having characteristics similar to the displacement-voltage characteristics of the piezoelectric element shown in, for example, FIGS.

  In the piezoelectric element having the displacement-voltage characteristic of FIG. 37, for example, by using a portion indicated by a line segment connecting points a and c, or by using a portion indicated by a line segment connecting points d and e, A substantially linear voltage-displacement characteristic can be obtained, and control becomes easy. In the piezoelectric element having the displacement-voltage characteristic shown in FIG. 38, the change in the amount of elongation with respect to the change in voltage is different from the change in the amount of contraction with respect to the change in voltage, and the voltage-displacement characteristic has hysteresis. Therefore, it is advantageous when performing a cam operation.

  As an example of a device using a displacement control element having characteristics similar to the displacement-voltage characteristics of the piezoelectric element shown in FIGS. 37 and 38, as shown in FIG. 39, a plurality of optical waveguides 110a to 110e are vertically arranged. An optical switch array 116 in which a plurality of optical waveguides 112a to 112d are arranged side by side and an optical switch 114 is arranged at each intersection. In the optical switch array 116, light 118a to 118e is respectively incident on a plurality of optical waveguides 110a to 110e arranged in the vertical direction, and light is emitted from some of the optical waveguides 112a to 112d arranged in the vertical direction. Here is an example. In FIG. 39, the light 118a incident on the optical waveguide 110a in the first row is emitted from the optical waveguide 112b in the second column, the light 118b incident on the optical waveguide 110b in the second row is emitted in the horizontal direction as it is, Light 118c incident on the third-row optical waveguide 110c is emitted from the first-row optical waveguide 112a, light 118d incident on the fourth-row optical waveguide 110d is emitted from the third-row optical waveguide 112c, An example is shown in which light 118e incident on the optical waveguide 110e in the fifth row is emitted from the optical waveguide 112d in the fourth column. In FIG. 39, ○ indicates that the optical switch 114 is in the first state (114a) and guides the incident light in the horizontal direction, and ● indicates that the optical switch 114 is in the second state. (114b) shows a state where incident light is guided in the vertical direction.

  To realize the first state (114a), as shown in FIG. 40A, a reflecting plate 120 connected to a displacement control element (not shown) is connected to an optical waveguide 110 extending in a row direction and an optical waveguide 110 extending in a column direction. The second state (114b) can be realized by inserting the reflector 120 connected to the displacement control element into the intersection 122 with the wave path 112, as shown in FIG. 40B. 122 may be inserted.

  The driving method of the displacement control element can be easily realized by the same driving method as the display devices 40A to 40D according to the above-described first to fourth embodiments.

  In order to control the displacement, in addition to the above-described piezoelectric material, a method in which a pair of electrodes are opposed to each other and a distance between the electrodes is changed by an electrostatic force acting when a voltage is applied between the electrodes may be used. .

  Next, a method of driving a displacement control element using a coil having a BH characteristic having a large residual magnetic flux (a large hysteresis) as shown in FIG. 41 will be described. A large residual magnetic flux indicates that the BH curve has a hysteresis and that the saturation magnetic flux density and the residual magnetic flux density are substantially the same. The circuit configuration of the position control device having this displacement control element has almost the same configuration as the configuration shown in FIG.

  First, in the BH curve shown in FIG. 41, the magnetic field (H) corresponds to the current i flowing through the coil, and the magnetic flux density (B) corresponds to the amount of displacement of the control object. To obtain a magnetic flux density, the voltage level is set so that the current at point e flows during the selection period. In this case, the operating point of the displacement control element moves to the point E. When the current is cut off during the non-selection period, the operating point moves to the point F. That is, the control target is displaced to a position corresponding to the residual magnetic flux density shown at the point F.

  The drive voltage may be applied to the displacement control element alternately, and for example, point F and point H whose polarity is inverted may be used as a pair. Alternatively, a drive voltage having a different voltage level between positive and negative is applied, and for example, the negative polarity side is controlled to be in a reset state so as to always pass through the point D and pass through the point B, F or J on the positive polarity side. You may.

  Here, an example of a method of driving the circuit element 10 including the displacement control element using the coil having the BH characteristic shown in FIG. 41 will be described with reference to FIG.

  In this driving method, as shown in FIG. 42, for example, the selection period of the first row of circuit elements 10 and the positive direction period Ts1p arrives, and then, for example, the selection period of the second row of circuit elements 10 And the positive direction period Ts2p (the non-selection period Ts1u of the circuit elements 10 in the first row) is followed by the selection period of the circuit elements 10 in the first row and the negative direction period Ts1n. After that, for example, it is a selection period of the circuit elements in the second row and a negative direction period Ts2n (non-selection period Ts1u of the circuit elements 10 in the first row).

  First, at time t80 in FIG. 42, the operation enters the positive direction period Ts1p of the circuit element 10 in the first row. At this time, the first signal S1 maintains a low level (for example, 0 V), the second signal S2 also maintains a low level (for example, 0 V), and the data signal SD also maintains a low level (for example, 0 V). . In this state, the first and second rectifying elements D1 and D2 are both in a non-conductive state, and the potential Va at the connection point 58 is the same as the level (0 V) of the data signal SD as shown in FIG. become. As a result, the voltage across the load 92 is maintained at 0V.

  At the next time point t81, when the data signal SD changes to a high level (for example, 10 V), the first rectifying element D1 is forward-biased and becomes conductive, and the voltage Vc across the load 92 sharply reaches a high level (for example, 10 V). As a result, a current flows in the inductor 94 in the positive direction, and the control target 102 moves in the positive direction. For example, it moves to a position in the positive direction corresponding to the magnetic flux density shown at point A in FIG. At this time, the potential Va at the connection point maintains 0V.

  At the next time point t82, when the data signal SD changes to a low level (for example, 0V), the first rectifying element D1 is again reverse-biased and becomes non-conductive, and the voltage Vc across the load 92 becomes low (for example, 0V). The control target is stopped at a position corresponding to the residual magnetic flux density shown at point B in FIG.

  At the next time point t83, it enters the positive direction period Ts2p of the circuit element 10 in the second row (non-selection period Ts1u of the circuit element in the first row). At this time, the first signal S1 changes to a high level (for example, 10 V). Therefore, in the positive direction period Ts2p, even if the level of the data signal SD changes and the potential Va of the connection point 58 changes, these levels are lower than the high level of the first signal S1 in the first row. In addition, since the second signal S2 in the first row is equal to or higher than the low level, both the first and second rectifiers D1 and D2 related to the circuit element 10 in the first row are maintained in a non-conductive state. . That is, the control target 102 is stopped at a position corresponding to the residual magnetic flux density indicated by the point B in FIG.

  At the next time point t84, the operation enters the negative direction period Ts1n of the circuit element 10 in the first row. At this time, the first signal S1 maintains a high level, the second signal S2 changes to a high level (for example, 10 V), and the data signal SD changes to a high level (for example, 10 V). In this case, the potential Va at the connection point 58 becomes the same as the level (10 V) of the data signal SD, and both the first and second rectifying elements D1 and D2 relating to the circuit elements 10 in the first row are in a non-conductive state. Will be maintained. That is, the control target is stopped at a position corresponding to the residual magnetic flux density shown at point B in FIG.

  At the next time point t85, when the data signal SD changes to a low level (for example, 0 V), the second rectifying element D2 is forward-biased and becomes conductive, and the voltage Vc across the load 92 becomes low (for example, -10 V). As a result, the current flows in the inductor 94 in the negative direction, and the control target 102 moves in the negative direction. For example, it moves to a position in the negative direction corresponding to the magnetic flux density shown at point C in FIG. At this time, the potential Va at the connection point is maintained at 10V.

  At the next time point t86, when the data signal SD changes to a high level (for example, 10 V), the second rectifying element D2 is again reverse-biased and becomes non-conductive, and the voltage Vc across the load 92 sharply rises to 0V. However, the control target is stopped at a position corresponding to the residual magnetic flux density shown at point D in FIG.

  At the next time point t87, it enters the negative direction period Ts2n of the circuit element 10 in the second row (the non-selection period Ts1u of the circuit element in the first row). At this time, the second signal S2 changes to a low level (for example, 0 V). Therefore, in the negative direction period Ts2n, even if the level of the data signal SD changes, the level is lower than the high level of the first signal S1 in the first row and the second signal S2 in the first row. , The first and second rectifying elements D1 and D2 relating to the circuit elements 10 in the first row are both kept in a non-conductive state. That is, the control target is stopped at a position corresponding to the residual magnetic flux density indicated by the point D in FIG.

  As described above, the circuit elements 10 in the first row are not affected by the data signal SD with respect to the circuit elements 10 in the second row, and use the residual magnetic flux density of the BH characteristic shown in FIG. , The position of the control target can be maintained. That is, since no current flows through the inductor 94 during the non-selection period, the position of the control target 102 is held without change due to residual magnetization. Further, the current i flowing to the load 92 during the non-selection period is substantially zero, and the power consumption can be reduced.

  Note that the circuit element, the signal processing circuit, the control device, the display device, the display device driving method, the circuit element driving method, and the control device driving method according to the present invention are not limited to the above-described embodiments. Of course, various configurations can be adopted without departing from the gist.

FIG. 2 is a configuration diagram illustrating a circuit element according to the present embodiment. FIG. 2 is a configuration diagram illustrating a signal processing circuit according to the present embodiment. FIG. 4 is an explanatory diagram illustrating a potential relationship during an operation period of the signal processing circuit according to the present embodiment. FIG. 1 is a configuration diagram illustrating a display device according to a first embodiment. FIG. 4 is a diagram illustrating a voltage-accumulated charge characteristic of a capacitive load used in the display device according to the first embodiment. 5 is a timing chart illustrating an example of a driving method of the display device according to the first embodiment. 4 is a diagram illustrating timings when the driving method of the display device according to the first embodiment is applied to four-row scanning. 8A is a waveform diagram showing a case where the end point of the first voltage state is changed by pulse width modulation of a pixel signal, FIG. 8B is a diagram showing an example of an optical output waveform, and FIG. 8C is an optical output waveform. It is a figure showing other examples of. 9A is a waveform diagram showing a case where the amplitude of the first voltage state is changed by amplitude modulation of a pixel signal, FIG. 9B is a diagram showing an example of an optical output waveform, and FIG. It is a figure showing the example of. It is a lineblock diagram showing a display concerning a 2nd embodiment. FIG. 11A is a waveform diagram showing a change in voltage between both ends of a capacitive load used in the display device according to the second embodiment, and FIG. 11B shows a change in light output according to a change in voltage between both ends of the capacitive load. FIG. 9 is a timing chart illustrating an example of a driving method of a display device according to a second embodiment. FIG. 13A is a diagram illustrating an example of a timing when the driving method of the display device according to the second embodiment is applied to four-row scanning, and FIG. 13B is a diagram illustrating another example. FIG. 14A is a waveform diagram showing an example in which the phase of a trigger signal included in a pixel signal is changed, and FIG. 14B is a waveform diagram showing a case in which the start point of the first voltage state is changed by phase modulation. FIG. 14C is a diagram illustrating an example in which the light output period changes according to the phase of the trigger signal. 15A is a waveform diagram showing an example in which the pulse width of a pixel signal is changed, FIG. 15B is a waveform diagram showing a case in which the amplitude of the first voltage state is changed by pulse width modulation, and FIG. FIG. 5 is a diagram showing an example in which the output level of the pixel signal changes according to the pulse width of the pixel signal. 16A is a waveform diagram showing an example in which the amplitude of a pixel signal is changed, FIG. 16B is a waveform diagram showing a case in which the amplitude of the first voltage state is changed by amplitude modulation, and FIG. 16C is a light output. FIG. 5 is a diagram illustrating an example in which a level changes according to the amplitude of a pixel signal. FIG. 14 is a configuration diagram illustrating a display device according to a third embodiment. FIG. 14 is a diagram illustrating a duty ratio-light amount characteristic of a capacitive load used in the display device according to the third embodiment. FIG. 19A is a waveform diagram showing an example in which the phase of a trigger signal included in a pixel signal is changed, and FIG. 19B is a waveform diagram showing a case in which the start point of the second voltage state is changed by phase modulation. FIG. 19C is a diagram illustrating an example in which the output level of light changes according to the phase of the trigger signal. FIG. 14 is a diagram illustrating a storage voltage-light amount characteristic of a capacitive load used in the display device according to the third embodiment. 21A is a waveform diagram showing an example in which the pulse width of a pixel signal is changed, FIG. 21B is a waveform diagram showing a case in which the amplitude of the second voltage state is changed by pulse width modulation, and FIG. FIG. 5 is a diagram showing an example in which the output level of the pixel signal changes according to the pulse width of the pixel signal. FIG. 22A is a waveform diagram showing an example in which the amplitude of a pixel signal is changed, FIG. 22B is a waveform diagram showing a case in which the amplitude of the second voltage state is changed by amplitude modulation, and FIG. 22C is a light output. FIG. 5 is a diagram illustrating an example in which a level changes according to the amplitude of a pixel signal. 13 is a timing chart illustrating an example of a driving method of a display device according to a third embodiment. It is a lineblock diagram showing the display concerning a 4th embodiment. 15 is a timing chart illustrating an example of a driving method of a display device according to a fourth embodiment. FIG. 26A is a diagram illustrating an example of timing when the driving method of the display device according to the fourth embodiment is applied to four-row scanning, and FIG. 26B is a diagram illustrating another example. FIG. 27A is a waveform diagram showing an example in which the phases of a positive trigger signal and a negative trigger signal included in a pixel signal are changed, and FIG. 27B is a first voltage state and a second voltage state by phase modulation. FIG. 27C is a diagram showing an example in which the light output period changes according to the phases of the positive trigger signal and the negative trigger signal. FIG. 28A is a waveform diagram showing an example in which the pulse width of the pixel signal is changed, and FIG. 28B is a waveform diagram showing a case in which the respective amplitudes of the first voltage state and the second voltage state are changed by pulse width modulation. FIG. 28C is a diagram showing an example in which the light output level changes according to the pulse width of the pixel signal. FIG. 29A is a waveform diagram showing an example in which the amplitude of a pixel signal is changed, and FIG. 29B is a waveform diagram showing a case in which each amplitude in a first voltage state and a second voltage state is changed by amplitude modulation. FIG. 29C is a diagram showing an example in which the light output level changes according to the amplitude of the pixel signal. 1 is a configuration diagram illustrating a position control device according to the present embodiment. FIG. 3 is an explanatory diagram illustrating a model of a position control system including an inductor and a resistor. FIG. 7 is a characteristic diagram illustrating a change in the position of a control target according to the magnitude and direction of a current flowing through an inductor. 6 is a timing chart showing a control operation when the control target is displaced in the forward direction in the position control device according to the present embodiment. 6 is a timing chart showing a control operation when the control target is displaced in the negative direction in the position control device according to the present embodiment. FIG. 35A is a diagram illustrating an example of timing when the driving method of the position control device according to the present embodiment is applied to four-row scanning, and FIG. 35B is a diagram illustrating another example. FIG. 36A is an explanatory diagram showing the setting of the voltage between both ends of the load when the control target is moved in the positive direction. FIG. 36B is an explanatory diagram showing the setting of the voltage between both ends of the load when moving the control target in the negative direction. is there. FIG. 4 is a diagram illustrating an example of a displacement-voltage characteristic of a piezoelectric element used as a displacement control element. FIG. 9 is a diagram illustrating another example of the displacement-voltage characteristic of a piezoelectric element used as a displacement control element. It is a schematic structure figure showing the optical switch array constituted by arranging many displacement control elements. FIG. 40A is an explanatory diagram showing a first state of the optical switch, and FIG. 40B is an explanatory diagram showing a second state of the optical switch. It is a figure showing an example of BH characteristics of a displacement control element using a coil with a large residual magnetic flux. 6 is a timing chart illustrating an example of a method of driving a circuit element including a displacement control element using a coil having a large residual magnetic flux. It is an explanatory view showing a conventional passive matrix drive system. FIG. 4 is an explanatory diagram showing a conventional active matrix driving method using a nonlinear resistance element. FIG. 4 is a diagram illustrating current-voltage characteristics of a nonlinear resistance element.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 10 ... Circuit element 12 ... 1st wiring 14 ... 2nd wiring 16 ... 3rd wiring 18, 58 ... Connection point 20, 92 ... Load 30 ... Signal processing circuit 40A-40D ... Display device 42 ... Pixel 44 ... Display Section 46 Selection line 48 Signal line 50 Reset line 60 Capacitive load 70 Discharge instruction line 80 First line 82 Second line 90 Position control device 94 Inductor D1 First rectifier D2: second rectifying element

Claims (43)

A first wiring;
A second wiring;
A third wiring;
First and second rectifying elements serially connected in a forward direction between the first wiring and the second wiring, respectively;
A circuit element having a load connected between a connection point of the first and second rectifiers and the third wiring. The circuit element according to claim 1,
When the potential of the first wiring is V1 and the potential of the second wiring is V2,
V1 ≧ V2 over the entire operation period
A circuit element, characterized in that: The circuit element according to claim 2,
A circuit element, wherein a first period in which a current flows from the third wiring to the load is set in the operation period. The circuit element according to claim 3,
When the potential at the connection point is V3,
In the first period,
V1 <V3
A circuit element characterized by satisfying the following. The circuit element according to claim 2,
A circuit element, wherein a second period in which a current flows from the second wiring to the load is set in the operation period. The circuit element according to claim 5,
When the potential at the connection point is V3,
In the second period,
V2> V3
A circuit element characterized by satisfying the following. The circuit element according to claim 2,
A circuit element, wherein a third period for inhibiting conduction to the load is set in the operation period. The circuit element according to claim 7,
When the potential at the connection point is V3,
In the third period,
V2 ≦ V3 ≦ V1
A circuit element characterized by satisfying the following. The circuit element according to any one of claims 1 to 8,
A circuit element, wherein the rectifying element is a diode. The circuit element according to claim 9,
A circuit element, wherein the diode is a thin film diode. The circuit element according to claim 10,
A circuit element, wherein the thin film diode is an MIM element. A signal processing circuit having a circuit element and a control circuit,
(1) The circuit element includes:
A first wiring;
A second wiring;
A third wiring;
First and second rectifying elements serially connected in a forward direction between the first wiring and the second wiring, respectively;
A load connected between a connection point of the first and second rectifying elements and the third wiring,
(2) The control circuit includes:
A signal processing circuit which controls at least a potential of the first wiring and a potential of the second wiring. A control device having a plurality of circuit elements and a control circuit,
(1) The circuit element includes:
A first wiring;
A second wiring;
A third wiring;
First and second rectifying elements serially connected in a forward direction between the first wiring and the second wiring, respectively;
A load connected between a connection point of the first and second rectifying elements and the third wiring,
(2) The control device, wherein the control circuit controls potentials of the first wiring, the second wiring, and the third wiring. The control device according to claim 13,
When the potential of the first wiring is V1 and the potential of the second wiring is V2,
V1 ≧ V2 over the entire operation period
A control device, characterized in that: The control device according to claim 14,
During the operation period, a selection period and a non-selection period are set for each of the circuit elements,
When the potential at the connection point is V3,
In the non-selection period,
V2 ≦ V3 ≦ V1
A control device characterized by satisfying the following. The control device according to claim 15,
In the selection period,
V1 <V3 or V2> V3
A control device characterized by satisfying the following. The control device according to claim 16,
During the operation period, a reset period is set for each of the circuit elements,
In the reset period,
V1 <V3 or V2> V3
A control device characterized by satisfying the following. The control device according to any one of claims 13 to 17,
The control device, wherein the load is a displacement control element that displaces a control target based on a voltage applied to the load. The control device according to claim 18,
The said displacement control element has a piezoelectric element, The control apparatus characterized by the above-mentioned. The control device according to claim 18,
The control device, wherein the displacement control element has an inductor, and controls a displacement of the control target by magnetization of the inductor, which is controlled by a current flowing through the inductor by a voltage. The control device according to claim 18,
The control device, wherein the displacement control element has at least a pair of opposing electrodes, and utilizes an electrostatic force that acts when a voltage is applied between the at least one pair of electrodes. A display unit having a number of pixels,
A large number of selection lines indicating selection / non-selection for each pixel,
A number of signal lines for supplying pixel signals to each pixel in the selected state,
A number of reset lines for supplying a reset signal to each pixel in a selected state,
Each of the pixels is
First and second rectifying elements serially connected in a forward direction between any two of the selection line, the signal line, and the reset line;
A display device comprising: a load connected between a connection point of the first and second rectifying elements and a remaining line. The display device according to claim 22,
Of the selection line, the signal line, and the reset line, a line to which a cathode of the first rectifier is connected is defined as a first line, and a line to which an anode of the second rectifier is connected. Defined as the second line,
When the potential of the first line is V1 and the potential of the second line is V2,
V1 ≧ V2 over the entire operation period
A display device, characterized in that: The display device according to claim 23,
During the operation period, a selection period and a non-selection period are set for each of the pixels,
When the potential at the connection point is V3,
In the non-selection period,
V2 ≦ V3 ≦ V1
A display device characterized by satisfying the following. The display device according to claim 24,
In the selection period,
V1 <V3 or V2> V3
A display device characterized by satisfying the following. The display device according to claim 25,
During the operation period, a reset period is set for each of the pixels,
In the reset period,
V1 <V3 or V2> V3
A display device characterized by satisfying the following. A display unit having a number of pixels,
A large number of selection lines indicating selection / non-selection for each pixel,
A number of signal lines for supplying pixel signals to each pixel in the selected state,
A number of reset lines for supplying a reset signal to each pixel in a selected state,
Each of the pixels is
First and second rectifying elements serially connected in a forward direction between any two of the selection line, the signal line, and the reset line;
A driving method of a display device having a load connected between a connection point of the first and second rectifying elements and a remaining line,
Of the selection line, the signal line, and the reset line, a line to which a cathode of the first rectifier is connected is defined as a first line, and a line to which an anode of the second rectifier is connected. Defined as the second line,
When the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3,
Of the pixels, the selected pixels are driven so that V1 <V3 or V2> V3,
A method for driving a display device, wherein pixels in a non-selected state are driven so that V2 ≦ V3 ≦ V1. The method for driving a display device according to claim 27,
The pixel is
A driving method of a display device, characterized by having a light emission characteristic in which light is emitted during an application period of the second voltage state by applying a first voltage state and a second voltage state to the load. The method for driving a display device according to claim 28,
The end point of the second voltage state is changed by modulating the pulse width of the pixel signal supplied to the pixel in accordance with the gray level of the pixel, so that the light emission luminance of the pixel is adjusted to the gray level. A method for driving a display device, wherein the method is changed according to a level. The method for driving a display device according to claim 28,
By controlling the amplitude of the pixel signal supplied to the pixel according to the gray level of the pixel, the amplitude of the second voltage state is changed, so that the light emission luminance of the pixel is changed to the gray level. A method for driving a display device, wherein the method is changed in accordance with the method. The method for driving a display device according to claim 28,
By modulating the phase of the trigger signal included in the pixel signal supplied to the pixel according to the gray level of the pixel, the start time of the second voltage state is changed, and the light emission luminance of the pixel is changed. Is changed according to the gradation level. The method for driving a display device according to claim 28,
By modulating the pulse width of the pixel signal supplied to the pixel in accordance with the gradation level of the pixel, thereby changing the amplitude of the second voltage state, the light emission luminance of the pixel is reduced to the gradation level. A method for driving a display device, the method comprising: The method for driving a display device according to claim 28,
When the pixel has a characteristic that a light amount changes according to a duty ratio in a period of the first voltage state with respect to a predetermined period,
By modulating the phase of a trigger signal included in the pixel signal supplied to the pixel in accordance with the gray level of the pixel, the pulse width of the first voltage state is changed, so that the light emission luminance of the pixel is changed. Is changed according to the gradation level. The method for driving a display device according to claim 28,
When the pixel has a characteristic that a light amount changes according to an accumulation voltage in the first voltage state,
By modulating the pulse width of the pixel signal supplied to the pixel in accordance with the gradation level of the pixel, thereby changing the amplitude of the first voltage state, the light emission luminance of the pixel is reduced to the gradation level. A method for driving a display device, the method comprising: The method for driving a display device according to claim 28,
When the pixel has a characteristic that a light amount changes according to an accumulation voltage in the first voltage state,
By modulating the amplitude of the pixel signal supplied to the pixel according to the gray level of the pixel, the amplitude of the first voltage state is changed, so that the light emission luminance of the pixel is changed to the gray level. A method for driving a display device, wherein the method is changed in accordance with the method. The method for driving a display device according to any one of claims 28 to 35,
A driving method for a display device, wherein the first voltage state and the second voltage state are continuously applied to the load. The method for driving a display device according to claim 27,
The pixel is
By applying a first voltage state, a reference voltage state, and a second voltage state having a polarity opposite to the first voltage state to the load, at least an application period of the first voltage state and the A method for driving a display device, wherein the display device has a light emission characteristic in which light emission is performed in an application period of a second voltage state. The method for driving a display device according to claim 37,
The start time of the first voltage state and the start time of the second voltage state are changed by modulating the phase of a trigger signal included in the pixel signal supplied to the pixel according to the gray level of the pixel. A driving method of the display device, wherein the light emission luminance of the pixel is changed in accordance with the gradation level. The method for driving a display device according to claim 37,
The amplitude of the first voltage state and the amplitude of the second voltage state are changed by modulating a pulse width of the pixel signal supplied to the pixel in accordance with a gradation level of the pixel, whereby the pixel Wherein the light emission luminance of the display device is changed according to the gradation level. The method for driving a display device according to claim 37,
By modulating the amplitude of the pixel signal supplied to the pixel in accordance with the gray level of the pixel, the amplitude of the first voltage state and the amplitude of the second voltage state are changed, so that the A method for driving a display device, wherein light emission luminance is changed according to the gradation level. It has a plurality of circuit elements, a plurality of first wirings, a plurality of second wirings, and a plurality of third wirings, and at least one of the first wiring and the second wiring is Wiring for instructing selection / non-selection of each circuit element,
Each of the circuit elements,
First and second rectifying elements serially connected in series in a forward direction between any two of the first wiring, the second wiring, and the third wiring;
A driving method of a circuit element having a load connected between a connection point of the first and second rectifying elements and a remaining wiring,
Of the first wiring, the second wiring, and the third wiring, a line to which a cathode of the first rectifying element is connected is defined as a first line, and an anode of the second rectifying element is defined as a first line. Is defined as a second line,
When the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3,
Among the circuit elements, the circuit elements in the selected state are driven so that V1 <V3 or V2> V3,
A method of driving a circuit element, comprising driving a circuit element in a non-selected state so that V2 ≦ V3 ≦ V1. A plurality of circuit elements;
A large number of selection lines for instructing selection / non-selection for each circuit element,
A number of signal lines for supplying signals to each circuit element in the selected state,
A plurality of reset lines for supplying a reset signal to each circuit element in a selected state,
Each of the circuit elements,
First and second rectifying elements serially connected in a forward direction between any two of the selection line, the signal line, and the reset line;
A driving method of a control device having a load connected between a connection point of the first and second rectifying elements and a remaining line,
Of the selection line, the signal line, and the reset line, a line to which a cathode of the first rectifier is connected is defined as a first line, and a line to which an anode of the second rectifier is connected. Defined as the second line,
When the potential of the first line is V1, the potential of the second line is V2, and the potential of the connection point is V3,
Among the circuit elements, the circuit elements in the selected state are driven so that V1 <V3 or V2> V3,
A driving method for a control device, wherein a circuit element in a non-selected state is driven so that V2 ≦ V3 ≦ V1. Having a plurality of circuit elements,
Each of the circuit elements includes a first wiring for selecting and instructing a positive displacement, a second wiring for selecting and instructing a negative displacement, a third wiring for indicating a displacement amount, First and second rectifying elements serially connected in a forward direction between a first wiring and the second wiring, a connection point between the first and second rectifying elements, and the third wiring And a load connected between the control device and a driving method,
When the potential of the first wiring is V1, the potential of the second wiring is V2, and the potential of the connection point is V3,
The circuit element for which the forward displacement has been selected and instructed is driven such that V1 ≧ V2 and V3> V1 at the start of displacement,
The circuit element for which the negative direction displacement is selected and instructed is driven such that V1 ≧ V2 and V3 <V2 at the displacement start time,
A driving method for a control device, wherein a circuit element in a non-selected state is driven so that V2 ≦ V3 ≦ V1.

Images