JP2004361690A - Plasma display device - Google Patents

Abstract

An object of the present invention is to stop the operation of a display drive circuit when an abnormality occurs in the display drive circuit in a plasma display device.
A scan driver circuit for supplying display data to address electrodes of a plasma display panel, and a plasma display panel disposed between the scan driver circuit and a power supply and according to a display operation of the plasma display panel. Power recovery circuit 20 that recovers energy from the power supply, a midpoint voltage detection circuit 21 that detects a predetermined midpoint voltage of the power recovery circuit 20, and a voltage detected by the midpoint voltage detection circuit 21 and two points. And a microcomputer 26 that controls the operation of the scan driver circuit 12 based on signals from the voltage comparison circuits 24 and 25.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a plasma display device known as a large-screen, thin, and lightweight display device.
[0002]
[Prior art]
Plasma display devices can display at higher speeds than liquid crystal panels, have a wider viewing angle, are easier to increase in size, and have higher display quality due to their self-luminous type. It has recently received particular attention in technology.
[0003]
Generally, in this plasma display device, an ultraviolet ray is generated by gas discharge, and a phosphor is excited by the ultraviolet ray to emit light, thereby performing color display. Then, a display cell partitioned by a partition is provided on the substrate, and a phosphor layer is formed on the display cell.
[0004]
This plasma display device is roughly classified into an AC type and a DC type in terms of driving, and there are two types of discharge types, a surface discharge type and a counter discharge type. At present, the mainstream of plasma display devices is a surface discharge type having a three-electrode structure, which has a pair of display electrodes adjacent to each other in parallel on one substrate, and a structure on the other substrate. It has address electrodes arranged in a direction intersecting with the display electrodes, partition walls, and a phosphor layer, so that the phosphor layer can be made relatively thick, which is suitable for color display by the phosphor.
[0005]
Further, as a driving circuit of this plasma display device, a driving circuit as shown in Patent Document 1 is known.
[0006]
[Patent Document 1]
JP 2002-278509 A
[Problems to be solved by the invention]
An object of the present invention is to make it possible to control the operation of the display drive circuit when an abnormality occurs in the display drive circuit in such a plasma display device.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a plasma display device according to the present invention comprises a plurality of rows of stripe-shaped display electrodes on a pair of substrates forming a discharge space and being paired with a scan electrode and a sustain electrode facing each other. And a plasma display panel having a plurality of discharge cells formed by providing a plurality of columns of address electrodes facing each other so as to intersect with each other, and supplying a drive signal voltage and a sustain pulse to the scan electrodes of the plasma display panel. And a power recovery circuit disposed between the scan driver circuit and a power supply for recovering energy from the plasma display panel in accordance with the display operation of the plasma display panel. A midpoint voltage detection circuit for detecting a voltage at a predetermined midpoint; A voltage comparison circuit for comparing the reference voltage of the voltage and the two points detected by the pressure detecting circuit, in which and a control circuit for controlling the operation of the scan driver circuit by the signal from the voltage comparator circuit.
[0009]
With this configuration, the operation of the scan driver circuit can be controlled when an abnormality occurs in the scan driver circuit portion.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7, but embodiments of the present invention are not limited thereto.
[0011]
First, the structure of a plasma display panel in a plasma display device will be described with reference to FIG. As shown in FIG. 1, a plurality of rows of stripe-shaped display electrodes 2 formed of a pair of scan electrodes and sustain electrodes are formed on a transparent front substrate 1 such as a glass substrate, and cover the electrode group. A dielectric layer 3 is formed as described above, and a protective film 4 is formed on the dielectric layer 3.
[0012]
A plurality of rows of stripes covered with an overcoat layer 6 are provided on a rear substrate 5 opposed to the front substrate 1 so as to intersect with the display electrodes 2 of scan electrodes and sustain electrodes. Address electrodes 7 are formed. A plurality of partitions 8 are arranged on the overcoat layer 6 between the address electrodes 7 in parallel with the address electrodes 7, and the phosphor layers 9 are provided on the side surfaces between the partitions 8 and on the surface of the overcoat layer 6. I have.
[0013]
The substrate 1 and the substrate 5 are opposed to each other with a minute discharge space therebetween so that the display electrode 2 of the scan electrode and the sustain electrode and the address electrode 7 are substantially orthogonal to each other, and the periphery thereof is sealed. In the discharge space, one or a mixed gas of helium, neon, argon, and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of partitions by partition walls 8, so that a plurality of discharge cells are provided at intersections between the display electrodes 2 and the address electrodes 7, and each of the discharge cells has a red, green, and blue color. The phosphor layers 9 are sequentially arranged for each color such that
[0014]
FIG. 2 shows an electrode arrangement of the plasma display panel. As shown in FIG. 2, the scan electrodes, sustain electrodes, and address electrodes have a matrix configuration of M rows × N columns, and M rows × N columns are arranged in the row direction. Scan electrodes SCN1 to SCNM and sustain electrodes SUS1 to SUSM are arranged, and N columns of address electrodes D1 to DN are arranged in the column direction.
[0015]
In the plasma display panel having such an electrode configuration, an address discharge is performed between the address electrode and the scan electrode by applying a write pulse between the address electrode and the scan electrode, and after selecting a discharge cell, the scan electrode A sustain discharge is performed between the scan electrode and the sustain electrode by applying a periodic sustain pulse that is alternately inverted between the scan electrode and the sustain electrode, thereby performing a predetermined display.
[0016]
In general, an ADS (address / display period separation) method is used as a gradation display driving method for a plasma display device. In the ADS method, one field is temporally divided into a plurality of subfields. For example, when displaying 256 gradations with 8 bits, one field is divided into eight subfields. Each subfield is divided into an address period in which an address discharge for selecting a lighting cell is performed and a sustain period (display discharge period) in which a sustain discharge for display is performed.
[0017]
In the ADS method, scanning by address discharge is performed on the entire surface of the PDP from the first line to the m-th line in each subfield, and sustain discharge is performed when the entire address discharge is completed.
[0018]
FIG. 3 shows a configuration of a display driving circuit of the plasma display device according to the present embodiment. As shown in FIG. 3, a plasma display panel (PDP) 10, an address driver circuit 11, a scan driver circuit 12, a sustain driver circuit 13, a discharge control timing generation circuit 14, power supply circuits 15, 16, A having the configuration shown in FIG. A / D converter (analog / digital converter) 17, a scan number converter 18, and a subfield converter 19 are provided.
[0019]
In the circuit of FIG. 3, first, the video signal VD is input to the A / D converter 17. The horizontal synchronizing signal H and the vertical synchronizing signal V are supplied to a discharge control timing generation circuit 14, an A / D converter 17, a scan number conversion unit 18, and a subfield conversion unit 19. The A / D converter 17 converts the video signal VD into a digital signal, and provides the image data to the scan number converter 18.
[0020]
The scanning number conversion unit 18 converts the image data into image data of the number of lines corresponding to the number of pixels of the PDP 10 and supplies the image data of each line to the subfield conversion unit 19. The subfield conversion unit 19 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serializes each bit of the pixel data for each subfield to the address driver circuit 11. Output to The address driver circuit 11 is connected to the power supply circuit 15, converts data serially provided for each subfield from the subfield conversion unit 19 into parallel data, and applies a voltage to a plurality of address electrodes based on the parallel data. Supply.
[0021]
The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU with reference to the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 has an output circuit 121 and a shift register 122. Further, the sustain driver circuit 13 includes an output circuit 131 and a shift register 132. These scan driver circuit 12 and sustain driver circuit 13 are connected to a common power supply circuit 16.
[0022]
The shift register 122 of the scan driver circuit 12 supplies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting in the vertical scanning direction. The output circuit 121 sequentially supplies a drive signal voltage to the plurality of scan electrodes in response to a discharge control timing signal SC provided from the shift register 122.
[0023]
The shift register 132 of the sustain driver circuit 13 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting in the vertical scanning direction. The output circuit 131 sequentially supplies a drive signal voltage to the plurality of sustain electrodes in response to the discharge control timing signal SU given from the shift register 132.
[0024]
FIG. 4 shows an example of a timing chart of the display drive circuit of the plasma display device. As shown in FIG. 4, during the writing period, after all the sustain electrodes SUS1 to SUSM are held at 0 (V), A positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the first row, and a negative scan pulse voltage -Vs (V) is applied to the scan electrodes SCN1 in the first row. When applied to each of them, a write discharge occurs at the intersection of the predetermined address electrodes D1 to DN and the scan electrode SCN1 in the first row.
[0025]
Next, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the second row, and a negative scan pulse voltage -Vs is applied to the scan electrodes SCN2 in the second row. When (V) is applied to each, a write discharge occurs at the intersection of the predetermined address electrodes D1 to DN and the scan electrode SCN2 in the second row.
[0026]
The same operation as described above is sequentially performed. Finally, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed on the Mth row, and the Mth row is scanned. When a negative scan pulse voltage -Vs (V) is applied to each of the electrodes SCNM, a write discharge occurs at the intersection of the predetermined address electrodes D1 to DN and the scan electrode SCNM in the Mth row.
[0027]
In the next sustain period, when all the scan electrodes SCN1 to SCNM are once held at 0 (V) and a negative sustain pulse voltage -Vm (V) is applied to all the sustain electrodes SUS1 to SUSM, write discharge occurs. A sustain discharge occurs between the scan electrodes SCN1 to SCNM and the sustain electrodes SUS1 to SUSM at the intersection. Next, a negative sustain pulse voltage -Vm (V) is alternately applied to all of the scan electrodes SCN1 to SCNM and all of the sustain electrodes SUS1 to SUSM, so that sustain discharge continuously occurs in the discharge cells to be displayed. Panel display is performed by the light emission of the sustain discharge.
[0028]
In the next erasing period, when all the scan electrodes SCN1 to SCNM are once held at 0 (V) and the erasing pulse voltage -Ve (V) is applied to all the sustain electrodes SUS1 to SUSM, an erasing discharge occurs to cause a discharge. Stops.
[0029]
With the above operation, one screen is displayed on the plasma display device.
[0030]
FIG. 5 is a diagram showing a main circuit configuration of a scan driver circuit portion in the display drive circuit shown in FIG. 3. As shown in FIG. 5, the PDP 10 is provided between the scan driver circuit 12 and the power supply circuit 16. A power recovery circuit 20 that recovers energy from the PDP 10 according to a display operation is connected and arranged.
[0031]
Reference numeral 21 denotes a midpoint voltage detection circuit for detecting a predetermined midpoint voltage of the power recovery circuit 20, 22 and 23 reference voltage generation circuits connected to a low voltage power supply, and 24 and 25 detection by the midpoint voltage detection circuit 21. A voltage comparison circuit that compares the obtained voltage with two reference voltages generated by the reference voltage generation circuits 22 and 23. The signals of the voltage comparison circuits 24 and 25 are used as a control circuit for controlling the operation of the scan driver circuit 12. It is connected so as to be input to the microcomputer 26.
[0032]
In general, in a plasma display device, the midpoint voltage of the power recovery circuit 20 connected to the scan driver circuit 12 is always detected, and when an abnormality occurs, it is detected that the midpoint voltage becomes 0 V as compared with the normal state. Notifying the abnormality, the operation of the discharge control circuit is stopped, and the operation of the power supply circuit is also stopped, so that the destruction of components of the power recovery circuit 20 is minimized.
[0033]
Conventionally, for this kind of purpose, as shown in FIG. 6, a midpoint voltage detecting circuit 21 for detecting the midpoint voltage of the power recovery circuit 20 is connected and arranged, and the midpoint voltage is always detected. When an abnormality occurs in the power recovery circuit 20, it detects that the midpoint voltage becomes 0V, sends an abnormality occurrence signal to the microcomputer 26, stops the operation of the discharge control circuit, and also stops the operation of the power supply circuit. Although the destruction of the components of the power recovery circuit 20 has been minimized, no abnormality other than the midpoint voltage of 0 V can be detected.
[0034]
In the present invention, a midpoint voltage detection circuit 21 that detects a midpoint voltage of the power recovery circuit 20, a voltage comparison circuit 24 that compares the voltage detected by the midpoint voltage detection circuit 21 with two reference voltages, The microcomputer 26 is connected and arranged in accordance with signals from the voltage comparison circuits 24 and 25, and always compares the midpoint voltage detection range with the reference voltage range so that the midpoint voltage detection range is higher than the reference voltage range. When it comes off, an abnormality occurrence signal is sent to the microcomputer 26 to stop the operation of the discharge control circuit and the operation of the power supply circuit. FIG. 7 shows an outline of a midpoint voltage detection range and a control operation range according to the present invention.
[0035]
As described above, according to the circuit configuration of the present embodiment, when an abnormality occurs in the power recovery circuit, not only when the midpoint voltage becomes 0 V but also when the midpoint voltage is out of the normal operation range, The operation can be stopped to minimize the destruction of the circuit.
[0036]
【The invention's effect】
As is apparent from the above description, according to the plasma display device of the present invention, when an abnormality occurs in the power recovery circuit, not only the case where the midpoint voltage becomes 0 V, but also the midpoint voltage is out of the normal operation range. Also in such a case, an effect is obtained that the circuit operation is stopped and the destruction of the circuit can be minimized.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a schematic configuration of a panel of a plasma display device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an electrode arrangement of the panel of the plasma display device. FIG. FIG. 4 is a block diagram illustrating an example of a display driving circuit. FIG. 4 is a signal waveform diagram illustrating an example of a driving method of the plasma display device. FIG. 5 is a circuit diagram illustrating main circuits of the display driving circuit of the plasma display device. 6 is a circuit diagram of a circuit as a comparative example of the present invention. FIG. 7 is an explanatory diagram showing an operation range of the circuit in the present invention.
Reference Signs List 10 Plasma display panel 12 Scan driver circuit 16 Power supply circuit 20 Power recovery circuit 21 Midpoint voltage detection circuit 22, 23 Reference voltage generation circuit 24, 25 Voltage comparison circuit 26 Microcomputer

Claims (1)

A plurality of columns of stripe-shaped display electrodes on a pair of substrates paired with a scan electrode and a sustain electrode facing each other to form a discharge space, and a plurality of columns of address electrodes facing each other so as to intersect the display electrodes; And a scan driver circuit for supplying a drive signal voltage and a sustain pulse to the scan electrodes of the plasma display panel, a scan driver circuit and a power supply. A power recovery circuit that is disposed between and recovers energy from the plasma display panel in accordance with the display operation of the plasma display panel; and a midpoint voltage detection circuit that detects a predetermined midpoint voltage of the power recovery circuit. , A voltage ratio for comparing the voltage detected by the midpoint voltage detection circuit with two reference voltages A plasma display device comprising a circuit, by comprising a control circuit for controlling the operation of the scan driver circuit by the signal from the voltage comparator circuit.

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