JP2004349309A - Semiconductor storage device - Google Patents

Abstract

An object of the present invention is to provide a memory cell array in which the influence of a signal from a non-selected cell during operation of a memory cell is reduced and good reading is possible.
In a semiconductor memory device including a plurality of transistors having a memory function and formed on a semiconductor substrate, a plurality of bit lines are connected to source regions of the plurality of transistors, and sense is independently performed. Conventionally, by providing a plurality of bit lines connected to the source region without sharing, a cell array capable of reducing the influence of the signal of the unselected cell connected to the bit line on the read side of the selected cell is provided. Can be provided.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device including a memory cell array in which nonvolatile memory elements are arranged.
[0002]
[Prior art]
FIG. 11 is a schematic plan view of a conventional memory cell, FIG. 12 is a cross-sectional view taken along line AA ′ of the schematic plan view, and FIG. 13 is a circuit diagram of a memory cell array. The memory cell in FIG. 12 is, for example, a flash memory. A gate oxide film 402 is provided on a semiconductor substrate 401, and further has a floating gate 403 serving as a charge retention film thereon. 404 is an insulating film, and 405 is a control gate. 406 is a source region, and 407 is a drain region. 408 is an interlayer insulating film, 409 is a bit line contact, and 410 is a metal wiring serving as a bit line. The threshold voltage of the field-effect transistor viewed from the control gate 405 changes depending on the presence or absence of the charge in the floating gate 403, and data is read. The operation principle will be described with reference to the cell array diagram of FIG. , Bn are bit lines serving as data lines, and are connected to, for example, the drain region 407 in FIG. 12 of each memory cell. W1, W2, W3,..., Wm are word lines, and are composed of control gates 405. By selecting a specific word line and a specific bit line, a specific memory cell can be selected. For example, if the word line W1 and the bit line B2 are selected, the memory cell M11 is selected. SL is a source line, which is connected to a source region of each memory cell.
[0003]
In this case, for example, when selecting and reading M11, the information written in M11 can be read by setting the word line W1 to the high level, the bit line B1 to the high level, and the source line SL to the low level. it can.
[0004]
[Patent Document 1] JP-A-3-219496
[0005]
[Problems to be solved by the invention]
However, in the above-mentioned conventional memory cell, unselected cells M21,..., Mm1 are also connected to the bit line B1 connected to the selected memory cell M11. That is, although the word lines W2, W3,..., Wm connected to the unselected cells are at the low level, the potential difference between the source and the drain is low because the bit line B1 is at the high level and the source line SL is at the low level. , Mm1, and an off current flows through each of the non-selected memory cells M21, M31,..., Mm1. For example, when the ON / OFF ratio of the transistor constituting each memory cell is about three digits, when m = 1000, the current read from M11 is read from M21, M31,..., Mm1. The current becomes about the same as the total current, and it becomes difficult to detect the stored information of the selected cell by the current flowing through the selected bit line. Therefore, the number (m number) of memory cells connected to the bit line is limited by the ON / OFF ratio of the transistors constituting the memory cells.
[0006]
The present invention has been made in view of the above problems, and provides a memory cell array in which the influence of a leak current from an unselected cell at the time of a read operation of a memory cell is reduced and good read is possible.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device according to a first aspect of the present invention
In a semiconductor memory device in which a plurality of transistors having a memory function are arranged in a matrix on a semiconductor substrate,
The transistor has two diffusion regions serving as source / drain regions,
The gate electrodes of the transistors arranged in the row direction are connected to each other by a word line,
One of the diffusion regions of the transistors arranged in the column direction is connected to each other by a first bit line,
The other one of the diffusion regions of the transistors arranged in the row direction is connected to each other by a second bit line.
[0008]
According to the above configuration, a transistor having a specific memory function can be selected by selecting a specific word line and a first bit line. Furthermore, since the potentials applied to the first bit line and the second bit line can be controlled independently for each line, the leakage current from the non-selected memory cell during the read operation of the selected memory cell can be controlled. , And a good read operation can be performed. Further, since the influence of the leak current of the unselected memory cells can be effectively suppressed, the number of memory cells connected to the bit line can be increased, and the integration degree of the memory cell array can be improved.
[0009]
According to a second aspect of the present invention, in the semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate,
On the surface of the semiconductor substrate of the first conductivity type, element isolation regions extending in a first direction are formed side by side in a second direction intersecting the first direction, and are respectively formed between adjacent element isolation regions. An active region extending in the first direction is defined;
In each of the active regions, first diffusion regions and second diffusion regions are alternately formed,
A channel region is defined between the adjacent first diffusion region and second diffusion region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate so as to pass over a channel region in each of the active regions.
On the semiconductor substrate, a plurality of first bit lines extending in the first direction are connected to first underlying diffusion regions, respectively.
A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and are respectively connected to the corresponding second diffusion regions. It is characterized by
[0010]
According to the above configuration, the same operation and effect as those of the semiconductor memory device of the first invention can be obtained.
[0011]
In one embodiment, a film having a memory function is provided below the word line in a region where the word line intersects with the channel region, and the film having a memory function is a silicon film. The word line and the channel region are electrically separated by an insulating film.
[0012]
In the above embodiment, the material forming the film having the memory function is specified.
In one embodiment, the silicon film is polycrystalline silicon.
[0013]
According to the above embodiment, since the polycrystalline silicon film is the most commonly used material in the LSI manufacturing process, the process can be easily constructed.
[0014]
In one embodiment, the transistor having a memory function stores two bits of information with one transistor.
[0015]
According to the above embodiment, since the cell area per bit is significantly reduced, the degree of integration of the memory cell array can be improved.
[0016]
In one embodiment, an insulating film having a memory function is provided below the word line on the active region where the word line intersects with the channel region.
[0017]
The above embodiment shows a specific structure in which one transistor stores 2-bit information. Since an insulating film having a memory function is used, charges can be locally stored in the insulating film, and 2-bit storage can be performed.
[0018]
In one embodiment, the insulating film having a memory function is a silicon nitride film.
[0019]
According to the above embodiment, the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0020]
According to one embodiment, a memory function body is formed on both sides of a portion of the word line on the channel region, and the memory function body includes a charge holding film having a function of accumulating charges. It is characterized by:
[0021]
According to the above embodiment, since the charge holding film having the function of accumulating charges is formed in the memory function body formed on both sides of the word line, miniaturization of the transistor is easy. Therefore, the degree of integration of the memory cell array can be improved.
[0022]
Further, it can be formed by a process which has a very high affinity with a normal field-effect transistor forming a memory element and a logic circuit. In other words, the mixed mounting process of the logic circuit and the memory cell array is easy.
[0023]
In one embodiment, the charge retention film is a silicon nitride film.
[0024]
According to the above embodiment, the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0025]
In one embodiment, at least one of the first bit line and the second bit line includes a portion made of a high melting point metal.
[0026]
According to the above embodiment, since the number of metal wiring layers can be reduced, it is possible to suppress the step shape from being deteriorated due to the overlapping metal wiring even if miniaturization is advanced to increase the degree of integration. . Therefore, miniaturization of the memory cell array is facilitated. Furthermore, by using a high melting point metal, a low resistance can be realized even if the source / drain region (diffusion region) is made shallow, so that the operation of the memory cell array can be sped up.
[0027]
In one embodiment, the voltage V1 is applied to the word line connected to the selected memory cell, and the voltage V2 is applied to the first bit line connected to the selected memory cell, to thereby select the word line. Applying a voltage V3 to a second bit line connected to the selected memory cell, and applying a voltage V3 to a first bit line other than the first bit line connected to the selected memory cell. The read operation of the memory cell is performed by applying the voltage V2 to a second bit line other than the second bit line connected to the selected memory cell.
[0028]
According to the above embodiment, it is possible to reduce the influence of the off-leak of the non-selected memory cell. Further, it is possible to prevent a non-selected memory cell connected to the word line from being turned on and causing a current to flow, thereby changing the potential of the second bit line.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
<First embodiment>
FIG. 1 is a schematic plan view of a memory cell array according to a first embodiment of the present invention, and FIGS. 2 to 4 are cross-sectional views taken along line AA ′, BB ′, and CC ′ in FIG. FIG. 5 shows a circuit diagram of the memory cell array. In FIG. 5, a transistor having a memory function (memory cell) is represented by a symbol indicating a normal field effect transistor.
[0030]
In the memory cell array according to the present embodiment, as shown in FIGS. 1 to 3, a silicon oxide film 102 is formed on a semiconductor substrate 101 as a gate insulating film, for example, in a thickness of about 1 nm to 10 nm. Further, a charge retention film 103 made of, for example, a silicon nitride film is provided on the upper portion of the charge retention film 103 in a thickness of about 2 nm to 10 nm. A silicon oxide film 104 having a thickness of 5 nm to 10 nm is provided thereon as an insulating film. The electric charge is held in regions 105 and 106 of the silicon nitride film 103. Further, a gate electrode 107 is provided on the silicon oxide film 104. In this embodiment mode, the gate electrode 107 forms a word line. Gate electrode 107 is made of polycrystalline silicon or a laminated film of polycrystalline silicon and a metal. Diffusion regions (source / drain regions) 108, 109, 110, and 111 are provided on the semiconductor substrate 101 with the gate electrode 107 interposed therebetween. Reference numeral 112 denotes a gate sidewall insulating film formed of, for example, a silicon oxide film. In addition, a silicon oxide film 113 and a silicon nitride film 114 are provided on the gate electrode 107 in order to form the contacts 116 and 117 by a self-aligned contact (SAC) process. The first interlayer insulating film 115 is made of, for example, a BPSG film (Boron-Phosphorus-Silicate-Glass). The contacts 116 and 117 are, for example, contact plugs made of tungsten. The first layer metal 118 (constituting the second bit line) is made of, for example, aluminum silicon. 119 is a second interlayer insulating film, 120 is a second layer metal (constituting the first bit line), and 121 is an element isolation region.
[0031]
As is clear from FIGS. 1 to 5, the memory cell array according to the present embodiment includes a plurality of transistors having a memory function arranged in a matrix on a semiconductor substrate 101, and each of the transistors has a source / drain region. 2 (for example, the transistor A in FIG. 2 has the diffusion regions 108 and 109), and the gate electrodes of the transistors arranged in the row direction (the horizontal direction in FIG. 1 and FIG. 5) are connected to the word line (W1). , W2,..., Wm), and one of the diffusion regions (the diffusion regions 109 and 111 in FIG. 2) of the transistors arranged in the column direction (vertical direction in FIG. 1 and FIG. 5) is a first bit line ( Ba1, Ba2,..., And Ban), and the other of the diffusion regions of the transistors arranged in the row direction (the diffusion regions 108 and 110 in FIG. 2) is the second diffusion region. Tsu door line (Bb1, Bb2, ..., Bbm) are connected to each other by. By selecting a specific word line and a first bit line, a specific memory cell is selected. For example, if the word line W1 and the first bit line Ba1 are selected, the memory cell M11 can be selected.
[0032]
In the memory cell of the present embodiment, a plurality of transistors having a memory function are arranged on a semiconductor substrate, and a first direction (in FIGS. 1 and 5, The element isolation regions 121 extending in the vertical direction on the paper are formed side by side in the second direction (horizontal direction in FIGS. 1 and 5) intersecting the first direction. Each of the active regions extends in the first direction, and a first diffusion region (the diffusion regions 109 and 111 in FIG. 2) and a second diffusion region (the diffusion region in FIG. 108, 110) are formed alternately, a channel region is defined between the adjacent first diffusion region and the second diffusion region, and a plurality of channel regions extending in the second direction are formed on the semiconductor substrate. Word lines (W1, W2 , Wm) are provided so as to pass over the channel region in each of the active regions, and a plurality of first bit lines (Ba1, Ba2, ..., Ban) extending in the first direction are provided on the semiconductor substrate. ) Are connected to the first diffusion regions located below, and a plurality of second bit lines (Bb1, Bb2,..., Bbm) extending in the second direction are formed on the semiconductor substrate. The second diffusion regions are provided so as to pass over the second diffusion regions, and are connected to the corresponding second diffusion regions.
[0033]
Unlike the memory cell array of the related art, the memory cell array of the present embodiment can independently control the potentials of the second bit lines (Bb1, Bb2,..., Bbm) parallel to the word lines. Therefore, when reading out the selected memory cell M11, the word line W1 is set to the high level, the first bit line Ba1 is set to the high level, the second bit line Bb1 is set to the low level, and the other first bit lines ( , Ban) and the second bit lines (Bb2,..., Bbm) can be opened. In this case, off currents other than the memory cell M1 do not flow to the selected bit line. Therefore, the influence of the leak current from the non-selected memory cell during the read operation of the memory cell is reduced, and a good read operation can be performed. Further, since the influence of the leak current of the unselected memory cells can be effectively suppressed, the number of memory cells connected to the bit line can be increased, and the integration degree of the memory cell array can be improved.
[0034]
In the memory cells constituting the memory cell array of this embodiment, information is written by injecting electric charge into the region 105 or the region 106 in the charge holding film 103, and the threshold value changes depending on the presence or absence of the electric charge in the regions 105 and 106. That is, the change in the amount of current is read. For example, in the transistor A of FIG. 2, information is written by injecting hot electrons into the region 105 in the charge holding film 103 using the diffusion region 108 as a drain and the diffusion region 109 as a source. The reading is performed by using the diffusion region 108 as a source and the diffusion region 109 as a drain, and by judging the presence or absence of charges based on the amount of current flowing, and reading information.
[0035]
Similarly, information can be written by injecting a charge into the region 106 in the charge holding film 103. In this case, the source / drain is reversed when writing and reading charges in the region 105. According to the above method, one memory cell can perform a two-bit operation. Of course, there is no problem even if one memory cell is used for one bit operation. However, it is preferable to store 2-bit information in one memory cell because the degree of integration of the memory cell array is greatly improved.
[0036]
An example of a read operation of the semiconductor device (memory cell array) of this embodiment will be described with reference to FIG.
[0037]
For example, when selecting the memory cell M1, V1 (for example, 2V) is applied to the word line W1, V2 (for example, 0V) is applied to the first bit line Ba1, V3 (for example, 2V) is applied to the second bit line Bb1, Apply each. By applying the voltage in this manner, the memory cell M1 is turned on, and a current flows from the second bit line Bb1 to the first bit line Ba1. At this time, electrons flow from the first bit line Ba1 to the second bit line Bb1. At this time, for example, the stored information of the memory cell M1 can be known by detecting the value of the current flowing through the first bit line Ba1 or monitoring the potential change of the first bit line Ba1. Note that in addition to the above-described read operation, by performing a read operation by further swapping the potentials of the first bit line Ba1 and the second bit line Bb1, 2-bit read of the memory cell M1 can be performed.
[0038]
Note that it is preferable to apply V2 (for example, 0 V) to the second bit lines other than the selected second bit line (Bb1). This is because V2 is applied to the first bit line Ba1, and V2 is also applied to the second bit line other than Bb1, so that the influence of the off-leak of the non-selected memory cell connected to Ba1 is reduced. Because you can.
[0039]
Further, it is preferable to apply V3 (for example, 2 V) to the first bit lines other than the selected first bit line (Ba1). This is because one of the unselected memory cells connected to the word line W1 to which the voltage V1 (for example, 2V) is applied is connected to the second bit line Bb1 to which the voltage V3 (for example, 2V) is applied. Because it is. By applying V3 to the first bit line other than Ba1, the non-selected memory cells connected to the word line W1 are turned on, causing a current to flow, and preventing the potential of the second bit line Bb1 from fluctuating. be able to.
[0040]
As described above, the voltage V1 is applied to the word line connected to the selected memory cell, the voltage V2 is applied to the first bit line connected to the selected memory cell, and the voltage V1 is applied to the selected memory cell. The voltage V3 is applied to the connected second bit line, and the voltage V3 is applied to the first bit lines (non-selected first bit lines) other than the first bit line connected to the selected memory cell. To apply the voltage V2 to a second bit line (an unselected second bit line) other than the second bit line connected to the selected memory cell.
[0041]
Of course, the unselected first bit line and the unselected second bit line may be in an open state.
[0042]
In the memory cell array of the present embodiment, for example, as apparent from FIG. 2, an insulating film (silicon nitride film 103) having a memory function is provided between the gate electrode 107 and the channel region. When charges are accumulated in the insulating film in this manner, one-cell two-bit operation becomes possible as is clear from the above description, and the degree of integration of the memory cell array can be increased.
[0043]
Further, the insulating film having a memory function is preferably a silicon nitride film. This is because the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0044]
Note that the film having a memory function existing between the gate electrode 107 and the channel region is not limited to the silicon nitride film, but may be a silicon film separated from the gate electrode and the channel region by an insulating film. In this case, although one-cell one-bit operation is performed, the effect of the memory cell array of the present embodiment (the effect of leakage current from unselected cells during the read operation of the memory cell is reduced, and a good read operation can be performed, By increasing the number of memory cells connected to the bit line, the degree of integration of the memory cell array can be improved).
[0045]
Preferably, the silicon film is made of polycrystalline silicon.
[0046]
By the way, since it is possible to adopt the SAC process in manufacturing the memory cell array of the present embodiment, the gate pitch and the metal pitch are set to 2F (F is the minimum processing size) as shown by a dotted line D in FIG. In addition, it is possible to read and write 2-bit information per memory cell, so that the cell area per bit is 2F. ² It can be. Therefore, the cell area can be greatly reduced as compared with the conventional memory cell.
[0047]
In the present embodiment, the source / drain regions are formed in the semiconductor substrate. However, the source / drain regions may be formed by providing low-concentration well regions in the semiconductor substrate. In this case, the conductivity type of the well region is opposite to that of the source / drain region, but the conductivity type of the semiconductor substrate is not limited.
[0048]
Further, the film thickness, film type, and the like described in the present embodiment are not limited to those described above. Further, the voltage to be applied should be determined optimally according to the film thickness and application to be used, and is not limited to the above-mentioned value.
<Second embodiment>
The memory cell array of the present embodiment is different from the first embodiment in that the second bit line has a portion made of a high melting point metal. The rest has substantially the same structure as that of the first embodiment, and a detailed description of the same parts will be omitted. The circuit diagram of the memory cell array of this embodiment is exactly the same as that of FIG.
[0049]
FIG. 6 is a schematic plan view of the memory cell array, and FIGS. 7 and 8 are schematic cross-sectional views taken along line AA ′ and line BB ′ in FIG.
[0050]
In the memory cell array according to the present embodiment, the refractory metal layer 213 corresponds to the first layer metal 118 (second bit line) in FIG. Examples of the high melting point metal include WSi and TiSi ₂ And the like.
[0051]
6 to 8, 201 is a semiconductor substrate, 202 is a silicon oxide film, 203 is a silicon nitride film, 204 is a silicon oxide film, 205 and 206 are charge holding regions, 207 is a gate electrode, 208, 209, 210 and 211. Is a diffusion region, 212 is a gate sidewall insulating film, 214 is a silicon oxide film, 215 is a silicon nitride film, 216 is a first interlayer insulating film, 217 is a contact, and 218 is a first layer metal (first bit line). .
[0052]
In the present embodiment, since the high melting point metal is used for the bit line wiring, the number of metal wiring layers can be reduced. Therefore, even if miniaturization is advanced to increase the degree of integration, it is possible to suppress the step shape from being deteriorated due to the overlapping of the metal wirings. Therefore, miniaturization of the memory cell array is facilitated. Furthermore, by using a high melting point metal, a low resistance can be realized even if the source / drain region (diffusion region) is made shallow, so that the operation of the memory cell array can be sped up.
<Third embodiment>
The memory cell array according to the present embodiment is different from the first embodiment in that charges are accumulated in a charge retaining film in a memory function body provided on a side wall of a gate electrode. That is, the function of retaining charges is provided not in the gate insulating film but in the gate sidewall insulating film. Further, the diffusion region and the gate electrode do not overlap. The rest has substantially the same structure as that of the first embodiment, and a detailed description of the same parts will be omitted. The circuit diagram of the memory cell array of this embodiment is exactly the same as that of FIG.
[0053]
9 is a schematic plan view of the memory cell array, and FIG. 10 is a schematic cross-sectional view taken along the line AA ′ of FIG.
[0054]
9 and 10, reference numeral 301 denotes a semiconductor substrate, 302 denotes a silicon oxide film (gate insulating film), 303 denotes a gate electrode, 304 denotes a silicon oxide film, 305 denotes a silicon nitride film, and 306, 307, 308, and 309 denote diffusion regions. , 310 is a silicon oxide film, 311 is a silicon nitride film, 312 is a first interlayer insulating film, 313 and 314 are contacts, 315 is a first layer metal, 316 is a second interlayer metal, and 317 is a second layer metal. .
[0055]
On the side wall of the gate electrode 303, a memory function body (consisting of a silicon oxide film 304 and a silicon nitride film 305) in the form of a side wall insulating film is formed. The silicon nitride film 305 has a function of storing charges, and the silicon oxide film 304 has a function of preventing the stored charges from being dissipated.
[0056]
The diffusion regions 306, 307, 308, and 309 do not overlap with the gate electrode 303 as shown in FIG. That is, the end of the diffusion region does not reach the end of the gate electrode, and has a so-called offset structure (offset region). For this reason, the likelihood of occurrence of the inversion layer in the offset region changes depending on the amount of charge accumulated in the silicon nitride film 305, and is detected as a current difference flowing through the memory element.
[0057]
Since the gate oxide film 302 does not need to have a function of accumulating charges, it can be made sufficiently thin. Therefore, it is easy to miniaturize the memory element, and the memory cell array can be highly integrated.
[0058]
Further, the present memory element can be formed by a process having a very high affinity with a normal field-effect transistor constituting a logic circuit. In other words, the mixed mounting process of the logic circuit and the memory cell array is easy. This is because the memory function body (consisting of the silicon oxide film 304 and the silicon nitride film 305) of the present memory element can be used as it is as a gate sidewall insulating film of a normal field-effect transistor. However, in an ordinary field effect transistor, it is necessary to form an extension or an LDD (Lightly Doped Drain).
[0059]
Incidentally, it is preferable that the insulating film having a function of accumulating electric charges be a silicon nitride film. This is because the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0060]
The operation method of the memory cell array according to the present embodiment is the same as that of the first embodiment.
(Details of the memory element used in the third embodiment)
The memory element constituting the semiconductor memory device of the present invention is mainly arranged across a first conductivity type region which is a diffusion region, a second conductivity type region, and a boundary between the first and second conductivity type regions. Or a gate electrode formed on a gate insulating film, a gate electrode formed on the gate insulating film, and both sides of the gate electrode. Memory function body, a source / drain region (diffusion region) disposed on the opposite side of the memory function body from the gate electrode, and a channel region disposed below the gate electrode.
[0061]
This memory element functions as a memory element for storing quaternary or more information by storing binary or more information in one charge holding film, and also has a variable resistance effect by a memory function body. , Also functions as a memory cell having both functions of a selection transistor and a memory transistor. However, this memory element does not necessarily need to store and function quaternary information or more, and may function by storing binary information, for example.
[0062]
The semiconductor device of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type well region formed in the semiconductor substrate.
[0063]
The semiconductor substrate is not particularly limited as long as it is used for a semiconductor device. For example, a bulk substrate made of an element semiconductor such as silicon and germanium, a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, and GaN. Is mentioned. In addition, as a substrate having a semiconductor layer on its surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer over a glass or plastic substrate may be used. Among them, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.
[0064]
An element isolation region is preferably formed on the semiconductor substrate or the semiconductor layer, and elements such as a transistor, a capacitor, and a resistor, a circuit including the elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multiple element. It may be formed in a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and the semiconductor substrate preferably has at least one well region of a first conductivity type (P-type or N-type). . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, or a body region may be provided below the channel region.
[0065]
The gate insulating film or the insulating film is not particularly limited as long as it is usually used for a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, A single-layer film or a stacked film of a high dielectric film such as a tantalum oxide film or a hafnium oxide film can be used. Among them, a silicon oxide film is preferable. The thickness of the gate insulating film is, for example, about 1 to 20 nm, preferably about 1 to 6 nm. The gate insulating film may be formed only immediately below the gate electrode, or may be formed larger (wider) than the gate electrode.
[0066]
The gate electrode or the electrode is formed on the gate insulating film in a shape usually used for a semiconductor device or a shape having a concave portion at a lower end. Note that a single gate electrode means a gate electrode which is formed as an integral shape without being separated by a single-layer or multilayer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. The gate electrode is not particularly limited as long as it is generally used for a semiconductor device, and a conductive film, for example, a metal such as polysilicon: copper and aluminum: a high melting point metal such as tungsten, titanium, and tantalum: A single-layer film or a laminated film of silicide or the like with a high melting point metal may be used. The gate electrode is preferably formed to have a thickness of, for example, about 50 to 400 nm. Note that a channel region is formed below the gate electrode.
[0067]
The memory function body is configured to include at least a film or a region having a function of retaining charges, having a function of storing and retaining charges, trapping charges, or retaining a charge polarization state. Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectric substances such as hafnium oxide, zirconium oxide, and tantalum oxide; zinc oxide; Body; metal and the like. The memory function body includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer therein; an insulator film including one or more conductors or semiconductor dots; It can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. Above all, the silicon nitride film has a large hysteresis characteristic due to the presence of many levels for trapping electric charges, and has a long charge retention time and does not cause a problem of charge leakage due to generation of a leak path. Is preferable, and is a material used as a standard in the LSI process.
[0068]
By using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability regarding storage and holding can be improved. This is because, since the silicon nitride film is an insulator, even if a charge leaks to a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. Furthermore, when a plurality of memory elements are arranged, even if the distance between the memory elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of a conductor. No lost information is lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the memory element.
In order to further increase the reliability of memory retention, the insulating film having a function of retaining charges does not necessarily have to be in the form of a film, and insulators having a function of retaining charges are discretely present in the insulating film. Is preferred. Specifically, it is preferable that the material is dispersed in a dot shape in a material that does not easily retain charge, for example, silicon oxide.
[0069]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0070]
Further, by using an insulator film containing one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0071]
Further, a ferroelectric film such as PZT or PLZT whose polarization direction changes by an electric field may be used as the memory function body. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to the polarization, and are maintained in that state. Therefore, a hysteresis characteristic similar to that of a film that is supplied with electric charge from outside the film having a memory function and traps electric charge can be obtained, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since the hysteresis characteristic can be obtained only by the polarization of the electric charge in the film, there is an effect that writing / erasing can be performed at high speed.
[0072]
That is, it is preferable that the memory function body further include a region that makes it difficult for the charge to escape or a film that has a function of making the charge hard to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0073]
The charge retaining film included in the memory function body is formed directly or on both sides of the gate electrode via an insulating film, and also directly on the semiconductor substrate (well region, body region, or via the gate insulating film or the insulating film). (Source / drain region or diffusion region). The charge retention films on both sides of the gate electrode are preferably formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed so as to completely or partially fill the concave portion directly or via an insulating film.
[0074]
The gate electrode is preferably formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the memory element is facilitated. Further, a memory element having such a simple arrangement is easy to manufacture and can improve the yield.
[0075]
In the case where a conductive film is used as the charge holding film, the charge holding film is provided with an insulating film interposed therebetween so as not to directly contact the semiconductor substrate (the well region, the body region, the source / drain region, or the diffusion region) or the gate electrode. Is preferred. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in an insulating film, a structure in which a part is arranged in a side wall insulating film formed on a side wall of a gate, and the like are given. .
[0076]
The source / drain regions are arranged on the opposite side of the charge holding film from the gate electrode as diffusion regions of a conductivity type opposite to that of the semiconductor substrate or the well region. The junction between the source / drain region and the semiconductor substrate or the well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that in the case where an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have the following junction depth.
[0077]
The source / drain region may be arranged so as to overlap with the gate electrode end, may be arranged so as to coincide with the gate electrode end, or may be arranged offset from the gate electrode end. You may. In particular, in the case of offset, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region below the charge retaining film greatly changes depending on the amount of charge accumulated in the memory function body, and the memory effect is reduced. It is preferred because it increases and brings about a reduction in the short channel effect. However, if the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset amount is larger than the thickness of the charge holding film in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the nearer source / drain region is shorter. What is particularly important is that at least a part of the charge storage region in the memory function body overlaps with a part of the source / drain region which is a diffusion region. The essence of the memory element constituting the semiconductor memory device of the present invention is that the memory is rewritten by the electric field crossing the memory function body due to the voltage difference between the gate electrode and the source / drain region existing only on the side wall of the memory function body. That's why.
[0078]
The source / drain region may partially extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high-melting point metals. Among them, polysilicon is preferable. This is because polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so that it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate, and it is easy to suppress the short channel effect. . In this case, it is preferable that a part of the source / drain region is disposed so as to sandwich at least a part of the memory function body together with the gate electrode.
[0079]
The memory element of the present invention can be formed by a normal semiconductor process, for example, by a method similar to the method of forming a single-layer or stacked-layer sidewall spacer on the side wall of a gate electrode. Specifically, after forming a gate electrode or an electrode, a single layer including a charge holding film such as a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, and an insulating film / charge holding film / insulating film. A method of forming a film or a laminated film, etching back under appropriate conditions to leave these films in the form of sidewall spacers; forming an insulating film or a charge retaining film, and etching back under appropriate conditions to form a sidewall. A method in which a charge retaining film or an insulating film is formed in the form of a spacer, and then etched back in the same manner to leave a sidewall spacer; a semiconductor substrate including a gate electrode formed of an insulating film material in which a particulate charge retaining material is dispersed A method of applying or depositing on the upper surface and etching back under appropriate conditions to leave the insulating film material in a side wall spacer shape; after forming a gate electrode, forming the single-layer film or the laminated film and forming a mask A method in which patterning and the like using. Before forming a gate electrode or an electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, and the like are formed, and a channel region of these films is formed. An opening is formed in a region to be formed, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
When a memory cell array is configured by arranging the memory elements of the present invention, the best mode of the memory element is, for example, (1) the gate electrodes of a plurality of memory elements have the function of a word line integrally; ▼ A memory function body is formed on both sides of the word line. 3) An insulator, particularly a silicon nitride film, holds electric charges in the memory function body. 4) ONO (Oxide) (Nitride Oxide) film, and the silicon nitride film has a surface substantially parallel to the surface of the gate insulating film. (5) The silicon nitride film in the memory function body is a silicon oxide film with a word line and a channel region. {Circle around (6)} The silicon nitride film and the diffusion layer in the memory function overlap each other, {circle around (7)} the silicon having a surface substantially parallel to the surface of the gate insulating film The thickness of the insulating film separating the nitride film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film. (8) Writing and erasing operations of one memory element are performed by a single word line. ▼ There is no electrode (word line) having a function of assisting the writing and erasing operations on the memory function body. (10) The conductivity type opposite to the conductivity type of the diffusion region is provided immediately below the memory function body in contact with the diffusion region. Having a region with a high impurity concentration. The best mode is the case where all the above requirements are satisfied. However, it is needless to say that all the above requirements need not be satisfied.
[0080]
When a plurality of the above requirements are satisfied, a particularly preferable combination exists. For example, (3) an insulator, particularly a silicon nitride film, holds electric charges in the memory function body, and (9) an electrode (word line) having a function of assisting a write and erase operation on the memory function body. And (6) the case where the insulating film (silicon nitride film) in the memory function body and the diffusion layer overlap. If the insulator holds the electric charge in the memory function body and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film ( It has been found that only when the silicon nitride film) and the diffusion layer overlap, the writing operation is performed favorably. That is, it has been found that when the requirements (3) and (9) are satisfied, the requirement (6) must be satisfied. On the other hand, when the electric charge is held in the memory function body by the conductor, the writing operation can be performed even when the conductor in the memory function body and the diffusion layer do not overlap (the conductor in the memory function body). Is to assist writing by capacitive coupling with the writing electrode). In addition, when there was an electrode having a function of assisting the writing and erasing operations on the memory function body, the writing operation could be performed even when the insulating film and the diffusion layer in the memory function body did not overlap. .
[0081]
However, in the case where it is an insulator, not a conductor, that retains electric charges in the memory function body, and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, A very large effect can be obtained.
[0082]
First, the bit line contact can be arranged closer to the memory function body on the side wall of the word line, or even if the distance between the memory elements is short, a plurality of memory function bodies do not interfere with each other and can hold the stored information. This facilitates miniaturization of the memory element. When the charge holding region in the memory function body is a conductor, interference occurs between the charge holding regions as the memory elements approach each other due to capacitive coupling, and storage information cannot be held.
When the charge holding region in the memory function body is an insulator (for example, a silicon nitride film), it is not necessary to make the memory function body independent for each memory cell. For example, memory function bodies formed on both sides of one word line shared by a plurality of memory cells do not need to be separated for each memory cell, and memory function bodies formed on both sides of one word line. Can be shared by a plurality of memory cells sharing a word line. Therefore, a photo and etching process for separating the memory function body is not required, and the manufacturing process is simplified. Further, a margin for alignment of a photo and a margin for reducing the thickness of an etching film are not required, so that a margin between memory cells can be reduced. Therefore, as compared with the case where the charge holding region in the memory function body is a conductor (for example, a polycrystalline silicon film), even if formed at the same fine processing level, there is an effect that the memory cell occupation area can be reduced (memory If the charge holding region in the functional body is a conductor, a photo and etching step for separating the memory functional body for each memory cell is required, and a photo alignment margin and an etching film reduction margin are required.
[0083]
Furthermore, since there is no electrode having the function of assisting the writing and erasing operations on the memory function body and the element structure is simple, the number of steps is reduced, the yield is improved, and the transistors forming the logic circuit and the analog circuit are formed. Can be easily combined.
[0084]
Further, as a very important design matter, the case where the charge holding region in the memory function body is an insulator and there is no electrode having a function of assisting the writing and erasing operations on the memory function body (the above two conditions) Is very effective in reducing the cell occupation area, improving the yield by simplifying the manufacturing method, and reducing the cost.) We have found that wrapping allows writing and erasing at very low voltages. Specifically, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less. This function has a very large effect on circuit design. That is, since it is not necessary to generate a high voltage in a chip as in a flash memory, it is possible to omit a charge pumping circuit requiring an enormous occupation area or to reduce the scale. In particular, when a small-capacity memory is incorporated in a logic LSI for adjustment, the occupied area of the memory section is dominated by the occupied area of the peripheral circuit that drives the memory cell rather than the memory cell. Eliminating or reducing the scale of the booster circuit is most effective for reducing the chip size.
From the above, it is particularly preferable to satisfy the requirements (3), (9) and (6).
[0085]
【The invention's effect】
According to the first aspect of the present invention, a transistor having a specific memory function can be selected by selecting a specific word line and a first bit line. Furthermore, since the potentials applied to the first bit line and the second bit line can be controlled independently for each line, the leakage current from the non-selected memory cell during the read operation of the selected memory cell can be controlled. , And a good read operation can be performed. Further, since the influence of the leak current of the unselected memory cells can be effectively suppressed, the number of memory cells connected to the bit line can be increased, and the integration degree of the memory cell array can be improved.
[0086]
Further, the semiconductor memory device according to the second aspect of the invention also has the same operation and effect as the semiconductor memory device according to the first aspect.
[0087]
In one embodiment, the film having a memory function is a silicon film, and the silicon film is electrically separated from a word line and a channel region by an insulating film, and specifies a material forming the film having a memory function. .
[0088]
In one embodiment, since the silicon film is polycrystalline silicon, and the polycrystalline silicon film is the most commonly used material in the LSI manufacturing process, the process can be easily constructed.
In one embodiment, the transistor having the memory function stores two bits of information with one transistor, so that the cell area per bit is significantly reduced. Therefore, the degree of integration of the memory cell array can be improved.
[0089]
In one embodiment, a specific structure in which an insulating film having a memory function is provided and one transistor stores 2-bit information is shown. Since an insulating film having a memory function is used, charges can be locally stored in the insulating film, and 2-bit storage can be performed.
[0090]
In one embodiment, the insulating film having a memory function is a silicon nitride film, and the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0091]
According to one embodiment, the charge holding film having a function of accumulating charges is formed in the memory function body formed on both sides of the word line, so that the transistor can be easily miniaturized. . Therefore, the degree of integration of the memory cell array can be improved.
[0092]
Further, it can be formed by a process which has a very high affinity with a normal field-effect transistor forming a memory element and a logic circuit. In other words, the mixed mounting process of the logic circuit and the memory cell array is easy.
[0093]
In one embodiment, the charge retention film is a silicon nitride film, and the silicon nitride film has a large number of levels for capturing electric charges, so that the memory effect can be increased. Further, since the silicon nitride film is a material used as a standard in the LSI manufacturing process, the process can be easily constructed.
[0094]
In one embodiment, at least one of the first bit line and the second bit line includes a portion made of a high melting point metal, so that the number of metal wiring layers can be reduced. . Therefore, even if miniaturization is advanced to increase the degree of integration, it is possible to suppress the step shape from being deteriorated due to the overlapping of the metal wirings. Therefore, miniaturization of the memory cell array is facilitated. Furthermore, by using a high melting point metal, a low resistance can be realized even if the source / drain region (diffusion region) is made shallow, so that the operation of the memory cell array can be sped up.
[0095]
Further, according to the embodiment, it is possible to reduce the influence of off-leak of the non-selected memory cell. Further, it is possible to prevent a non-selected memory cell connected to the word line from being turned on and causing a current to flow, thereby changing the potential of the second bit line.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a memory cell array according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA ′ of the schematic plan view shown in FIG.
FIG. 3 is a sectional view taken along line BB ′ of the schematic plan view shown in FIG. 1;
4 is a horse head at CC ′ of the schematic plan view shown in FIG. 1. FIG.
FIG. 5 is a circuit diagram of a memory cell array according to the present invention.
FIG. 6 is a schematic plan view of a memory cell array according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view taken along the line AA ′ of the schematic plan view shown in FIG. 6;
8 is a cross-sectional view taken along the line BB 'of the schematic plan view shown in FIG.
FIG. 9 is a schematic plan view of a memory cell array according to a third embodiment of the present invention.
FIG. 10 is a cross-sectional view taken along the line AA ′ of the schematic plan view shown in FIG. 9;
FIG. 11 is a schematic plan view of a conventional memory cell array.
FIG. 12 is a sectional view taken along line AA ′ of FIG. 11;
FIG. 13 is a circuit diagram of a memory cell array of a conventional semiconductor memory device.
[Explanation of symbols]
101 ... Semiconductor substrate
102, 104, 113: silicon oxide film
103 ... Charge holding film
105, 106: regions where electric charges are held
107 ... Gate electrode
108, 109, 110, 111 ... source / drain regions
112 ... sidewall film
114 ... Silicon nitride film
115 ... First interlayer insulating film
120 ... second metal
121 ... element isolation region

Claims (11)

In a semiconductor memory device in which a plurality of transistors having a memory function are arranged in a matrix on a semiconductor substrate,
The transistor has two diffusion regions serving as source / drain regions,
The gate electrodes of the transistors arranged in the row direction are connected to each other by a word line,
One of the diffusion regions of the transistors arranged in the column direction is connected to each other by a first bit line,
The other of the diffusion regions of the transistors arranged in the row direction is connected to each other by a second bit line. In a semiconductor memory device in which a plurality of transistors having a memory function are arranged on a semiconductor substrate,
On the surface of the semiconductor substrate of the first conductivity type, element isolation regions extending in a first direction are formed side by side in a second direction intersecting the first direction, and are respectively formed between adjacent element isolation regions. An active region extending in the first direction is defined;
In each of the active regions, first diffusion regions and second diffusion regions are alternately formed,
A channel region is defined between the adjacent first diffusion region and second diffusion region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate so as to pass over a channel region in each of the active regions.
On the semiconductor substrate, a plurality of first bit lines extending in the first direction are connected to first underlying diffusion regions, respectively.
A plurality of second bit lines extending in the second direction are provided on the semiconductor substrate so as to pass over the second diffusion region, and are respectively connected to the corresponding second diffusion regions. A semiconductor memory device characterized by the above-mentioned. A film having a memory function is provided above the channel region and below a word line in a region where the word line intersects. The film having a memory function is a silicon film. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is electrically separated from a channel region. 4. The semiconductor memory device according to claim 3, wherein said silicon film is polycrystalline silicon. 3. The semiconductor memory device according to claim 1, wherein the transistor having the memory function is a single transistor and stores 2-bit information. 3. The semiconductor memory device according to claim 2, wherein an insulating film having a memory function is provided below the word line on the active region where the channel region intersects with the word line. 7. The semiconductor memory device according to claim 6, wherein said insulating film having a memory function is a silicon nitride film. 3. The memory function body is formed on both sides of a portion of the word line on the channel region, and the memory function body includes a charge holding film having a function of accumulating charges. Semiconductor storage device. 9. The semiconductor memory device according to claim 8, wherein said charge holding film is a silicon nitride film. 3. The semiconductor memory device according to claim 2, wherein at least one of the first bit line and the second bit line includes a portion made of a high melting point metal. In the above semiconductor memory device,
A voltage V1 is applied to a word line connected to the selected memory cell,
A voltage V2 is applied to the first bit line connected to the selected memory cell,
A voltage V3 is applied to a second bit line connected to the selected memory cell,
Applying a voltage V3 to a first bit line other than the first bit line connected to the selected memory cell,
By applying the voltage V2 to a second bit line other than the second bit line connected to the selected memory cell,
3. The semiconductor memory device according to claim 2, wherein a read operation of the memory cell is performed.

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