JP2004342810A - Compound semiconductor device - Google Patents

Abstract

Provided is a compound semiconductor device capable of stabilizing the potential of a channel and efficiently removing holes accumulated in the channel in an FET having an AlGaN / GaN heterostructure.
A buffer layer having P-type conductivity is epitaxially grown on a conductive substrate. An electron transit layer made of GaN is formed on the buffer layer. An electron supply layer made of N-type AlGaN or N-type AlN is formed on the electron transit layer. A gate electrode is formed on the electron supply layer. A source electrode and a drain electrode that are ohmic-connected to the electron transit layer are arranged on both sides of the gate electrode.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a compound semiconductor device, and more particularly to a field effect transistor (FET) using GaN for an electron transit layer and using AlGaN or AlN for an electron supply layer.
[0002]
[Prior art]
In recent years, FETs using a two-dimensional electron gas having an AlGaN / GaN heterostructure using a substrate such as sapphire or SiC have been actively developed. Since the band gap of GaN is as large as 3.4 eV, the breakdown voltage can be increased and high-voltage operation can be performed by using GaN for the semiconductor device.
[0003]
FIG. 6 shows a cross-sectional view of a conventional AlGaN / GaN-based FET. An AlGaN buffer layer 102, a GaN electron transit layer 103, and an N-type AlGaN electron supply layer 104 are laminated in this order on a substrate 101 made of sapphire or semi-insulating SiC.
[0004]
A Schottky gate electrode 105 is formed on the electron transit layer 104, and a source electrode 106 and a drain electrode 107 are formed on both sides thereof. In the surface of the electron supply layer 104, a region between the gate electrode 105 and the source electrode 106 and a region between the gate electrode 105 and the drain electrode 107 are covered with the protective film 108.
[0005]
A metal layer 109 is formed on the bottom surface of the substrate 101, and the metal layer 109 is in close contact with the package 100. Source electrode 106 and package 100 are electrically connected by wire 111. Package 100 is grounded.
[0006]
The metal layer 109 formed on the bottom surface of the substrate 101 is grounded via the package 100. When the drain voltage fluctuates, the number of lines of electric force exiting from the drain electrode 107 fluctuates. Since the substrate 101 is semi-insulating, the number of lines of electric force that enter the substrate 101 also varies. This means that the potential of the electron transit layer 103 immediately below the gate electrode 105 is not stable.
[0007]
A buffer layer 102 is inserted to alleviate a large lattice mismatch between the substrate 101 and the electron transit layer 103 and to enhance the adhesion. However, many defects exist in the buffer layer 102, and as a result, many trap levels are formed. Further, the buffer layer 102 also becomes a factor that makes the potential of the electron transit layer 103 unstable.
[0008]
When a voltage is applied between the source electrode 106 and the drain electrode 107, the lines of electric force generated from the drain electrode 107 concentrate on the end of the gate electrode 105, and the breakdown voltage decreases.
[0009]
The electrons accelerated during the high-voltage operation excite electrons in the valence band (collision ionization), so that electron-hole pairs are generated in the electron transit layer 103. Some of the generated holes flow to the gate electrode 105, but a positive feedback phenomenon occurs in which holes accumulated in the channel increase electrons in the channel. There is a concern that dielectric breakdown may occur due to this positive feedback phenomenon.
[0010]
GaN having a large band gap is advantageous in that impact ionization is unlikely to occur, but it is preferable to suppress the accumulation of holes in the channel in order to prevent dielectric breakdown. In the case of a MOSFET using silicon, even though the band gap of silicon is as small as 1.1 eV, holes can be efficiently removed from the channel by introducing a P-type layer or using a P-type substrate. High voltage operation is realized.
[0011]
However, since the substrate 101 is semi-insulating, it is difficult to efficiently extract holes in the electron transit layer 103.
[0012]
[Non-patent document 1]
A. T. Ping et. al. , DC and Microwave Performance of High-Current AlGaN / GaN Heterostructure Field Effect Transistors Growth on Electronic Components, Electronic Components, Electronic Components, Electronic Devices. 19, No. 2, p. 54-57
[0013]
[Problems to be solved by the invention]
An object of the present invention is to provide a compound semiconductor device capable of stabilizing the potential of a channel and efficiently removing holes accumulated in the channel in an FET having an AlGaN / GaN heterostructure. is there.
[0014]
[Means for Solving the Problems]
According to one aspect of the present invention, a conductive substrate, a buffer layer epitaxially grown on the substrate and having P-type conductivity, an electron transit layer made of GaN formed on the buffer layer, An electron supply layer made of N-type AlGaN or N-type AlN formed on the electron transit layer; a gate electrode formed on the electron supply layer; Provided is a compound semiconductor device having a source electrode and a drain electrode that are ohmic-connected to a traveling layer.
[0015]
Since the conductive substrate and the buffer layer are used, the potential of the electron transit layer can be stabilized as compared with the case where an insulating or semi-insulating substrate or a buffer layer is used. In addition, since the buffer layer is P-type, holes generated in the electron transit layer can be drawn out to the substrate.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view of a compound semiconductor device (HEMT) according to the first embodiment. A 300 nm thick buffer layer 2 made of P-type AlGaN is formed on a main surface of a substrate 1 made of P-type conductive SiC. The P-type dopant of the buffer layer 2 is Mg, and its concentration is, for example, 2 × 10 ¹⁷ cm ⁻³ .
[0017]
On the buffer layer 2, an electron transit layer 3 made of undoped GaN and having a thickness of 3 μm is formed. An electron supply layer 4 made of N-type Al _0.25 Ga _0.75 N and having a thickness of 20 nm is formed thereon. The dopant of the electron supply layer 4 is Si, and its concentration is, for example, 2 × 10 ¹⁸ cm ⁻³ . These layers can be deposited by known metal organic chemical vapor deposition (MOCVD).
[0018]
A gate electrode 5 is formed on a part of the electron supply layer 4. The gate electrode 5 has a two-layer structure in which a Ni layer and an Au layer are stacked in this order, and makes a Schottky contact with the electron supply layer 4. On both sides of the gate electrode 5, a source electrode 6 and a drain electrode 7 are arranged at an interval from the gate electrode 5. The source electrode 6 and the drain electrode 7 have a two-layer structure in which a Ti layer and an Al layer are laminated in this order, and are connected to the electron transit layer 3 in ohmic contact.
[0019]
A region between the gate electrode 5 and the source electrode 6 and a region between the gate electrode 5 and the drain electrode 7 on the surface of the electron supply layer 4 are covered with a protective film 8 made of silicon nitride (SiN). ing.
[0020]
Hereinafter, a method for forming the gate electrode 5, the source electrode 6, the drain electrode 7, and the protective film 8 will be described. A resist film is formed on the surface of the electron supply layer 4, and openings are formed at positions where the source electrode 6 and the drain electrode 7 are to be arranged. A Ti layer and an Al layer are sequentially deposited, and the resist film is removed. As a result, the source electrode 6 and the drain electrode 7 remain. Heat treatment is performed at 450 to 900 ° C. to obtain ohmic contact.
[0021]
A 20-nm-thick silicon nitride film is deposited on the entire surface by CVD. A resist film is formed on the silicon nitride film, and an opening is formed in a region where the gate electrode 5 is to be arranged. Using the resist film as an etching mask, the silicon nitride film in the region where the gate electrode 5 is to be arranged is etched. An Ni layer and an Au layer are sequentially deposited on the entire surface. The resist film is removed, leaving the gate electrode 5.
[0022]
On the bottom surface of the substrate 1, a metal layer 9 is formed. The metal layer 9 has a two-layer structure of a Ti layer and an Au layer, and is formed by vapor deposition. When depositing the metal layer 9, the surface on which the gate electrode 5, the source electrode 6, and the drain electrode 7 are formed is covered with a resist film.
[0023]
This HEMT is mounted on the package 10 such that the metal layer 9 is in close contact with the package 10. Source electrode 6 is connected to package 10 by wire 11.
[0024]
In the first embodiment, SiC having P-type conductivity is used as the substrate 1. Further, the buffer layer 2 disposed between the substrate 1 and the electron transit layer 3 also has P-type conductivity. Since the electron transit layer 3 is connected to the package 10 via the buffer layer 2, the substrate 1, and the metal layer 9, the potential of the electron transit layer 3 can be stabilized. In order to obtain a sufficient effect of stabilizing the potential of the electron transit layer 3, the thickness of the substrate 1 is preferably set to 200 μm or less. Also, making the substrate thinner is effective in terms of heat radiation. From the viewpoint of heat radiation, it is more preferable that the thickness of the substrate 1 be 100 μm or less. The resistivity of the P-type SiC substrate 1 is in the range of 0.1 to 100000 Ωcm.
[0025]
Some of the lines of electric force generated from the drain electrode 7 reach the gate electrode 5, but most of the lines of electric force are terminated by the conductive buffer layer 2 and the substrate 1. For this reason, the concentration of the lines of electric force on the gate electrode 5 is reduced, and it is possible to prevent a decrease in the withstand voltage due to the concentration of the lines of electric force.
[0026]
Since the substrate 1 is made of P-type SiC, compared to the case of using semi-insulating SiC, the electrons in the two-dimensional electron gas layer formed at the interface between the electron transit layer 3 and the electron supply layer 4 are reduced. The potential barrier when looking at the substrate 1 side increases. Therefore, electrons reach the drain without leaking from the two-dimensional electron gas layer. Conversely, holes generated in the electron transit layer 3 easily move to the substrate 1. Therefore, the accumulation of holes in the electron transit layer 3 can be suppressed. As a result, the pinch-off characteristics are improved, the breakdown voltage is increased, and higher voltage operation can be realized.
[0027]
Generally, a P-type SiC substrate has a lower defect (micropipe) density than a semi-insulating SiC substrate. By using P-type SiC as the material of the substrate 1, it is possible to reduce a leak current via a defect.
[0028]
When an InAlGaN layer is grown on a SiC substrate, the growth due to the strain caused by the difference in lattice constant is not a flat two-dimensional growth but an island-like three-dimensional growth at the beginning of growth. Usually, this layer is used as a buffer layer, and an electron transit layer is grown thereon. However, in this buffer layer, the level due to vacancies generated at lattice positions of N atoms (trap level lower than the conduction band bottom by about 0.8 V) and the vacancies generated at lattice positions of Al atoms and Ga atoms are present. Level (a trap level higher by about 0.5 V from the upper end of the valence band) and the like. When carriers enter or leave these levels, the potential of the buffer layer fluctuates. The entry and exit of this carrier correspond to the movement of the Fermi level.
[0029]
If a P-type dopant such as Mg, Zn, or C is doped during the growth of the buffer layer, the Fermi level moves to the valence band side. Depending on the concentration of the P-type dopant, the Fermi level may exist in the valence band. A large number of holes (the hole concentration is sufficiently higher than the defect level density) generated thereby always fill in the defect levels on the valence band side to prevent carriers from entering and leaving. The defect level on the conduction band side emits electrons, which are minority carriers, and remains empty. As a result, the potential of the buffer layer is stabilized.
[0030]
FIG. 2 shows the relationship between the thickness of the electron transit layer 3 and the gain of the HEMT at 2 GHz. The abscissa represents the thickness of the electron transit layer in the unit “μm”, and the ordinate represents the gain in the unit “dB”. The gain plotted in FIG. 2 indicates that the substrate 1 shown in FIG. 1 has a thickness of 300 μm, a relative dielectric constant of 10, a relative dielectric constant of the electron transit layer 3 of 9, and a pad connected to the gate electrode 5. The shape was obtained by calculation as a square of 100 μm × 100 μm. The calculation was performed on the assumption that the buffer layer 3 was not formed.
[0031]
When the thickness of the electron transit layer 3 is reduced, the parasitic capacitance between the gate pad and the substrate increases, so that the gain decreases. In the region where the thickness of the electron transit layer 3 is 3 μm or more, almost the same gain as in the case where the substrate is semi-insulating is obtained. By setting the thickness of the electron transit layer 3 to 3 μm or more, it is possible to prevent the high frequency characteristics from being deteriorated due to the P-type substrate 1.
[0032]
Next, a second embodiment will be described. In the first embodiment, P-type SiC is used as the material of the substrate 1, but in the second embodiment, N-type SiC is used. Other configurations are the same as those of the semiconductor device according to the first embodiment.
[0033]
Even if the substrate 1 is formed of N-type SiC, the buffer layer 2 is of P-type, so that the electrons in the two-dimensional electron gas layer formed at the interface between the electron transit layer 3 and the electron supply layer 4 can be used as the substrate 1. The potential barrier when looking at the side increases. Therefore, electrons reach the drain without leaking from the two-dimensional electron gas layer.
[0034]
The holes generated in the electron transit layer 3 move toward the P-type buffer layer 2. The holes that have reached the buffer layer 2 are recombined with electrons at the PN junction at the interface between the buffer layer 2 and the substrate 1. For this reason, the same effect as when the substrate 1 is formed of P-type SiC can be obtained. The P-type buffer layer 2 prevents electrons from being injected from the N-type substrate 1 into the electron transit layer 3.
[0035]
Generally, an N-type SiC substrate has a lower defect (micropipe) density than a semi-insulating SiC substrate. By using N-type SiC as the material of the substrate 1, it is possible to reduce leakage current via defects.
[0036]
The resistivity of a general P-type SiC substrate is 0.1 to 100,000 Ωcm, whereas the resistivity of an N-type SiC substrate is 0.001 to 1 Ωcm. By using an N-type SiC substrate having a low resistivity, the potential stability of the electron transit layer can be further improved.
[0037]
FIG. 3 is a sectional view of a compound semiconductor device according to the third embodiment. The laminated structure from the substrate 1 to the electron supply layer 4, the configurations of the gate electrode 5, the source electrode 6, the drain electrode 7, and the protective film 8 are the same as the configuration of the compound semiconductor device according to the first embodiment shown in FIG. It is.
[0038]
In the third embodiment, a buried electrode 15 is arranged beside the source electrode 6 (the side opposite to the gate electrode 5). The buried electrode 15 is made of, for example, Al and extends from the upper surface of the electron supply layer 4 to the upper surface of the P-type SiC substrate 1. A P-type impurity diffusion region 16 doped with Zn is formed at the interface between the buried electrode 15 and the electron transit layer 3, particularly at the interface on the gate electrode 5 side.
[0039]
Hereinafter, a method of forming the buried electrode 15 and the impurity diffusion region 16 will be described. After forming the source electrode 6 and the drain electrode 7 and performing a heat treatment for obtaining ohmic contact, a resist film is formed on the entire surface, and an opening is formed in a region where the embedded electrode 15 is to be arranged. Using the resist film as an etching mask, the upper surface of the substrate 1 is etched to form a concave portion. An Al layer is deposited so as to fill the recess, and the resist film is removed.
[0040]
A new resist film is formed, and an opening is formed near the embedded electrode 15. Zn ions are implanted through this opening to form an impurity diffusion region 16. After the implantation of Zn ions, heat treatment for activation is performed. Thereafter, as in the case of the first embodiment, the protective film 8, the gate electrode 5, and the metal layer 9 are formed.
[0041]
The FET is mounted on the package 10 so that the metal layer 9 is in close contact with the package 10. The source electrode 6 and the embedded electrode 15 are connected by a wire 17, and the embedded electrode 15 is connected to the package 10 by a wire 18.
[0042]
In the semiconductor device according to the third embodiment, holes generated in the electron transit layer 3 by impact ionization flow into the substrate 1 via the P-type impurity diffusion region 16 and the buried electrode 15. Therefore, the accumulation of holes in the electron transit layer 3 can be suppressed.
[0043]
FIG. 4 is a sectional view of a compound semiconductor device according to the fourth embodiment. In the semiconductor device according to the fourth embodiment, a P-type GaN layer 21 is inserted between the P-type AlGaN buffer layer 2 and the GaN electron transit layer 3 of the semiconductor device according to the first embodiment shown in FIG. ing. The thickness of the P-type GaN layer 21 is, for example, 100 nm, and the concentration of Mg, which is a P-type impurity, is, for example, 2 × 10 ¹⁷ cm ⁻³ . Other configurations are the same as those of the semiconductor device according to the first embodiment.
[0044]
By arranging the P-type GaN layer 21 below the electron transit layer 3, the effect of confining electrons at the interface between the electron transit layer 3 and the electron supply layer 4 can be enhanced. Further, holes generated in the electron transit layer 3 can be effectively extracted through the P-type GaN layer 21.
[0045]
FIG. 5 is a sectional view of a compound semiconductor device according to the fifth embodiment. In the semiconductor device according to the fifth embodiment, a P-type region 22 doped with Zn is formed in a part of the electron transit layer 3. The P-type region 22 is separated from the interface between the electron transit layer 3 and the electron supply layer 4 by a certain distance, and is in contact with the P-type AlGaAs buffer layer 2. The P-type region 22 is disposed between the gate electrode 5 and the drain electrode 7 when viewed from a line parallel to the normal to the surface of the substrate 1.
[0046]
The P-type region 22 is formed by growing the electron transit layer 3 and then implanting Zn ions into a deep portion thereof and performing a heat treatment for activation. After forming the P-type region 22, the electron supply layer 4 is deposited on the electron transit layer 3. Subsequent steps are the same as those of the semiconductor device according to the first embodiment.
[0047]
In the fifth embodiment, since the P-type region 22 is arranged only in a part, an increase in gate capacitance can be suppressed as compared with the case where the P-type region 22 is arranged on the entire surface. Further, since the P-type region 22 is disposed between the gate electrode 5 and the drain electrode 7, most of the lines of electric force coming out of the drain electrode 7 are terminated in the P-type region 22, and Concentration of electric lines of force can be suppressed.
[0048]
In the first to fifth embodiments, the buffer layer 2 is formed of P-type AlGaN, but may be formed of P-type AlN. The buffer layer 2 has a function of alleviating lattice mismatch between the substrate 1 and the electron transit layer 3. Therefore, it is preferable to use a material having a lattice constant equal to the lattice constant of the electron transit layer 3 as the material of the buffer layer 2. Note that even if a material having a lattice constant intermediate between the lattice constant of the substrate 1 and the lattice constant of the electron transit layer 3 can be used, the lattice mismatch can be reduced.
[0049]
The electron supply layer 4 may be formed of N-type AlN instead of N-type AlGaN. In the first to fifth embodiments, the substrate 1 made of conductive SiC is used. However, another metal substrate on which an AlGaN / GaN heterostructure can be grown, for example, a ZrB ₂ substrate or the like is used. It is also possible.
[0050]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0051]
From the above embodiments, the inventions described in the following supplementary notes are derived.
(Supplementary Note 1) A conductive substrate,
A buffer layer epitaxially grown on the substrate and having P-type conductivity;
An electron transit layer made of GaN formed on the buffer layer;
An electron supply layer made of N-type AlGaN or N-type AlN formed on the electron transit layer;
A gate electrode formed on the electron supply layer,
A compound semiconductor device having a source electrode and a drain electrode arranged on both sides of the gate electrode and ohmic-connected to the electron transit layer.
[0052]
(Supplementary Note 2) The compound semiconductor device according to supplementary note 1, wherein the substrate is formed of SiC.
(Supplementary Note 3) Further, an embedded electrode reaching from the upper surface of the electron supply layer to at least the upper surface of the substrate;
3. The compound semiconductor device according to claim 1, further comprising: a connection member that short-circuits the embedded electrode to the source electrode.
[0053]
(Supplementary Note 4) The buried electrode is disposed on the opposite side of the source electrode from the gate electrode,
The compound semiconductor device according to claim 3, further comprising an impurity diffusion region provided with P-type conductivity at an interface between the buried electrode and the electron supply layer.
[0054]
(Supplementary Note 5) The electron transit layer includes a P-type region doped with a P-type impurity, and the P-type region is disposed at a position away from an interface with the electron supply layer, and a bottom surface of the electron transit layer. 5. The compound semiconductor device according to any one of supplementary notes 1 to 4, wherein
[0055]
(Supplementary Note 6) The compound semiconductor device according to Supplementary Note 5, wherein the P-type region is disposed between the gate electrode and the drain electrode.
(Supplementary note 7) The compound semiconductor device according to any one of Supplementary notes 1 to 4, wherein a layer made of P-type conductive GaN is disposed between the substrate and the electron transit layer.
[0056]
(Supplementary Note 8) The compound semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the thickness of the electron transit layer is 3 µm or more.
(Supplementary note 9) The compound semiconductor device according to any one of supplementary notes 1 to 8, wherein the thickness of the substrate is 100 µm or less.
[0057]
(Supplementary Note 10) The compound semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the resistivity of the substrate is 0.001 to 100000 Ωcm.
[0058]
【The invention's effect】
As described above, according to the present invention, the potential of the electron transit layer can be stabilized by using the conductive substrate. Further, by disposing a P-type buffer layer between the substrate and the electron transit layer, it is possible to prevent electrons in the electron transit layer from leaking to the substrate.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.
FIG. 2 is a graph showing a relationship between a thickness of an electron transit layer and a gain.
FIG. 3 is a sectional view of a semiconductor device according to a third embodiment.
FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment.
FIG. 5 is a sectional view of a semiconductor device according to a fifth embodiment.
FIG. 6 is a cross-sectional view of a conventional semiconductor device having an AlGaN / GaN heterostructure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Electron transit layer 4 Electron supply layer 5 Gate electrode 6 Source electrode 7 Drain electrode 8 Protective film 9 Metal layer 10 Packages 11, 17, 18 Wire 15 Buried electrode 16 P-type impurity diffusion region 21 P-type GaN Layer 22 P-type region

Claims (5)

A conductive substrate;
A buffer layer epitaxially grown on the substrate and having P-type conductivity;
An electron transit layer made of GaN formed on the buffer layer;
An electron supply layer made of N-type AlGaN or N-type AlN formed on the electron transit layer;
A gate electrode formed on the electron supply layer,
A compound semiconductor device having a source electrode and a drain electrode arranged on both sides of the gate electrode and ohmic-connected to the electron transit layer. 2. The compound semiconductor device according to claim 1, wherein said substrate is formed of SiC. Furthermore, from the upper surface of the electron supply layer, an embedded electrode reaching at least the upper surface of the substrate,
The compound semiconductor device according to claim 1, further comprising: a connection member that short-circuits the embedded electrode to the source electrode. The buried electrode is disposed on the opposite side of the source electrode from the gate electrode,
The compound semiconductor device according to claim 3, further comprising an impurity diffusion region provided with P-type conductivity at an interface between the buried electrode and the electron supply layer. The electron traveling layer includes a P-type region doped with a P-type impurity, wherein the P-type region is disposed at a position away from an interface with the electron supply layer and reaches a bottom surface of the electron traveling layer. The compound semiconductor device according to any one of claims 1 to 4.

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