JP2004235254A - Infrared detector and manufacturing method thereof - Google Patents

Abstract

An infrared detector capable of easily removing a protective material for protecting a terminal such as a metal bump and a method for manufacturing the same.
A step of sequentially forming a lower contact layer and a multiple quantum well layer on a substrate, a step of forming a pixel isolation groove in the multiple quantum well layer, and a passivation layer in the pixel isolation groove. A step of forming an insulating layer) 11, a step of forming a first metal bump (terminal) 12a in a hole 11a of the passivation layer 11, a step of joining a semiconductor chip 14 to the first metal bump 12a, (Protective material) A step of etching and removing the substrate 1 while protecting the metal bumps 11 a with 15 and a step of removing the photoresist 15. The width of the pixel isolation groove 10 or the thickness of the passivation layer 11 is provided. Is set to a value at which the opening end of the pixel separation groove 10 is closed by the passivation layer 11.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an infrared detector and a method of manufacturing the same, and more particularly, to an infrared detector that detects infrared light using intersubband transition of a multiple quantum well and a method of manufacturing the same.
[0002]
[Prior art]
Infrared images are widely used for defense, crime prevention, medical equipment, heat monitoring devices in factories, environmental gas sensors, and the like, and various devices for obtaining infrared images have been studied. Above all, IRFPA (Infrared Focal Plane Array) has attracted attention as a key device capable of obtaining an infrared image with high spatial resolution and good detectability. The IRFPA is formed by integrating semiconductor photodiodes with a narrow gap, and uses each photodiode as one pixel. Since the atmosphere shows high transmittance in the far-infrared region, a HgCdTe photodiode is usually used for IRFPA to detect light in the far-infrared region. However, IRFPAs using HgCdTe photodiodes are more difficult to develop as the planar area of the device increases.
[0003]
Therefore, a quantum well infrared detector (QWIP; Quantum Well Infrared Photodetector) is mentioned as a candidate for a device having a larger detection area and higher performance than IRFPA. QWIP-FPA (QWIP Focal Plane Array) can be manufactured by a well-established technique for manufacturing a GaAs-based compound semiconductor today, and thus has low cost and good process reproducibility.
[0004]
Non-Patent Document 1 discloses that an element structure of QWIP-FPA is formed on a GaAs substrate, and a ROIC chip on which a readout integrated circuit (ROIC) is formed and the QWIP-FPA are flipped through metal bumps. It discloses that the GaAs substrate is removed by wet etching after chip bonding. When the GaAs substrate is removed in this manner, incident infrared rays are easily confined within one pixel, so that incident infrared rays are prevented from entering and exiting a plurality of pixels due to multiple reflection, and crosstalk between pixels is suppressed. .
[0005]
On the other hand, Non-Patent Document 2 discloses that in such a QWIP-FPA, GaAs is regrown in a window of a SiON layer and is used as a plug electrically connected to a GaAs substrate. .
[0006]
The QWIP-FPAs described in Non-Patent Documents 1 and 2 are cooling-type detectors, and are usually used by being housed in a sealed container whose inside is kept in a vacuum in order to improve cooling efficiency.
[0007]
As a technique different from the above, Patent Literature 1 discloses a technique in which an insulating layer is buried in a pixel isolation groove of a charge injection type charge transfer element to make it flat. Patent Document 2 discloses a technique in which a groove for element isolation is formed in a semiconductor substrate, an insulating layer containing impurities is formed in the groove, and the insulating layer is planarized.
[0008]
[Patent Document 1]
JP-A-60-88461 [Patent Document 2]
JP-A-7-74237 [Non-Patent Document 1]
H. Nishino et al. , "Sensitivity enhancement of quantum well infrared photodetector with a pseudo-random optical coupler by reference international reference. Infrared Technology and Applications XXV, SPIE vol. 3698, 574 (1999)
[Non-patent document 2]
Y. Matsukura et al. Quantum Well Infrared Photodetectors (QUIP) with Selective re-grown N-GaAs Plugs, Proc. Infrared Technology and Applications XXVII, SPIE vol. 4369, 481 (2001)
[0009]
[Problems to be solved by the invention]
By the way, according to the technology described in Non-Patent Document 1, when wet etching a GaAs substrate, a photo-mask is formed in a gap between the ROIC chip and the GaAs substrate so that a metal bump electrically connecting the ROIC chip and the QWIP-FPA is not etched. It is necessary to apply a protective material such as a resist so that the metal bumps do not come into contact with the etching solution. The photoresist is removed after the GaAs substrate has been etched.
[0010]
However, the above-mentioned photoresist penetrates the gap between the ROIC chip and the GaAs substrate by capillary action and enters the narrow pixel separation groove of the QWIP-FPA, so that the photoresist in the pixel separation groove is completely removed. Is difficult, and the photoresist remains in the pixel separation groove. In this case, the remaining photoresist becomes a source of degassing, the degree of vacuum in the sealed container deteriorates, and the reliability of the entire QWIP-FPA device is impaired. If it is attempted to completely remove the photoresist to avoid this inconvenience, it takes a long time to remove the photoresist, resulting in a new inconvenience that the manufacturing time of the QWIP-FPA becomes long.
[0011]
The present invention has been made in view of the problems of the conventional example, and provides an infrared detector capable of easily removing a protective material for protecting terminals such as metal bumps and a method for manufacturing the same. With the goal.
[0012]
[Means for Solving the Problems]
The above-described problems are caused by a lower contact layer having an exposed lower surface, a multiple quantum well layer formed on an upper surface of the lower contact layer, and a multiple quantum well layer formed in the multiple quantum well layer, and the multiple quantum well layer is separated for each pixel. A pixel isolation groove, an insulating layer formed in the pixel isolation groove and covering the multiple quantum well layer, a hole formed in the insulating layer, and at least a lower portion formed in the hole. An infrared detector comprising: a terminal electrically connected to the well layer; and a semiconductor chip bonded to the terminal, wherein an opening end of the pixel isolation groove is closed by the insulating layer. Solved by.
[0013]
Alternatively, the above-described problems may include forming a lower contact layer on or above a substrate, forming a multiple quantum well layer on the lower contact layer, and forming a pixel isolation groove in the multiple quantum well layer. Separating the multiple quantum well layer for each pixel, forming an insulating layer above the multiple quantum well layer and in the pixel isolation groove, forming a hole in the insulating layer, Forming at least a lower portion of a terminal electrically connected to the multiple quantum well layer in the hole, joining a semiconductor chip to the terminal, and providing a protective material between the semiconductor chip and the insulating layer Forming, removing the substrate by etching the substrate while protecting the terminals with the protective material, and removing the protective material, wherein the width of the pixel isolation groove or the insulating layer The film thickness of The values open end of the element separation groove is closed by the insulating layer, wherein the protective material is solved by the method of manufacturing an infrared detector, characterized in that to prevent from entering into the pixel isolation trench.
[0014]
Next, the operation of the present invention will be described.
[0015]
According to the present invention, since the opening end of the pixel separation groove is closed with the insulating layer so that the protection material does not enter the pixel separation groove, the protection material can be easily removed after the step of etching the substrate. In addition, the amount of the protective material remaining on the insulating layer is reduced. Thus, the degree of vacuum in the sealed container is prevented from increasing, and the characteristics of the entire infrared detector are improved.
[0016]
In addition, by using a passivation layer formed on the uppermost layer of the film formed above the multiple quantum well layer as an insulating film for preventing the pixel isolation groove, the groove as in Patent Documents 1 and 2 is used. It is not necessary to form a new insulating film for closing the gate, and the above advantage can be obtained without increasing the number of steps.
[0017]
Further, the insulating layer above the pixel isolation groove does not need to be completely flattened, and a depression reflecting the pixel isolation groove may be formed. In this case, the aspect ratio of the depression is 0 or more and 1 or more. By doing so, it is possible to prevent a protective material such as a photoresist from remaining in the depression.
[0018]
In order to close the opening end of the pixel separation groove as described above, it is practically preferable that the width of the pixel separation groove is 400 nm or less.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an infrared detector according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6 are cross-sectional views illustrating a method for manufacturing an infrared detector according to an embodiment of the present invention.
[0020]
First, steps required until a structure shown in FIG.
[0021]
First, a GaAs layer having a thickness capable of absorbing lattice defects and the like of the GaAs substrate 1, for example, a thickness of about 300 nm is formed on the GaAs substrate 1 by an organic metal growth method, and the buffer layer 2 is formed. Thereafter, an n-type GaAs layer is formed as a lower contact layer 3 on the buffer layer 2 to a thickness of about 1 μm by an organic metal growth method. The lower contact layer 3 is doped with silicon as an n-type impurity at a concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ .
[0022]
Subsequently, by a metal organic chemical vapor deposition method using trimethylgallium, trimethylaluminum, and arsine as a reaction gas, an AlGaAs layer having a composition of aluminum of 0.25 and a thickness of 30 nm, and 1 × of silicon as an n-type impurity were formed. The n-GaAs layer doped at a concentration of 10 ¹⁷ cm ⁻³ and having a thickness of 5 nm forms a multiple quantum well layer 4 having a required period, for example, 50 periods, which is repeated. The light receiving wavelength range of the multiple quantum well layer 4 is an infrared ray of 8 to 12 μm, but the present invention is not limited to an infrared detector that receives this wavelength range.
[0023]
Next, an n-type GaAs layer doped with silicon at a concentration of 1 × 10 ¹⁸ cm ⁻³ as an n-type impurity is formed on the multiple quantum well layer 4 to a thickness of about 200 nm by an organic metal growth method. The contact layer 5 is used.
[0024]
Thereafter, an n-type GaAs layer is formed as the semiconductor layer 6 to a thickness of about 650 nm on the upper contact layer 5 by metal organic chemical vapor deposition.
[0025]
Subsequently, as shown in FIG. 1B, the semiconductor layer 6 is patterned by a photolithography method to form optical coupling layers 6a and 6b having a surface having an uneven shape. The pattern of the optical coupling layers 6a and 6b is not limited. The etching may be performed up to the upper contact layer 5 as shown in the drawing, or the etching may be stopped in the middle of the semiconductor layer 6 so that the surface of the optical coupling layer 6a is uneven. , 6b. The optical coupling layers 6a and 6b are formed in groups for each of the pixels P1 and P2.
[0026]
Next, as shown in FIG. 1C, the multiple quantum well layer 4 and the upper contact layer 5 are patterned by photolithography to expose the lower contact layer 3 at the peripheral portion of the substrate 1.
[0027]
Next, steps required until a sectional structure shown in FIG.
[0028]
First, a resist pattern (not shown) having an electrode-shaped window is formed on the optical coupling layers 6a and 6b and on the exposed lower contact layer 3, and an AuGe layer is formed on the resist pattern and in the window by a vacuum deposition method. It is formed to a thickness of about 20 nm. Thereafter, an Au layer is formed on the AuGe layer to a thickness of about 50 nm by a vacuum evaporation method, and the resist pattern is removed by a lift-off method, so that the AuGe layer and the Au layer are left only in the windows. The remaining AuGe layer and Au layer are used as lower ohmic electrodes 7a and 7b on the lower contact layer 3, and are used as upper ohmic electrodes 8a and 8b on a part of the optical coupling layers 6a and 6b.
[0029]
Thereafter, as shown in FIG. 2B, a resist pattern (not shown) having a window in the shape of a reflective electrode is formed on the entire surface, and an Au layer is formed on the resist pattern and in the window by a vacuum deposition method to a thickness of about 5 mm. After being formed to a thickness of 100 nm, the resist pattern is removed by a lift-off method, and the Au layer is left only on each of the pixels P1 and P2 to be used as the reflection electrodes 9a and 9b.
[0030]
Next, as shown in FIG. 2C, a resist pattern (not shown) having a window in the shape of a pixel separation groove is formed on the reflective electrodes 9a and 9b and on the upper contact layer 5, and the resist pattern is used as a mask. The multiple quantum well layer 4 and the upper contact layer 5 are etched by the used plasma etching. As a result, a pixel separation groove 10 for separating the multiple quantum well layer 4 and the upper contact layer 5 for each of the pixels P1 and P2 is formed in these layers 4 and 5.
[0031]
In the present embodiment, the width of the pixel isolation groove 10 is formed to be smaller than 400 nm, and a mixed gas of SiCl ₄ and Cl ₂ is used as an etching gas for etching the multiple quantum well layer 4 and the upper contact layer 5. use. The plane size of each of the pixels P1 and P2 is approximately several tens μm × several tens μm, and 256 × 256 such pixels P1 and P2 are arranged in a plane.
[0032]
Next, as shown in FIG. 3A, a SiN layer is formed as a passivation layer 11 on the lower ohmic electrodes 7a and 7b, on the reflective electrodes 9a and 9b, and in the pixel isolation groove 10 by a CVD method (chemical vapor deposition). Method). The passivation layer 11 is an insulating layer formed on the uppermost layer of the film formed above the multiple quantum well layer 4, and functions to protect each layer thereunder from an external atmosphere.
[0033]
In the present embodiment, the passivation layer 11 is formed to such a thickness that the opening end of the pixel separation groove 10 is closed, but by setting the thickness on the reflective electrodes 9a and 9b to about 350 nm, The maximum thickness of the passivation layer 11 on the side surface of the pixel separation groove 10 is about 200 nm, and the opening end of the pixel separation groove 10 having a width of 400 nm can be closed.
[0034]
In addition, as the passivation layer 11, an SiON layer may be formed in addition to the SiN layer. Further, the type of the CVD method for forming the passivation layer 11 is not limited, and a plasma CVD method or a thermal CVD method can be adopted. The passivation layer 11 is formed according to the characteristics of the film formed by these various CVD methods. The pixel separation groove 10 may be closed by adjusting the film thickness of the pixel.
[0035]
Thereafter, as shown in FIG. 3B, the passivation layer 11 is patterned by photolithography to form holes 11a and 11b above the upper ohmic electrodes 8a and 8b, and the passivation layer is formed at the periphery of the substrate 1. The lower ohmic electrodes 7a and 7b are exposed by retreating the side surfaces 11c and 11d of the eleventh surface.
[0036]
Next, as shown in FIG. 3C, a resist pattern (not shown) having a window on the holes 11a and 11b is formed, and In is formed in the resist pattern and the inside of the window by a vacuum evaporation method. The pattern is removed by a lift-off method, and the remaining In is used as first metal bumps (terminals) 12a and 12b. The lower portions of the first metal bumps 12a and 12b are formed in the holes 11a and 11b, and are electrically connected to the multiple quantum well layer 5 via the reflective electrodes 9a and 9b and the upper contact layer 5.
[0037]
By the steps so far, the element structure of the QWIP-FPA is completed. Thereafter, the process proceeds to a step of flip-chip bonding the semiconductor chip for inputting / outputting signals to / from the QWIP-FPA and the QWIP-FPA. Therefore, as shown in FIG. 4A, the second metal bumps 13a and 13b of the semiconductor chip 14 on which the readout circuit (ROIC: Read Out Integrated Circuit) is formed are brought into contact with the first metal bumps 12a and 12b. Then, these bumps are press-bonded by ultrasonic waves or the like and joined. Although not specifically shown, the lower ohmic electrodes 7a and 7b are also electrically connected to the semiconductor chip 14 via metal bumps such as In bumps.
[0038]
By the way, the substrate 1 plays a role of facilitating the handling up to this step, but after the semiconductor chip 14 is joined, the semiconductor chip 14 plays the role, so that the substrate 1 becomes unnecessary. Therefore, thereafter, the process proceeds to the step of removing the unnecessary substrate 1.
[0039]
First, as shown in FIG. 4B, a photoresist (protective material) 15 is dropped on a peripheral portion of the substrate 1 and the photoresist 15 is applied between the semiconductor chip 14 and the passivation layer 11 by utilizing a capillary phenomenon. After that, the photoresist 15 is baked and solidified. Since the photoresist 15 is formed to protect the first and second metal bumps 12a, 12b, 13a, and 13b in an etching process described later, the photoresist 15 has such an amount that the metal bumps are completely isolated from the outside. It is preferable to pour the photoresist 15.
[0040]
Further, since the pixel isolation groove 10 is closed by the passivation layer 11 as described above, the photoresist 15 does not enter the pixel isolation groove 10.
[0041]
Subsequently, as shown in FIG. 5A, the substrate 1 and the buffer layer 2 are removed by wet etching while protecting the metal bumps 12a, 12b, 13a, and 13b with the photoresist 15. At this time, an etching stopper layer may be formed in advance between the lower contact layer 3 and the buffer layer 2 so that the etching is automatically stopped below the lower contact layer 3.
[0042]
Next, as shown in FIG. 5B, the photoresist 15 is removed by dissolving with an organic solvent such as butanol.
[0043]
The outline of the infrared detector according to the present embodiment is completed by the steps described above.
[0044]
In this infrared detector, infrared rays enter from the exposed lower surface of the lower contact layer 3 and a part thereof is absorbed in the multiple quantum well layer 4, but there is a selective side for the absorption, and the vibration surface of the electric field is a multiple quantum well layer. The probability of absorption of infrared rays in the normal direction of the well layer 4 is maximized. The reflective electrodes 9a and 9b cooperate with the uneven optical coupling layers 6a and 6b thereunder to irregularly reflect the incident infrared rays, generate infrared rays having the above-described electric field components, and generate infrared rays in the multiple quantum well layer 4. Functions to be efficiently absorbed.
[0045]
The pixel separating groove 10 separates the pixels P1 and P2 so as to prevent the infrared rays incident on the respective pixels P1 and P2 from leaking to other pixels, and to reduce crosstalk between the pixels. Function.
[0046]
Furthermore, by removing the substrate 1, infrared rays are prevented from being reflected multiple times within the substrate 1 and incident on a plurality of pixels, and the above-described crosstalk can be further reduced.
[0047]
Thereafter, as shown in FIG. 6, the back surface of the semiconductor chip 14 is fixed to the bottom in the sealing container 16 provided with the window 18 for transmitting infrared rays by an adhesive or the like. A cooling mechanism 17 such as a Stirling cooler for cooling the inside of the sealed container 16 to a desired temperature is provided outside, and a vacuum pump (not shown) for evacuating the inside to a desired degree of vacuum. ) Is provided in communication with the sealed container 16. Thus, the infrared detector according to the present embodiment is completed.
[0048]
According to the present embodiment described above, the opening end of the pixel isolation groove 10 is closed with the passivation layer 11 and the surface shape of the passivation layer 11 is made substantially flat at the opening end, so that each metal bump 12a, 12b, 13a , 13b from the etchant is prevented from entering the narrow pixel separation groove 10. Therefore, after the substrate 1 is removed by etching, the photoresist 15 is easily removed with an organic solvent or the like, and the amount of the photoresist 15 remaining on the passivation layer 11 and causing degassing is reduced. It is possible to prevent the degree of vacuum in the sealing container 16 from increasing, and to improve the characteristics of the entire infrared detector.
[0049]
In addition, according to this method, the pixel isolation groove 10 is closed by using the passivation layer 11 formed on the uppermost layer, so that a new insulating film for closing the groove is formed as in Patent Documents 1 and 2. Therefore, the above advantage can be obtained without increasing the number of steps.
[0050]
To close the opening end of the pixel isolation groove 10 with the passivation layer 11 as described above, as shown in FIG. 7, the width W1 of the pixel isolation groove 10 is reduced or the thickness t of the passivation layer 11 is increased. Good. If the width W1 and the film thickness t are set incorrectly, as shown in FIG. 8, even after the photoresist 15 is removed, a part thereof remains in the pixel separation groove 15, and the degree of vacuum in the sealing container 16 deteriorates. Resulting in.
[0051]
In addition, the upper surface of the passivation layer 11 does not need to be completely flat, and a depression such that the photoresist 15 can be easily removed may be left reflecting the pixel separation groove 10. Specifically, as shown in a dotted circle in FIG. 7, even if the recess 11a having the width W2 and the depth D remains above the pixel separation groove 10, the aspect ratio of the recess 11a (= D / W2) Is equal to or larger than 0 and substantially equal to or smaller than 1, the photoresist 15 does not remain in the depression 11a.
[0052]
Hereinafter, features of the present invention will be additionally described.
[0053]
(Supplementary Note 1) A lower contact layer having an exposed lower surface;
A multiple quantum well layer formed on the upper surface of the lower contact layer;
A pixel separation groove formed in the multiple quantum well layer and separating the multiple quantum well layer for each pixel;
An insulating layer formed in the pixel isolation groove and covering the multiple quantum well layer;
A hole formed in the insulating layer;
At least a lower portion is formed in the hole, and a terminal electrically connected to the multiple quantum well layer;
A semiconductor chip bonded to the terminal,
Has,
An infrared detector wherein an opening end of the pixel separation groove is closed by the insulating layer.
[0054]
(Supplementary Note 2) a step of forming a lower contact layer on or above the substrate;
Forming a multiple quantum well layer on the lower contact layer;
Forming a pixel separation groove in the multiple quantum well layer and separating the multiple quantum well layer for each pixel;
Forming an insulating layer above the multiple quantum well layer and in the pixel isolation trench;
Forming a hole in the insulating layer;
Forming at least a lower portion of a terminal electrically connected to the multiple quantum well layer in the hole;
Joining a semiconductor chip to the terminal,
Forming a protective material between the semiconductor chip and the insulating layer;
A step of etching and removing the substrate while protecting the terminals with the protective material;
Removing the protective material;
Has,
The width of the pixel separation groove or the thickness of the insulating layer is set to a value such that the opening end of the pixel separation groove is closed by the insulating layer, to prevent the protection material from entering the pixel separation groove. Characteristic method of manufacturing an infrared detector.
[0055]
(Supplementary note 3) The method for manufacturing an infrared detector according to Supplementary note 2, wherein the insulating layer is a passivation layer formed as an uppermost layer in a film formed above the multiple quantum well layer. .
[0056]
(Supplementary Note 4) The method for manufacturing an infrared detector according to Supplementary Note 2 or 3, wherein the width of the pixel separation groove is 400 nm or less.
[0057]
(Supplementary Note 5) The manufacturing of the infrared detector according to any one of Supplementary Notes 2 to 4, wherein an aspect ratio of a dent formed in the insulating layer above the element isolation groove is set to 0 or more and 1 or less. Method.
[0058]
(Supplementary note 6) The method for manufacturing an infrared detector according to any one of Supplementary notes 2 to 5, wherein a SiN layer or a SiON layer is formed as the insulating layer.
[0059]
(Supplementary note 7) The method for manufacturing an infrared detector according to any one of supplementary notes 2 to 6, wherein a metal bump is formed as the terminal.
[0060]
(Supplementary Note 8) The method for manufacturing an infrared detector according to any one of Supplementary Notes 2 to 7, wherein a photoresist is used as the protective material.
[0061]
(Supplementary note 9) The method for manufacturing an infrared detector according to any one of supplementary notes 2 to 8, wherein a GaAs substrate is used as the substrate.
[0062]
(Supplementary Note 10) a step of forming an upper contact layer on the multiple quantum well layer;
A step of forming an optical coupling layer having an uneven surface on the upper contact layer,
Forming a reflective electrode on the optical coupling layer,
Has,
10. The infrared detector according to claim 2, wherein the terminal is formed on the reflective electrode.
[0063]
(Supplementary note 11) The infrared detector according to any one of Supplementary notes 2 to 10, wherein a step of placing the semiconductor chip in a sealing container having an infrared transmission window is performed after removing the protective material. .
[0064]
【The invention's effect】
As described above, according to the present invention, the opening end of the pixel separation groove is closed with the insulating layer so that the protection material does not enter the pixel separation groove, so that the protection material is removed after the step of etching the substrate. And the amount of the protective material remaining on the insulating layer can be reduced, the degree of vacuum in the sealed container can be prevented from increasing, and the characteristics of the entire infrared detector can be improved. .
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views (part 1) illustrating a method of manufacturing an infrared detector according to an embodiment of the present invention.
FIGS. 2A and 2B are cross-sectional views (part 2) illustrating a method for manufacturing an infrared detector according to an embodiment of the present invention.
FIGS. 3A and 3B are cross-sectional views (part 3) illustrating a method for manufacturing an infrared detector according to the embodiment of the present invention.
FIGS. 4A and 4B are cross-sectional views (part 4) illustrating a method for manufacturing an infrared detector according to an embodiment of the present invention.
FIGS. 5A and 5B are cross-sectional views (part 5) illustrating a method for manufacturing an infrared detector according to the embodiment of the present invention.
FIG. 6 is a sectional view (part 6) illustrating the method for manufacturing the infrared detector according to the embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing a width of a pixel isolation groove and a thickness of a passivation layer in the embodiment of the present invention.
FIG. 8 is a cross-sectional view showing inconvenience seen when the width of the pixel isolation groove and the thickness of the passivation layer are incorrectly set.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Buffer layer, 3 ... Lower contact layer, 4 ... Multiple quantum well layer, 5 ... Upper contact layer, 6 ... Semiconductor layer, 6a, 6b ... Optical coupling layer, 7a, 7b ... Lower ohmic electrode, 8a , 8b ... upper ohmic electrode, 9a, 9b ... reflective electrode, 10 ... pixel isolation groove, 11 ... passivation layer, 11a, 11b ... hole, 11c, 11d ... side surface, 12a, 12b ... first metal bump, 13a, 13b ... Second metal bumps, 14 semiconductor chips, 15 photoresists, 16 sealing containers, 17 cooling mechanisms, 18 windows, P1, P2 pixels.

Claims (5)

A lower contact layer having an exposed lower surface;
A multiple quantum well layer formed on the upper surface of the lower contact layer;
A pixel separation groove formed in the multiple quantum well layer and separating the multiple quantum well layer for each pixel;
An insulating layer formed in the pixel isolation groove and covering the multiple quantum well layer;
A hole formed in the insulating layer;
At least a lower portion is formed in the hole, and a terminal electrically connected to the multiple quantum well layer;
A semiconductor chip bonded to the terminal,
Has,
An infrared detector wherein an opening end of the pixel separation groove is closed by the insulating layer. Forming a lower contact layer on or above the substrate;
Forming a multiple quantum well layer on the lower contact layer;
Forming a pixel separation groove in the multiple quantum well layer and separating the multiple quantum well layer for each pixel;
Forming an insulating layer above the multiple quantum well layer and in the pixel isolation trench;
Forming a hole in the insulating layer;
Forming at least a lower portion of a terminal electrically connected to the multiple quantum well layer in the hole;
Joining a semiconductor chip to the terminal,
Forming a protective material between the semiconductor chip and the insulating layer;
A step of etching and removing the substrate while protecting the terminals with the protective material;
Removing the protective material;
Has,
The width of the pixel separation groove or the thickness of the insulating layer is set to a value such that the opening end of the pixel separation groove is closed by the insulating layer, to prevent the protection material from entering the pixel separation groove. Characteristic method of manufacturing an infrared detector. 3. The method according to claim 2, wherein the insulating layer is a passivation layer formed as an uppermost layer in a film formed above the multiple quantum well layer. 4. The method according to claim 2, wherein the width of the pixel separation groove is 400 nm or less. 5. The method for manufacturing an infrared detector according to claim 2, wherein an aspect ratio of a dent formed in the insulating layer above the element isolation groove is set to 0 or more and 1 or less.

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