JP2004228589A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability and manufacturing yield of an insulating gate type field effect transistor which is formed on a semiconductor thin film on an insulating film. <P>SOLUTION: A second integrated insulating gate type transistor which is controlled by a gate potential and a drain potential of a first insulating gate type transistor, is formed inside a multilayer semiconductor substrate. The source of the second insulating gate type transistor is connected to the substrate terminal of the first insulating gate type transistor through an embedded gate insulating film. The source is not doped by ion implantation. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technology and a semiconductor device, and more particularly to a technology effective when applied to high performance and high reliability of a highly integrated semiconductor device.

  2. Description of the Related Art With the advancement of performance and miniaturization of semiconductor devices, self-alignment technology capable of absorbing misalignment of a mask is frequently used.

  For example, Japanese Patent Application Laid-Open No. H11-26714 (Patent Document 1) discloses that a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting a memory cell of a DRAM is covered with a silicon nitride film, and an interlayer made of a silicon oxide film is further provided. A technique for forming a plug connected to the source / drain region of the MISFET after forming an insulating film is disclosed. In the process of forming the connection hole in which the plug is formed, a two-stage process of a first etching process in which the silicon oxide film is etched and the silicon nitride film is hardly etched and a second etching process in which the silicon nitride film is etched are performed. An etching process is employed. Since the MISFET (selection MISFET) of the DRAM memory cell is processed with a minimum processing size, when forming a connection hole between the gate electrodes, a mask shift between the gate electrode pattern and the connection hole pattern cannot be avoided. Unless it is used, it is difficult to form a proper connection hole. In this regard, in the technique disclosed in the above publication, the silicon nitride film covering the gate electrode functions as an etching stopper, and the self-alignment of processing the connection hole with the gate electrode can be realized.

  According to the technique disclosed in the above publication, the thickness of the silicon oxide film is relatively smaller than the thickness of the silicon oxide film as the interlayer insulating film, and the silicon nitride film functions as an etching stopper. Sufficient over-etching can be performed in one etching step. Therefore, even if the connection holes are fine or have a large aspect ratio, the depth of the connection holes in the wafer surface can be made uniform, and the process margin can be increased. On the other hand, since the thickness of the silicon nitride film serving as the stopper film is sufficiently small, excessive etching of the substrate is suppressed even when sufficient overetching is performed in the second etching step. In other words, the self-alignment processing of the connection hole with respect to the substrate surface can be realized. In particular, when the bottom of the contact hole is over the element isolation region, the silicon oxide film constituting the element isolation region may be excessively etched. Over-etching can be sufficiently suppressed. As a result, the leakage current of the MISFET caused by excessive etching of the substrate (element isolation region) can be suppressed, and in the case of a DRAM, the refresh characteristics can be improved.

  The self-alignment processing on the substrate surface described above can be applied to, for example, a wiring processing step using a damascene process. That is, when forming a wiring groove or a connection hole for forming a wiring in an interlayer insulating film, a thin silicon nitride film is previously formed at a position corresponding to the bottom of the wiring groove or the bottom of the connection hole. A wiring groove or a connection hole is formed in the same manner as described above. Even in such a process, it is possible to suppress excessive etching of the member at the bottom of the wiring groove or the connection hole, improve the uniformity of the depth of the wiring groove or the depth of the connection hole, and realize a reliable connection between wiring layers.

Incidentally, as a method of forming a silicon nitride film, there are various film forming methods such as a thermal CVD (Chemical Vapor Deposition) method and a plasma CVD method. For example, JP-A-2-234430 discloses that a silicon nitride film formed by an ECR (Electron Cyclotron Resonance) -CVD method using silane (SiH ₄ ) and nitrogen (N ₂ ) as a source gas is an interlayer insulating film or a passivation film. The technology applied to the invention is disclosed. Japanese Patent Application Laid-Open No. 63-132434 discloses a technique in which a silicon nitride film formed by an ECR-CVD method using silane (SiH ₄ ) and nitrogen (N ₂ ) as a source gas is applied to a passivation film. I have.
JP-A-11-026714 JP-A-02-234430 JP-A-63-132434

  However, the present inventors have recognized the following problems. The recognition of the problems described below has been obtained through experimental studies by the present inventors, and has not been made publicly known.

  In other words, with the miniaturization and high performance of semiconductor devices, restrictions on heat treatment are becoming stricter. For example, miniaturization of a semiconductor device requires precise control of the position and depth of a diffusion layer (impurity semiconductor region). If a high-temperature process is interposed after the formation of these precisely controlled diffusion layers, diffusion of impurities will occur, and the formation position of the diffusion layers will fluctuate, which is not preferable. Since the controllability of the impurity concentration in the diffusion layer is also required to be high, re-diffusion of the impurity in the diffusion layer is not preferable from the viewpoint of fluctuation of the impurity concentration. In order to realize high performance of the semiconductor device, it is desirable to form a silicide layer on the surface of the impurity diffusion layer or the surface of the gate electrode. However, if a high-temperature process is interposed after the formation of the silicide layer, various problems occur due to the poor heat resistance of the silicide layer. That is, problems such as a composition change in the silicide layer due to a re-reaction between the silicide layer and the silicon layer, a decrease in the conductivity of the silicide layer due to the composition change, an increase in stress in the silicide layer, generation of voids, etc. Occurs.

  Therefore, the formation of the silicon nitride film for self-alignment covering the gate electrode, the wiring groove of the damascene wiring, and the silicon nitride film for forming the connection hole in a self-alignment manner requires a high temperature (generally 700 ° C. or higher). The thermal CVD method to be formed cannot be used. Further, in the formation of a silicon nitride film by a thermal CVD method, there is a problem that active hydrogen (H) generated during the film formation is diffused into a diffusion layer or a channel region of a MISFET, thereby changing a threshold value (Vth). The present inventors have also recognized that.

  Therefore, a silicon nitride film using a plasma CVD method which can be formed at a low temperature (generally, about 400 ° C.) will be studied.

  However, the silicon nitride film formed by the plasma CVD method has a new obstacle that can degrade device characteristics.

  That is, there is an obstacle that a formation surface is damaged by plasma due to bombardment of radicals or ions generated during the plasma process. As a result, impurities (boron (B), phosphorus (P), etc.) in the polycrystalline silicon film (gate electrode) or the diffusion layer (semiconductor substrate) to be formed are inactivated, or the polycrystalline silicon film is Further, there is a problem that dangling bonds in the diffusion layer increase and their resistance values increase.

The silicon nitride film formed by the plasma CVD method uses silane (SiH ₄ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) as a source gas because of its good step coverage. Such a SiH ₄ / NH ₃ / In a plasma CVD film (silicon nitride film) using N ₂ as a raw material, a large amount of hydrogen (H) is contained in the film. Hydrogen in the film is released by the subsequent heat treatment, and the film (silicon nitride film) stress caused by the release of hydrogen is increased. An increase in film stress has a problem of deteriorating device characteristics. In a remarkable case, peeling of the film occurs, which may cause a device failure.

  Further, the desorbed hydrogen diffuses into the polycrystalline silicon film serving as the gate electrode and the diffusion layer (source / drain) serving as the semiconductor substrate, and becomes a cause of inactivating impurities in the polycrystalline silicon film or the diffusion layer. As a result, there arises a problem of increasing the resistance of the gate electrode or the source / drain.

  Further, the desorbed hydrogen diffused into the polycrystalline silicon film or the diffusion layer makes it easy for impurities (particularly, boron (B)) in the polycrystalline silicon film or the diffusion layer to move, and the impurity (particularly, boron) is transferred to the channel region of the MISFET. Has the effect of making it easier to spread. As a result, the threshold voltage (Vth) of the MISFET fluctuates, and there is a problem that the performance of the semiconductor device is reduced.

As described above, in a silicon nitride film formed at a low temperature, it is considered that a large amount of hydrogen contained in the film deteriorates device characteristics. In the as-deposited (as deposited) state, even if the silicon nitride film is made of SiH ₄ / NH ₃ / N ₂ containing a large amount of hydrogen, it is subjected to a heat treatment after the film is formed to release hydrogen, thereby reducing the hydrogen content. A method of obtaining a silicon nitride film is considered. However, in this method, there is a problem that the film is peeled off after heat treatment and foreign matter is generated. Further, when a contact hole is formed in the film part that has been peeled off, poor coverage of the connection member is generated and conduction failure of the contact part is caused. There is a problem that arises.

  An object of the present invention is to provide a technique capable of forming a silicon nitride film for self-alignment at a low temperature and with a small hydrogen content.

  It is another object of the present invention to provide a film forming method capable of reducing plasma damage when forming a silicon nitride film.

  It is another object of the present invention to provide a semiconductor device in which a change in the resistance of a polycrystalline silicon film is small and a change in the threshold voltage of a MISFET is small.

  Another object of the present invention is to provide a high-performance and highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The present invention relates to a method for manufacturing a semiconductor device in which a first silicon nitride film for self-alignment processing is formed and a second silicon nitride film for passivation is further formed, wherein the first silicon nitride film includes silane and nitrogen. And the second silicon nitride film is formed by a plasma CVD method using silane, ammonia and nitrogen as source gases.

  The present invention relates to a semiconductor device having a first silicon nitride film for self-alignment processing and a second silicon nitride film for passivation, wherein the first silicon nitride film is subjected to Si-H / Si analysis by FT-IR analysis. A relationship of R1 <R2 exists between the -N bond ratio R1 and the Si-H / Si-N bond ratio R2 of the second silicon nitride film by FT-IR analysis.

Hereinafter, the inventions disclosed in this specification are listed and shown.
1. The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of selectively forming a first insulating film (for example, an element isolation region) on a surface of a semiconductor substrate; and (b) a second insulating film (for example, Forming a first conductor piece (for example, a gate electrode) via a gate insulating film); and (c) a region on the surface of the semiconductor substrate where the first insulating film and the first conductor piece do not exist. (D) forming a third insulating film (for example, a self-alignment film) so as to cover the first conductor piece, the semiconductor layer, and the first insulating film. (E) forming a fourth insulating film (for example, an interlayer insulating film) on the third insulating film; and (f) forming a first opening (for example, a contact) in the fourth and third insulating films. (G) forming a second hole in the first opening. Forming a body piece (for example, a plug); and (h) forming a fifth insulating film (for example, a passivation film) on the fourth insulating film, wherein the third insulating film and the fifth insulating film are formed. Is a silicon nitride film formed by a plasma CVD method, and the forming temperature of the third insulating film is higher than the forming temperature of the fifth insulating film.
2. 2. The method for manufacturing a semiconductor device according to the item 1, wherein the first and fourth insulating films are silicon oxide films, and the step of forming the first opening includes the step of forming the fourth insulating film with respect to the third insulating film. Etching the fourth insulating film under the condition that the etching amount of the third insulating film is large, and etching the third insulating film under the condition that the etching amount of the third insulating film with respect to the first insulating film is large. And a process.
3. 2. The method for manufacturing a semiconductor device according to item 1, wherein the fifth insulating film contains ammonia gas as a reactive gas, and the third insulating film does not contain ammonia as a reactive gas.
4. 2. The method for manufacturing a semiconductor device according to the item 1, further comprising a step of forming a silicide layer on a surface of the semiconductor layer between the steps (c) and (d).
5. 5. The method for manufacturing a semiconductor device according to the item 4, wherein the second conductor piece includes a first conductor layer (for example, a titanium nitride layer) and a second conductor layer (for example, a tungsten layer), and the first conductor layer comprises: It is thinner than the second conductor layer and located below the second conductor layer.
6. 2. The method of manufacturing a semiconductor device according to item 1, wherein (i) forming a third conductor piece (for example, a wiring) between the steps (g) and (h); The insulating film has a second opening exposing a part of the third conductor piece, and an external connection conductor piece (for example, a bonding wire or a bump electrode) is connected to the third conductor piece at the second opening. And a step of performing
7. 2. The method for manufacturing a semiconductor device according to item 1, wherein the first conductor piece is made of a silicon layer containing boron.
8. 2. The method for manufacturing a semiconductor device according to the item 1, wherein the conductor pieces are a first conductor layer made of silicon, a second conductor layer (for example, a barrier layer such as tungsten nitride), and a refractory metal (for example, titanium, cobalt, tungsten). Etc.) of the third conductor layer.
9. The method of manufacturing a semiconductor device according to the present invention includes: (a) a step of selectively forming a first insulating film (for example, an element isolation region) on a surface of a semiconductor substrate; and (b) a second insulating film (for example, Forming a first conductor piece (for example, a gate electrode) via a gate insulating film); and (c) a region on the surface of the semiconductor substrate, where the first insulating film and the first conductor piece do not exist. (D) forming a third insulating film (for example, a self-alignment film) so as to cover the first conductor piece, the semiconductor layer, and the first insulating film. (E) forming a fourth insulating film (for example, an interlayer insulating film) on the third insulating film; and (f) forming a first opening (for example, a contact) in the fourth and third insulating films. Forming a hole), and (g) forming the first opening Forming a second conductor piece (for example, a plug), and (h) forming a fifth insulating film (for example, a passivation film) on the fourth insulating film. The fifth insulating film is a silicon nitride film formed by a plasma CVD method, and the hydrogen content of the third insulating film is smaller than the hydrogen content of the fifth insulating film.
10. The method of manufacturing a semiconductor device according to the present invention includes: (a) forming a first insulating film (for example, a self-alignment film) on a semiconductor substrate; and (b) forming a second insulating film (for example, on the first insulating film). (C) forming an opening (for example, a damascene groove) in the second and first insulating films; and (d) forming a conductor layer (for example, in the opening). Forming a wiring), and (e) forming a third insulating film (for example, a passivation film) on the conductor layer, wherein the first insulating film and the third insulating film are formed by a plasma CVD method. Wherein the formation temperature of the first insulating film is higher than the formation temperature of the third insulating film.
11. The method of manufacturing a semiconductor device according to the present invention includes: (a) forming a first insulating film (for example, a self-alignment film) on a semiconductor substrate; and (b) forming a second insulating film (for example, on the first insulating film). (C) forming an opening (for example, a damascene groove) in the second and first insulating films; and (d) forming a conductor layer (for example, in the opening). Forming a wiring), and (e) forming a third insulating film (for example, a passivation film) on the conductor layer, wherein the first insulating film and the third insulating film are formed by a plasma CVD method. Wherein the hydrogen content of the first insulating film is smaller than the hydrogen content of the third insulating film.
12. The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of selectively forming a first insulating film (for example, an element isolation region) on a surface of a semiconductor substrate; and (b) a step of forming the first insulating film on the surface of the semiconductor substrate, 1) a step of forming a semiconductor layer (for example, a source / drain) in a region where no insulating film exists; (c) a step of forming a silicide layer of a refractory metal on the surface of the semiconductor layer; Forming a second insulating film (for example, a self-alignment film) so as to cover the silicide layer and the first insulating film, and (e) forming a third insulating film (for example, an interlayer insulating film) on the second insulating film. ), (F) forming an opening (for example, a contact hole) in the third and second insulating films, and (g) forming a conductor piece (for example, a plug) in the opening. And the second insulating film has a temperature of 400 degrees. A silicon nitride film formed by a plasma CVD method above.
13. Item 13. The method of manufacturing a semiconductor device according to Item 12, wherein the second insulating film is formed using monosilane and nitrogen as reaction gases and not using ammonia.
14． 13. The method for manufacturing a semiconductor device according to item 12, wherein the third insulating film is a silicon oxide film, and the step of forming the opening is performed under a condition that an etching amount with respect to the second insulating film is large. A step of etching the third insulating film; and a step of etching the second insulating film under a condition that the etching amount of the first insulating film is large.
15. 13. The method of manufacturing a semiconductor device according to the item 12, wherein the step of forming the silicide layer comprises: (h) depositing a refractory metal film on the semiconductor layer and the first insulating film; The method includes a step of performing a heat treatment on the substrate to form a silicide layer on the surface of the semiconductor layer; and (j) a step of removing the refractory metal film on the first insulating film.
16. Item 13. The method of manufacturing a semiconductor device according to Item 12, wherein the conductor piece includes a first conductor layer and a second conductor layer, wherein the first conductor layer is thinner than the second conductor layer, It is located below.
17. Item 17. The method for manufacturing a semiconductor device according to Item 16, wherein the first conductor layer is a titanium nitride layer, and the second conductor layer is a tungsten layer.
18. The method of manufacturing a semiconductor device according to the present invention includes: (a) a step of selectively forming a first insulating film (for example, an element isolation region) on a surface of a semiconductor substrate; and (b) a second insulating film (for example, Forming a first conductor piece (for example, a gate electrode) via a gate insulating film); and (c) a region on the surface of the semiconductor substrate, where the first insulating film and the first conductor piece do not exist. (D) forming a third insulating film (for example, a self-alignment film) so as to cover the first conductor piece, the semiconductor layer, and the first insulating film. And (e) forming a fourth insulating film (for example, an interlayer insulating film) on the third insulating film, wherein the first conductor piece is a silicon film containing boron. The third insulating film is formed by a plasma CVD method of 400 degrees or more. A silicon nitride film formed Ri.
19. Item 19. The method for manufacturing a semiconductor device according to Item 18, wherein the third insulating film is formed using monosilane and nitrogen as reaction gases and not using ammonia.
20. The method of manufacturing a semiconductor device according to the present invention includes: (a) forming a first insulating film (for example, a self-alignment film) on a semiconductor substrate; and (b) forming a second insulating film (for example, on the first insulating film). Forming a damascene groove forming insulating film), (c) forming an opening (for example, a damascene groove) in the second and first insulating films, and (d) forming a conductor layer ( Forming a wiring, for example), wherein the first insulating film is a silicon nitride film formed by a plasma CVD method at 400 ° C. or higher.
21. 21. The method for manufacturing a semiconductor device according to item 20, wherein the second insulating film is a silicon oxide film.
22. 21. The method of manufacturing a semiconductor device according to item 20, wherein the step of forming the conductor layer includes a step of forming a first lower conductor layer and a second upper conductor layer, and the second conductor layer is formed of copper. The first conductor layer has a copper diffusion preventing function.
23. The method for manufacturing a semiconductor device according to the present invention includes the steps of (a) forming a first conductor layer made of silicon, a second conductor layer, and a first conductor made of a refractory metal on a semiconductor substrate via a first insulation film (for example, a gate insulation film) Depositing a third conductor layer and a second insulating film (for example, a cap insulating film); and (b) processing the second insulating film, the third, second, and first conductor layers into a predetermined pattern; (C) forming a third insulating film (for example, a self-alignment film) on the second insulating film, wherein the second insulating film is a silicon nitride film formed by a plasma CVD method at a temperature of 400 degrees or more. It is.
24. 24. The method of manufacturing a semiconductor device according to the item 23, wherein the third insulating film is a silicon nitride film formed by a plasma CVD method at a temperature of 400 degrees or more.
25. The semiconductor device of the present invention includes: (a) a semiconductor substrate; (b) a first insulating film (for example, an element isolation region) selectively formed on a surface of the semiconductor substrate; A first conductor piece (for example, a gate electrode) formed via two insulating films (for example, a gate insulating film); and (d) a first insulating film and the first conductor piece on the surface of the semiconductor substrate. And (e) a third insulating film (for example, a self-alignment film) formed on the first conductor piece, the first insulating film, and the semiconductor layer. ), (F) a fourth insulating film (for example, an interlayer insulating film) formed on the third insulating film, and (g) formed in openings formed in the third and fourth insulating films. A second conductor piece (for example, a plug); and (h) a fifth conductor formed on the second conductor piece. The third and fifth insulating films are silicon nitride films formed by a plasma CVD method, and the hydrogen content of the third insulating film is equal to that of the fifth insulating film. It is less than the hydrogen content.
26. 26. The semiconductor device according to the item 25, wherein the second conductor piece includes a first conductor layer and a second conductor layer, wherein the first conductor layer is thinner than the second conductor layer, It is located below.
27. 27. The semiconductor device according to item 26, wherein the first conductor layer is a titanium nitride layer, and the second conductor layer is a tungsten layer.
28. 26. The semiconductor device according to the above item 25, wherein a refractory metal silicide layer is formed on a surface of the semiconductor layer.
29. 26. The semiconductor device according to the above item 25, wherein the first conductor piece is made of a silicon layer containing boron.
30. The semiconductor device according to the present invention comprises: (a) a semiconductor substrate; (b) a first conductor piece (for example, a gate electrode) formed on the semiconductor substrate via a first insulating film (for example, a gate insulating film); A) a second insulating film (for example, a cap insulating film) formed on the first conductor piece; and (d) a third insulating film (for example, a passivation film) formed on the second insulating film. The second and third insulating films are silicon nitride films formed by a plasma CVD method, and the hydrogen content of the second insulating film is smaller than the hydrogen content of the third insulating film.
31. 31. The semiconductor device according to the above item 30, further comprising (e) first and second semiconductor regions located at both ends of the first conductor piece and located on a surface of the semiconductor substrate. The conductor piece functions as a gate of the transistor, and the first and second semiconductor regions function as a source and a drain of the transistor. In the direction from the source to the drain, the second insulating film has a width substantially equal to the first conductor piece. It has.
32. 31. The semiconductor device according to the item 30, further comprising (e) a second conductor piece (for example, a wiring) formed on the second insulating film, and (f) an external connection connected to the second conductor piece. A conductor piece (for example, a bump), wherein the third insulating film has an opening, and the external connection conductor piece is connected to the second conductor piece at the opening.
33. The semiconductor device according to the present invention includes: (a) a semiconductor substrate; and (b) a first conductor piece (eg, a gate electrode) formed on the semiconductor substrate via a first insulating film (eg, a gate insulating film) and having a side wall. (C) a second insulating film (for example, a side wall) formed on a side wall of the first conductor piece, and (d) a third insulating film (for example, a passivation film) formed on the first conductor piece. The second and third insulating films are silicon nitride films formed by a plasma CVD method, and the hydrogen content of the second insulating film is smaller than the hydrogen content of the third insulating film. is there.
34. 34. The semiconductor device according to the above item 33, further comprising: (e) a second conductor piece (for example, a wiring) formed on the second insulating film; and (f) an external connection connected to the second conductor piece. A conductor piece (for example, a bump), wherein the third insulating film has an opening, and the external connection conductor piece is connected to the second conductor piece at the opening.
35. The semiconductor device of the present invention includes (a) a semiconductor substrate, (b) a first insulating film (for example, a self-alignment film) on the semiconductor substrate, and (c) a second insulating film on the first insulating film. (E.g., an insulating film for forming a wiring groove); (d) a first conductor piece (e.g., a wiring) formed in a first opening formed in the first and second insulating films; A third insulating film (for example, an interlayer insulating film) on one conductor piece, (f) a second conductive piece (for example, wiring) on the third insulating film, and (g) a fourth insulating film on the second conductive piece ( For example, a passivation film), the first and fourth insulating films are silicon nitride films formed by a plasma CVD method, and the hydrogen content of the first insulating film is equal to the hydrogen content of the fourth insulating film. It is less than the content.
36. 36. The semiconductor device according to the above item 35, further comprising (h) an external connection conductor piece connected to the second conductor piece, wherein the fourth insulating film has a second opening, In the opening, the conductor piece for external connection and the second conductor piece are connected.
37. 37. The semiconductor device according to the above item 36, wherein the second insulating film is a silicon oxide film.
38. Item 13. The method for manufacturing a semiconductor device according to Item 12, comprising a step of forming a first conductor piece (for example, a gate electrode) made of a silicon material between the steps (a) and (b), In step c), a silicide layer of a refractory metal is formed on the surface of the first conductor piece.
39. 26. The semiconductor device according to the above item 25, wherein the first conductor piece is made of a silicon material, and a silicide layer of a high melting point metal is formed on a surface of the first conductor piece.
40. The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, wherein a first silicon nitride film for self-alignment processing is formed, and a second silicon nitride film for passivation is further formed. The film is formed by a plasma CVD method using silane and nitrogen as a source gas, and the second silicon nitride film is formed by a plasma CVD method using silane, ammonia and nitrogen as a source gas.
41. 41. In the method of manufacturing a semiconductor device according to the item 40, the formation of the first silicon nitride film is performed at a higher temperature than the formation of the second silicon nitride film.
42. 41. In the method of manufacturing a semiconductor device according to the item 40, the formation of the first silicon nitride film is performed at a temperature of 400 degrees or more.
43. A semiconductor device of the present invention is a semiconductor device having a first silicon nitride film for self-alignment processing and a second silicon nitride film for passivation, wherein the first silicon nitride film has a Si-Si film obtained by FT-IR analysis. There is a relationship of R1 <R2 between the H / Si-N bond ratio R1 and the Si-H / Si-N bond ratio R2 of the second silicon nitride film by FT-IR analysis.
44. 44. The semiconductor device according to the above item 43, wherein a Si—H bond of the first silicon nitride film by FT-IR analysis is 2 × 10 ²¹ cm ⁻³ or less.

  Note that the member names shown in parentheses in the above description are examples, and the present invention is not limited to these.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) A silicon nitride film for self-alignment can be formed at a low temperature and with a small hydrogen content.
(2) Plasma damage at the time of forming a silicon nitride film can be reduced.
(3) It is possible to provide a semiconductor device in which the resistance value of the polycrystalline silicon film is small and the threshold voltage of the MISFET is small.
(4) A high-performance and highly reliable semiconductor device can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted.

(Embodiment 1)
1 to 14 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a semiconductor substrate 1 made of, for example, p ⁻ type single crystal silicon is prepared, and an element isolation region 2 is formed on the main surface of the semiconductor substrate 1. The element isolation region 2 can be formed, for example, as follows. First, a silicon oxide film (SiO) and a silicon nitride film (SiN) are sequentially formed on the main surface of the semiconductor substrate 1, and this silicon nitride film is etched using a patterned photoresist film. A shallow groove is formed in the semiconductor substrate 1 using the silicon film as a mask. Thereafter, an insulating film such as a silicon oxide film filling the shallow groove is deposited, the silicon oxide film in a region other than the shallow groove is removed by using a CMP (Chemical Mechanical Polishing) method, and the silicon nitride film is further formed by a wet etching method or the like. Remove. As a result, the element isolation region 2 (the first insulating film of the above item 1) is formed.

  Next, impurities are ion-implanted using the patterned photoresist film as a mask to form a p-well 3 and an n-well 4. An impurity having a p-type conductivity such as boron (B) is ion-implanted into the p-well 3, and an impurity having a n-type conductivity such as phosphorus (p) is ion-implanted into the n-well 4. An n-channel MISFET Qn is formed in the p-well 3, and a p-channel MISFET Qp is formed in the n-well 4.

  Next, as shown in FIG. 1B, a silicon oxide film 5 (the second insulating film such as the above item 1) is formed in each region of the p well 3 and the n well 4. The silicon oxide film 5 is to be a gate insulating film of the MISFET, and is formed by, for example, a thermal CVD method.

  Next, a polycrystalline silicon film 6 is formed. The polycrystalline silicon film 6 is to be a gate electrode of the MISFET (the first conductor piece of item 1 and the like) and is formed by, for example, a CVD method.

  Next, as shown in FIG. 1C, an n-type impurity is formed on the polycrystalline silicon film 6 in a region (p-well 3 region) where the n-channel MISFET Qn is to be formed by using a photoresist film (not shown) as a mask. (For example, phosphorus (P)) is ion-implanted. Thereby, n-type region 6n of the polycrystalline silicon film is formed. Further, a p-type impurity (for example, boron (B)) is ion-implanted into the polycrystalline silicon film 6 in a region (n-well 4 region) where the p-channel type MISFET Qp is to be formed using a photoresist film (not shown) as a mask. . As a result, a p-type region 6p of the polycrystalline silicon film is formed.

  As described above, by ion-implanting the polycrystalline silicon film 6 in different regions, the conductivity type of the gate electrode becomes n-type in the case of an n-channel MISFET and p-type in the case of a p-channel MISFET. A dual gate structure can be configured. By employing the dual gate structure, Vth (threshold) of the MISFET can be reduced, and a MISFET driven at a low voltage can be formed. If a polycrystalline silicon film containing boron is used as a part of the gate electrode, the boron diffused from the gate electrode (polycrystalline silicon film) reaches the channel region (well) because the thermal diffusion coefficient of boron is large. Conventionally, there was a problem that the threshold voltage easily fluctuated. However, in this embodiment, a silicon nitride film not containing much hydrogen is used for a film for self-alignment processing as described later, so that boron diffusion is not performed. Control, and high reliability of the semiconductor device can be maintained. This will be described in detail later.

  Next, as shown in FIG. 2A, the polycrystalline silicon films 6, 6n, 6p are patterned into a predetermined pattern to form a gate electrode 7. Note that a dry etching method using a photoresist film (not shown) as a mask is used for patterning. Further, the gate electrode 7 may function as a wiring.

  Next, as shown in FIG. 2B, an n-type impurity (for example, phosphorus or arsenic (As)) is ion-implanted into the p-well 3 using a photoresist film (not shown) as a mask, and the n-type semiconductor region 8 is formed. (Semiconductor layer of the above item 1, etc.) is formed. Since the gate electrode 7 also functions as a mask, the n-type semiconductor region 8 is formed in self-alignment with the gate electrode 7. Using a photoresist film (not shown) as a mask, a p-type impurity (for example, boron) is ion-implanted into the n-well 4 to form a p-type semiconductor region 9 (the semiconductor layer of the above item 1 or the like). Similarly, since the gate electrode 7 also functions as a mask, the p-type semiconductor region 9 is formed in a self-aligned manner with respect to the gate electrode 7.

  Next, as shown in FIG. 2C, a sidewall 10 is formed on the side wall of the gate electrode 7. The sidewall 10 is formed, for example, by depositing a silicon oxide film on the side wall of the gate electrode 7 to such an extent that it can be formed with good step coverage, and anisotropically etching the silicon oxide film.

Further, as in the step of FIG. 2B, an n ⁺ -type semiconductor region 11 is formed in the p-well 3 region, and a p ⁺ -type semiconductor region 12 is formed in the n-well 4 region. The n ⁺ -type semiconductor region 11 and the p ⁺ -type semiconductor region 12 introduce impurities at a higher concentration than the n-type semiconductor region 8 and the p-type semiconductor region 9, respectively. In this ion implantation step, the sidewall 10 also functions as a mask, so that the n ⁺ -type semiconductor region 11 and the p ⁺ -type semiconductor region 12 are formed in self-alignment with the sidewall 10. As a result, a source / drain having an LDD (Lightly Doped Drain) structure composed of the n-type semiconductor region 8 and the n ⁺ -type semiconductor region 11 or composed of the p-type semiconductor region 9 and the p ⁺ -type semiconductor region 12 is formed.

  Next, as shown in FIG. 3A, a resistance element is formed on the wide element isolation region 2. The resistance element includes a conductor film R on the element isolation region 2, an insulating film 13 covering the conductor film R, and a lead electrode 14 on the insulating film 13. As the conductor film R, a metal having a relatively high resistivity (for example, tungsten or the like) or a semiconductor film (for example, a polycrystalline silicon film) having a relatively small amount of impurities can be used. As the insulating film 13, for example, a silicon oxide film or a silicon nitride film can be applied. As the extraction electrode 14, for example, a polycrystalline silicon film can be applied. The conductor film R can be formed, for example, by depositing a conductor film on the entire surface of the semiconductor substrate 1 and patterning the conductor film. Thereafter, an insulating film 13 is deposited by a CVD method, a sputtering method, or the like, a connection hole is opened, a polycrystalline silicon film is deposited by a CVD method, for example, and the polycrystalline silicon film is patterned into a predetermined shape to form a lead electrode 14. To form

  In the above description, the resistance element having the extraction electrode 14 is illustrated, but a resistance element of a type in which the extraction electrode 14 is not provided but is directly extracted with a plug may be used. In this case, if the conductor film R is formed of a polycrystalline silicon film, it is necessary to cover the surface of the conductor film R with an insulating film in order to prevent the entire surface of the polycrystalline silicon film from being silicided in a salicide process described later. There is.

  Further, the conductor film R may be formed (patterned) before the step of forming the sidewall 10 in FIG. 2C, and an insulating film for forming the sidewall 10 may be formed so as to cover the conductor film R. . In this case, a photoresist film covering the patterned conductor film R is formed, and the insulating film is anisotropically etched using the photoresist film as a mask, so that the insulating film 13 covering the conductor film R is formed in the region where the conductor film R is formed. Then, the sidewalls 10 can be formed at the same time.

  Next, as shown in FIG. 3B, a metal film 15 is deposited on the entire surface of the semiconductor substrate 1. The metal film 15 is made of a metal having a high melting point, such as titanium, tungsten, or cobalt. For depositing the metal film 15, for example, a CVD method or a sputtering method is used.

  Next, as shown in FIG. 3C, the semiconductor substrate 1 is subjected to a heat treatment using, for example, an RTA (Rapid Thermal Anneal) method. By this heat treatment, a silicidation reaction occurs in a region where the metal film 15 is in contact with the silicon material, and a silicide layer 16 is formed. Silicide layer 16 is, for example, cobalt silicide (CoSi) when metal film 15 is made of cobalt. Further, the unreacted metal film 15 is selectively removed. The removal of the unreacted metal film can be performed by wet etching under the condition that the metal film 15 is etched while the silicide layer 16 is not etched.

By forming the silicide layer 16 on the gate electrode 7, the n ⁺ type semiconductor region 11, the p ⁺ type semiconductor region 12, and the extraction electrode 14, the connection resistance with a plug or the like is reduced in the region where the contact is formed. Further, the sheet resistance can be reduced in a region such as the gate electrode 7, the n ⁺ type semiconductor region 11, and the p ⁺ type semiconductor region 12 where wiring is formed. As a result, the wiring resistance and the resistance between wirings are reduced, the response speed of the element is improved, and the performance of the semiconductor device can be improved.

  Note that the silicide layer 16 itself has poor heat resistance. That is, the resistance value differs depending on the crystal phase of the silicide layer (particularly, in the case of cobalt silicide), and even if a crystal phase having a small resistance value is used, the phase may change to a crystal phase having a high resistance value by a subsequent heat treatment. In addition, a silicidation reaction may proceed at the interface between the silicide layer and the non-silicided silicon region due to a subsequent heat treatment, and the silicon element ratio in the silicide layer may be reduced to cause a stoichiometric shift from the crystal structure. . Also in this case, there is a problem of increasing the resistance value. Furthermore, when there is an unreacted metal region, the unreacted metal moves to the silicon region at the same time as the silicidation due to the subsequent heat treatment, and a void is generated in the region where the unreacted metal was present. When such a cavity is formed in the contact portion, the contact resistance increases, and when it is significant, a connection failure occurs.

  However, in the present embodiment, as described later, the subsequent heat treatment at a high temperature is suppressed, and in particular, the self-alignment film (silicon nitride film) is formed by using the plasma CVD method without using the thermal CVD method. Since the film is formed at a relatively low temperature, the problem of the heat resistance of the silicide layer 16 does not occur. That is, the silicide layer 16 can be used while avoiding the problem of heat resistance, and the performance of the semiconductor device can be improved.

  Next, as shown in FIG. 4A, a silicon nitride film 17 (third insulating film of the above item 1, etc.) is formed on the entire surface of the semiconductor substrate 1. The silicon nitride film 17 is used for self-alignment processing as described later.

  The silicon nitride film 17 is formed by a plasma CVD method at a temperature of 350 ° C. or higher, preferably 400 ° C. or higher. Since the silicon nitride film is formed at a lower temperature as compared with the thermal CVD method requiring a film forming temperature of 700 ° C. or more (for example, about 780 ° C.), it is not necessary to consider the heat resistance of the silicide layer 16 as described above. .

The silicon nitride film 17 is formed by using silane (monosilane (SiH ₄ )) and nitrogen (N ₂ ) as source gases, and does not use ammonia (NH ₃ ) as the source gas. This point is different from the passivation film described later. The passivation film is formed under the condition that the source gas contains monosilane, ammonia, and nitrogen, and the film formation temperature is about 350 ° C. For the passivation film, a source gas containing ammonia is used in order to emphasize step coverage, but a source gas containing no ammonia is used for forming the silicon nitride film 17. The passivation film is formed at a relatively low temperature of about 350 ° C., while the silicon nitride film 17 is formed at a temperature of 350 ° C. or more, preferably 400 ° C. or more. That is, ammonia is not used for forming the silicon nitride film 17, but ammonia is used for forming the passivation film. The silicon nitride film 17 is formed at a higher temperature than the passivation film. In this specification, the temperature means the substrate temperature.

By using the source gas containing no ammonia, the amount of hydrogen contained in the silicon nitride film 17 can be reduced. By reducing the amount of hydrogen in the silicon nitride film 17, a subsequent heat treatment (for example, baking at about 700 ° C. when using PSG (Phosphor Silicate Glass), SOG (Spin On Glass), or the like for the interlayer insulating film) is performed. Desorption of hydrogen from the silicon nitride film 17 can be suppressed even if ringing or densification is added. As described above, when hydrogen is released, the stress of the silicon nitride film 17 increases, which may cause peeling of the silicon nitride film 17 or poor connection at the bottom of the connection hole. As described above, the desorbed hydrogen inactivates impurities (particularly, boron) in the silicon layer (gate electrode 7, n ⁺ -type semiconductor region 11, p ⁺ -type semiconductor region 12, and extraction electrode 14) into which the impurities are introduced. And increase its resistance value. Further, impurities (especially, boron) are easily moved, and the impurities (especially, boron) which are easily diffused move to the channel region of the MISFET to change the threshold value. The increase in the stress of the silicon nitride film, the change in the resistance value and the increase in the resistance value of the silicon layer, or the change in the threshold value of the MISFET due to the release of hydrogen cause the failure and the performance deterioration of the semiconductor device. However, in the present embodiment, since the silicon nitride film 17 does not contain a large amount of hydrogen in an as-deposited state, the above problem does not occur.

Further, by using a source gas containing no ammonia, plasma damage at the time of forming the silicon nitride film 17 can be reduced. That is, it is considered that in the case where the source gas contains ammonia, the Penning effect is caused by adding ammonia, and the plasma density is increased. However, in this embodiment, since ammonia is not added to the source gas, the plasma density does not increase more than necessary, and plasma damage or ion bombardment can be suppressed. As a result, damage to a silicon layer (gate electrode 7, n ⁺ -type semiconductor region 11, p ⁺ -type semiconductor region 12, lead electrode 14, or silicide layer 16) serving as a substrate on which silicon nitride film 17 is formed is reduced, It is possible to prevent generation of dangling bonds and increase in resistance due to dangling bonds.

  As described above, the amount of hydrogen contained in the silicon nitride film 17 is relatively small, but is at least smaller than the amount of hydrogen contained in a passivation film (silicon nitride film) described later.

  Here, the experimental results of the present inventors regarding the amount of hydrogen contained in the silicon nitride film 17 or the film quality of the silicon nitride film related thereto will be described.

  FIG. 15 is a graph showing the hydrogen content in the silicon nitride film when the film formation temperature (deposition temperature) is changed. The diamond data points indicate the hydrogen content in the film in the as-deposited state, and the square data points indicate the hydrogen content in the film after annealing at 780 ° C. for 10 seconds. Line A is an experimental straight line indicating the hydrogen content in the film in the as-deposited state, and line B is an experimental straight line indicating the hydrogen content in the film after annealing. As shown by line A, the higher the deposition temperature, the lower the hydrogen content in the film, and the difference between line A and line B (that is, the amount of hydrogen released by annealing) decreases as the deposition temperature increases. Therefore, by increasing the deposition temperature, the amount of hydrogen in the as-deposited region can be reduced, and the amount of hydrogen released by annealing can be reduced.

  FIG. 16 is a graph showing the relationship between the rate of change in the amount of hydrogen due to annealing obtained from the results of FIG. 15 and the stress displacement before and after annealing. Line C is the experimental straight line obtained from each data point. Here, the rate of change in the amount of hydrogen is represented by a value obtained by dividing the amount of hydrogen after annealing by the amount of hydrogen in the as-deposited state. As shown in the figure, there is a strong correlation between the rate of change in the number of hydrogen atoms due to annealing and the stress displacement, and it can be seen that the greater the rate of change in the number of hydrogen atoms (ie, the higher the deposition temperature), the smaller the stress displacement. At the boundary of the rate of change of hydrogen number due to annealing of about 0.7 (line D), film peeling occurs in a region where the rate of change of hydrogen number is smaller (that is, the deposition temperature is lower), and larger than that (that is, the deposition temperature is larger). (High) region, film peeling does not occur. Experimentally, by setting the deposition temperature to 400 ° C., peeling of the silicon nitride film can be substantially prevented, and it is meaningful that the silicon nitride film 17 is formed preferably at 400 ° C. or higher.

  FIG. 17 is a graph plotting the sheet resistance value of the polycrystalline silicon film when the silicon nitride film is deposited on the boron-containing polycrystalline silicon film and then annealed, with respect to the annealing temperature. Each data has an error bar.

  Triangular data points are data when a silicon nitride film is formed at 400 ° C. using monosilane and nitrogen (binary) as a source gas, and line E is an experimental curve connecting the data.

  The data points indicated by black circles are data when a silicon nitride film is formed at 360 ° C. using monosilane, ammonia, and nitrogen (ternary system) as a source gas, and line F is an experimental curve connecting the data.

  Diamond-shaped data points G are data shown as a reference, and show the sheet resistance (as deposited state) of the polycrystalline silicon film when the silicon nitride film is not deposited and annealed. Of course, this case shows the lowest resistance value.

The square data points are various comparative data for obtaining consideration, point H is data when the polycrystalline silicon film was treated with NH ₃ plasma, and point I was when the polycrystalline silicon film was treated with N ₂ plasma. The data in the case, point J is the data when the polycrystalline silicon film is treated with NH ₃ / N ₂ O plasma, and the point K is the heat treatment at 950 ° C. for 10 seconds after the polycrystalline silicon film is treated with N ₂ plasma. The data in the case where it is applied are shown.

The following can be understood from the data shown in FIG. That is, when a silicon nitride film is formed at 400 ° C. using a binary gas (line E), it is larger than when a silicon nitride film is formed at 36 ° C. using a ternary gas (line F). It can be said that the polycrystalline silicon film has a low sheet resistance value (that is, close to the as-deposited polycrystalline silicon film) and does not suffer from deterioration of the polycrystalline silicon film. In order to explain the difference in the resistance value between the silicon nitride film formed by the binary gas and the silicon nitride film formed by the ternary gas, data (point H) obtained by processing with NH ₃ plasma and processing with N ₂ plasma are described. The comparison between the data (point I) in the case where the processing was performed and the data (point J) in the case where the processing was performed with the NH ₃ / N ₂ O plasma is helpful. That is, the data at points H and I correspond to the data of the binary gas (line E), the data at the point J corresponds to the data of the ternary gas (line F), and the corresponding data is the sheet resistance value. Are almost equivalent. On the other hand, NH ₃ plasma and N ₂ plasma generate plasma using a primary gas, whereas NH ₃ / N ₂ O plasma generates plasma using a binary gas, compared to the case of a single gas. It is considered that the Penning effect that the degree of plasma dissociation increases is caused. That is, it is considered that the difference between the data at points H and I and the data at point J is due to plasma damage of the polycrystalline silicon film due to the Penning effect. If the same consideration is applied to the case of the line E and the line F, the Penning effect caused by ammonia occurs when the silicon nitride film is deposited by the ternary gas (line F), Compared with the case (line E), it can be considered that the polycrystalline silicon film as the substrate receives more plasma damage, and as a result, the resistance value of the polycrystalline silicon film increases. In this embodiment, when a silicon nitride film formed using a binary gas at a substrate temperature of 400 ° C. or higher is used as the silicon nitride film 17, the resistance of the gate electrode 7 and the like is kept low, and the performance of the semiconductor device is improved. It is shown experimentally that it can be kept high.

Also, the sheet resistance of the binary gas silicon nitride film does not increase significantly even if the annealing temperature is increased, but the sheet resistance of the ternary silicon nitride film increases more greatly when the annealing temperature is increased. In order to explain whether or not the sheet resistance changes due to the annealing temperature, data (point K) obtained by performing a heat treatment at 950 ° C. for 10 seconds after treating the polycrystalline silicon film with N ₂ plasma is referred to. Become. In the case of the point K, since the polycrystalline silicon film is only processed and heat-treated with N ₂ plasma, it is considered that the sheet resistance of the polycrystalline silicon film is increased by such a process. That is, a resistance rise of the degree indicated by the point K occurs without being affected by hydrogen. On the other hand, the data of the binary gas (line E) when the heat treatment (annealing) at about 950 ° C. is performed and the data at the point K are almost the same, but the data of the ternary gas (line F). Has greatly increased resistance. That is, in the case of the binary gas, hydrogen is hardly affected, but in the case of the ternary gas, a large amount of hydrogen is released as shown in FIG. It is considered that the resistance of the polycrystalline silicon film has increased. That is, the increase in the resistance of the polycrystalline silicon film (in the case of the line F) with the increase in the annealing temperature is due to desorbed hydrogen and the impurity (boron) in the polycrystalline silicon film is inactivated. I can think. If a silicon nitride film formed at 400 ° C. or higher using a binary gas as the silicon nitride film 17 of the present embodiment is used, the resistance of the gate electrode 7 and the like can be reduced even if a process with a high processing temperature is intervened thereafter. It is shown experimentally that the fluctuation of the value can be suppressed and the reliability of the semiconductor device can be kept high.

  As described above, by applying the silicon nitride film by the plasma CVD method using silane and nitrogen as source gases to the silicon nitride film 17 of the present embodiment at a substrate temperature of 400 ° C. or more, the silicon nitride film 17 is separated. , And the desorption of hydrogen from the silicon nitride film 17 can be suppressed, and the performance and reliability of the semiconductor device can be improved.

  Next, as shown in FIG. 4B, an interlayer insulating film 18 (a fourth insulating film of the above item 1) is formed. Interlayer insulating film 18 is made of, for example, a silicon oxide film. The silicon oxide film is formed by, for example, a CVD method. Further, the interlayer insulating film 18 may use PSG, SOG, or the like. If a self-flowing film such as PSG or SOG is used, the finely processed gate electrode 7 is satisfactorily embedded, and the surface can be easily flattened. Note that when PSG, SOG, or the like is used, heat treatment for sintering or densification is performed. However, as described above, desorption of hydrogen from the silicon nitride film 17 is suppressed, so that the silicon nitride film 17 is separated. There is no problem that the resistance of the gate electrode 7 rises or fluctuates and the threshold voltage of the MISFET fluctuates.

  The surface of the interlayer insulating film 18 may be planarized by using, for example, a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 5A, a photoresist film 19 having an opening in a connection hole pattern is formed on the interlayer insulating film 18, and an etching process is performed using the photoresist film 19 as a mask. 20 (the first opening of item 1 etc.) is formed. This etching (first etching step) is performed under conditions where the silicon oxide film is etched and the silicon nitride film is hardly etched. By selecting such conditions, the silicon nitride film 17 can function as an etching stopper. Thereby, even if the connection holes have different depths, the etching can be performed so that the upper surface of silicon nitride film 17 is exposed. That is, sufficient overetching can be performed until the deepest hole can be reliably processed, and holes having different depths can be reliably processed. In addition, even if there is non-uniformity in the etching rate in the wafer surface, sufficient over-etching can be performed until the processing of the hole where etching is completed at the latest time is completed, thereby increasing the processing margin of the connection hole. Can be.

  Next, as shown in FIG. 5B, a second etching is performed to remove the silicon nitride film 17 at the bottom of the connection hole 20. Thereby, the connection hole 20 is formed. The second etching is performed under such a condition that the silicon nitride film is easily etched and the silicon oxide film is hardly etched. In the second etching, even if sufficient over-etching is performed, excessive etching of the semiconductor substrate 1 (element isolation region 2) below (underlying) can be suppressed. That is, the thickness of the silicon nitride film 17 is sufficiently smaller than the thickness of the interlayer insulating film 18, and therefore, the over-etching in the second etching step is at most two minutes of the thickness of the silicon nitride film 17. It is enough to correspond to 1 of the above. For this reason, the over-etching in the second etching step is not so large that the element isolation region 2 and the like are excessively etched, and can be suppressed to such an extent that almost no obstacle is caused. As a result, the performance and reliability of the MISFET are not reduced due to excessive etching of the element isolation region 2 and the like, and the performance and reliability of the semiconductor device can be maintained high.

  Since the silicon nitride film 17 is difficult to peel as described above, the silicon nitride film 17 does not peel in the step of opening the connection hole 20.

  Next, as shown in FIG. 6A, a plug 21 is formed in the connection hole 20 as follows, for example. First, a titanium nitride (TiN) film is formed on the entire surface of the semiconductor substrate 1 including the inside of the connection hole 20. The titanium nitride film can be formed by, for example, a CVD method. Since the CVD method is excellent in step coverage of the film, a titanium nitride film having a uniform thickness can be formed even in the fine connection hole 20. Since the silicon nitride film 17 is hard to peel off, the step coverage of the titanium nitride film is not hindered. Next, a tungsten (W) film for filling the connection hole 20 is formed. The tungsten film can be formed by, for example, a CVD method. If the CVD method is used, the inside of the fine connection hole 20 can be similarly filled with tungsten. Next, the plug 21 can be formed by removing the titanium nitride film and the tungsten film in a region other than the connection hole 20 by, for example, the CMP method.

  Next, as shown in FIG. 6B, a silicon nitride film 22 is formed on the interlayer insulating film 18 and the plug 21, and an insulating film 23 for forming a first wiring layer is formed. The silicon nitride film 22 is a film serving as an etching stopper when a groove is formed in the insulating film 23, and is made of a material having an etching selectivity with respect to the insulating film 23. The insulating film 23 is made of a material having a small dielectric constant in order to suppress the line capacitance between the wirings. The insulating film 23 is, for example, a silicon oxide film. Further, the insulating film 23 may be an organic SOG film having a small dielectric constant or an SOG film containing fluorine. Note that a second layer wiring is formed on the silicon nitride film 22 and the insulating film 23. Therefore, the total film thickness is determined by the design film thickness required for the second wiring layer. In consideration of reducing the capacitance between wirings, it is desirable that the silicon nitride film 22 made of a silicon nitride film having a high dielectric constant be as thin as possible as long as the film thickness is sufficient to achieve the stop function.

  As the silicon nitride film 22, a silicon nitride film formed by a plasma CVD method using monosilane and nitrogen as a source gas at a substrate temperature of 400 ° C. or higher can be applied as in the case of the silicon nitride film 17 described above. By applying such a film similar to the silicon nitride film 17 to the silicon nitride film 22, a film with little hydrogen desorption can be applied to the stopper film without going through a high temperature process as in the case of the thermal CVD method. . As a result, the silicon nitride film 22 does not peel off even if a step that may cause hydrogen desorption occurs after this step, and the desorption of hydrogen is suppressed. There is no room for that to happen.

  Next, as shown in FIG. 7A, a photoresist film 24 having an opening formed in a wiring pattern of a first wiring layer is patterned on the insulating film 23, and the first photoresist film 24 is used as a mask to form a first photoresist film. Etching is performed. This first etching forms a part of the wiring groove 25 in the insulating film 23. In this etching, a condition is selected in which the silicon oxide film is easily etched and the silicon nitride film is hardly etched. Thus, the silicon nitride film 22 is used as an etching stopper.

  Next, as shown in FIG. 7B, a second etching is performed by selecting conditions for etching the silicon nitride film. As described above, since the silicon nitride film 22 is formed to be sufficiently thin, the overetching in the second etching may be small, and the overetching of the interlayer insulating film 18 can be suppressed. By using the two-stage etching as described above, the depth of the wiring groove 25 can be formed uniformly and reliably.

  Next, the wiring 26 of the first wiring layer is formed inside the wiring groove 25. Wiring 26 is composed of a barrier layer and a main conductive layer. The barrier layer is, for example, a titanium nitride film, and the main conductive layer is, for example, copper. The barrier layer has a function of preventing diffusion of copper to the periphery, and for example, a titanium nitride film can be exemplified. The metal film is not limited to the titanium nitride film, but may be another metal film as long as it has a copper diffusion preventing function. For example, tantalum (Ta) or tantalum nitride (TaN) can be used instead of titanium nitride. The barrier layer in the next step and subsequent steps will be described using a titanium nitride film as an example. However, it can be replaced with tantalum, tantalum nitride, or the like as described above. The copper film functions as a main conductive layer and can be formed by, for example, a plating method. Before forming a plating film, a thin copper film can be formed as a seed film by a sputtering method. Further, the copper film may be formed by a sputtering method. In this case, after the copper film is formed by sputtering, the copper film may be fluidized by heat treatment to improve the filling characteristics in the connection hole or the wiring groove. The case where the copper film in the next step and thereafter is formed by a plating method is exemplified, but the sputtering method may be used in the same manner as described above.

  The formation of the wiring 26 is performed as follows. First, a titanium nitride film is formed on the entire surface of the semiconductor substrate 1 including the inside of the wiring groove 25, and then a copper film filling the wiring groove 25 is formed. As a result, a metal laminated film 27 made of a titanium nitride film and a copper film is formed, and the wiring groove 25 is filled with the metal laminated film 27 (FIG. 8A).

  For example, a CVD method is used to form the titanium nitride film, and a plating method is used to form the copper film. Before the formation of the copper film by the plating method, a copper seed film can be formed by, for example, a sputtering method. Thereafter, the copper film and the titanium nitride film in the region other than the wiring groove 25 are removed by the CMP method to form the wiring 26 (FIG. 8B).

  Next, as shown in FIG. 9A, a stopper insulating film 28 and an interlayer insulating film 29 are sequentially formed on the wiring 26 and the insulating film 23. Stopper insulating film 28 is made of a material having an etching selectivity with respect to interlayer insulating film 29, and may be, for example, a silicon nitride film. On the other hand, the interlayer insulating film 29 can be a silicon oxide film. Note that a silicon nitride film formed under the same conditions as the silicon nitride film 17 can be used as the stopper insulating film 28.

  Next, a photoresist film having an opening formed in the connection hole pattern is patterned on the interlayer insulating film 29, and the interlayer insulating film 29 is etched using the photoresist film as a mask. In this etching, a condition is selected in which the silicon nitride film is hardly etched and the silicon oxide film is easily etched. Thus, the interlayer insulating film 29 can be etched using the stopper insulating film 28 as an etching stopper. Further, the conditions for etching the silicon nitride film are selected, and the stopper insulating film 28 is etched. Thereby, the connection hole 30 is formed. As described above, the overetching of the base can be suppressed by the two-stage etching.

  Next, a plug 31 is formed in the connection hole 30. The plug 31 can be formed as follows. First, a barrier layer is formed on the entire surface of the semiconductor substrate 1 including the inside of the connection hole 30, and a copper (Cu) film filling the connection hole 30 is formed. After that, the copper film and the barrier film in the region other than the connection hole 30 are removed by the CMP method to form the plug 31.

  Next, as shown in FIG. 9B, a silicon nitride film 32 and a silicon oxide film 33 are formed as in the case of the wiring 26, and the silicon oxide film 33 and the silicon nitride film 32 are subjected to two-stage etching. Then, a wiring groove 34 is formed. Further, a wiring 35 similar to the wiring 26 is formed in the wiring groove 34. Note that a silicon nitride film similar to the silicon nitride film 22 can be applied to the silicon nitride film 32.

  Next, as shown in FIG. 10, similarly to the case of the plug 31, a stopper insulating film 36 and an interlayer insulating film 37 are formed, and connection holes formed in the stopper insulating film 36 and the interlayer insulating film 37 by two-stage etching. Process 38. Then, a plug 39 similar to the plug 31 is formed in the connection hole 38.

  Further, the wiring 40 is formed on the interlayer insulating film 37. The wiring 40 is, for example, a laminated film of a titanium film, an aluminum film, and a titanium nitride film. The wiring 40 is formed by sequentially depositing, for example, a titanium film, an aluminum film, and a titanium nitride film, and etching this into a predetermined pattern using photolithography.

  Next, as shown in FIG. 11, an insulating film 41 covering the wiring 40 is formed, and an insulating film 42 is formed on the insulating film 41. The insulating film 41 is made of, for example, a silicon oxide film, and is formed by, for example, a CVD method. The insulating film 42 is made of, for example, SOG. By using the SOG film, unevenness of the surface caused by the wiring 40 can be flattened. When the SOG film is formed, a heat treatment for reflowing the SOG film is performed. However, the silicon nitride films 17 and 22 and the like are excellent in the peeling resistance as described above and have a nitrided structure in which hydrogen desorption is suppressed. Since a silicon film is used, the performance and reliability of the semiconductor device can be maintained high. Note that a silicon oxide film may be further formed over the insulating film 42.

  Further, a wiring 43 (third conductor piece of item 1 or the like) is formed on the insulating film 42. The wiring 43 includes a bonding pad, and is connected to an external connection conductor piece (for example, a bump). The wiring 43 is made of, for example, an aluminum film, and is formed by, for example, a sputtering method.

  Next, as shown in FIG. 12, a silicon nitride film 44 (fifth insulating film such as item 1) covering the wiring 43 is formed. The silicon nitride film 44 is a film constituting a passivation film, and has a function of blocking moisture or impurities entering from outside the semiconductor device. In addition, transmission of α rays and the like is suppressed, and malfunction of the semiconductor device is suppressed. In order to secure these functions, the silicon nitride film 44 is required to have step coverage. Therefore, the silicon nitride film applied to the silicon nitride film 44 is formed at a substrate temperature of about 350 ° C. by a plasma CVD method using monosilane, ammonia, and nitrogen as source gases. By forming the silicon nitride film under such conditions, a film having excellent step coverage can be formed, and intrusion of moisture and impurities can be effectively prevented. As described above, the silicon nitride film 44 and the silicon nitride films 17 and 22 are formed under different conditions. That is, the silicon nitride film 44 is formed at a lower temperature than the silicon nitride films 17 and 22, and ammonia is used for forming the silicon nitride film 44, but ammonia is used for forming the silicon nitride films 17 and 22. Not used. This is one of the features of the present embodiment.

  Next, as shown in FIG. 13, a silicon oxide film 45 covering the silicon nitride film 44 is formed. The silicon nitride film 44 and the silicon oxide film 45 function as a passivation film. Further, as shown in FIG. 14, a connection hole 46 is formed in the silicon oxide film 45 and the silicon nitride film 44 to expose the wiring 43. After a bump base metal 47 is formed so as to cover the connection hole 46, a bump 48 which is a conductor piece for external connection is formed. Although the bump 48 is formed in a substantially spherical shape, a part thereof is omitted in the drawing. The connection hole 46 can be formed using photolithography and etching techniques, and the bump base metal 47 can be formed by depositing a metal film on the entire surface of the semiconductor substrate 1 and then patterning the metal film. As the bump base metal 47, for example, gold can be exemplified, and as the bump 48, gold or solder can be exemplified.

  Thereafter, the semiconductor device is mounted on a package substrate or the like to complete the semiconductor device, but the description thereof is omitted.

  Here, the bumps 48 are illustrated as the external connection conductor pieces, but other inner leads such as bonding wires may be used. When connecting to a lead frame using a gold wire or the like, molding is performed later with resin or the like, but the description of this step is omitted.

  In addition, a so-called WPP (wafer) is formed by forming a relocation wiring via a resin film of polyimide or the like, forming a bump on a pad region of the relocation wiring, and thereafter dividing the wafer to complete individual semiconductor devices. The semiconductor device of the present embodiment can also be applied to a process package.

  The effects of the present embodiment will be described with reference to FIGS. FIG. 18 is a graph showing NBTI (Negative Bias Temperature Instability) characteristics of the MISFET. In the figure, line L is data measured for the semiconductor device of the present embodiment. Lines M, N, and O are data shown for comparison, and a film corresponding to the silicon nitride film 17 of the present embodiment is formed on a plasma using monosilane, ammonia, and nitrogen as source gases at a substrate temperature of about 350 ° C. This is data when a silicon nitride film formed by a CVD method (a film formed under the same conditions as the silicon nitride film 44) is applied. The lines M, N, and O form a silicon nitride film using different devices.

  As shown in FIG. 18, the life (tau: a characteristic value indicating the rise time of the off-state current) in a situation where the source-gate voltage (Vgs) is actually used (for example, Vgs = −1 V) is equal to the line L The value shown is the largest. That is, the reliability of the semiconductor device of the present embodiment is superior to the other cases (lines M, N, O). Since the lifetime tau is represented by a logarithm, it can be seen that the reliability of the semiconductor device of the present embodiment is excellent by orders of magnitude.

FIG. 19 is a graph showing the shift amount of the flat band voltage (Vfb). As the MISFET, a p-channel MISFET in which a gate electrode is doped with a p-type impurity (boron) is used. In the figure, the data on the right side (without NH ₃ ) shows the case of the semiconductor device of this embodiment, and the data on the left side (with NH ₃ ) shows that the film corresponding to the silicon nitride film 17 of this embodiment is 550 ° C. A case is shown in which a silicon nitride film (a film formed under the same conditions as the silicon nitride film 44) formed by a plasma CVD method using monosilane, ammonia, and nitrogen as a source gas is applied at a substrate temperature of about.

As shown in FIG. 19, while the Vfb shift reaches 1.4V in the case of NH ₃ there (left), when there is no NH ₃ (right side) the Vfb shift stops at about 0.45 V. Considering that the Vfb shift is caused by impurity (boron) diffusion from the gate electrode, it can be seen that in the semiconductor device of this embodiment, the diffusion of boron from the gate electrode is effectively suppressed.

  According to this embodiment, a silicon nitride film formed by a plasma CVD method using monosilane and nitrogen (that is, without using ammonia) as a source gas at a substrate temperature of 400 ° C. or higher is applied to the silicon nitride films 17 and 22 and the like. Accordingly, peeling of the silicon nitride films 17, 22 and the like can be suppressed, and desorption of hydrogen from the silicon nitride films 17, 22 and the like can be suppressed. As a result, the performance and reliability of the semiconductor device can be kept high.

The FT-IR method compares the silicon nitride film (first silicon nitride film) applied to the silicon nitride film 17 and the like with the silicon nitride film (second silicon nitride film) applied to the silicon nitride film 44. The ratio of the Si—H bond and the Si—N bond thus obtained is different. That is, there is a relationship of R1 <R2 between the Si—H / Si—N bond ratio R1 of the first silicon nitride film and the Si—H / Si—N bond ratio R2 of the second silicon nitride film. . According to the FT-IR measurement of the present inventors, the number of Si—H bonds in the first silicon nitride film is 1 × 10 ²¹ cm ⁻³ , and the number of Si—N bonds is 10 × 10 ²¹ cm ⁻³ . On the other hand, the number of Si—H bonds in the second silicon nitride film is 11 × 10 ²¹ cm ⁻³ , and the number of Si—N bonds is 6 × 10 ²¹ cm ⁻³ . It can be considered that hydrogen desorption from the second silicon nitride film is mainly caused by Si—H bonds.

(Embodiment 2)
A method of manufacturing a DRAM (Dynamic Random Access Memory) according to the second embodiment of the present invention will be described in the order of steps with reference to FIGS. The left portion of each drawing showing the cross section of the substrate shows a region (memory cell array) in which memory cells of the DRAM are formed, and the right portion shows a peripheral circuit region.

First, as shown in FIG. 20, a semiconductor substrate (hereinafter simply referred to as “substrate”) 101 made of single-crystal silicon having a p-type specific resistance of about 10 Ωcm is prepared. An isolation trench 102 of about 350 nm is formed. Thereafter, a thin (about 10 nm-thick) silicon oxide film 106 is formed on the inner wall of the element isolation groove 102 by, for example, wet oxidation at about 850 to 900 ° C. or dry thermal oxidation at about 1000 ° C. Further, for example, a silicon oxide film (hereinafter referred to as a TEOS oxide film) having a thickness of about 400 nm is deposited by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. Embed This silicon oxide film is polished by a CMP (Chemical Mechanical Polishing) method to remove the silicon oxide film in a region other than the element isolation groove 102, and to form an element isolation region while leaving the silicon oxide film 107 inside the element isolation groove 102. I do.

  Next, as shown in FIG. 21, a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into the substrate 101, and then the impurities are diffused by a heat treatment at about 1000 ° C., thereby forming a memory cell array. A p-type well 103 and an n-type well 105 are formed on the substrate 101, and a p-type well 103 and an n-type well 104 are formed on the substrate 101 in the peripheral circuit region. Further, after the surface of the substrate 101 (the p-type well 103 and the n-type well 104) is wet-cleaned using a hydrofluoric acid-based cleaning solution, each of the p-type well 103 and the n-type well 104 is thermally oxidized at about 800 ° C. A clean gate oxide film 108 having a thickness of about 6 nm is formed on the surface.

  Next, as shown in FIG. 22, a low-resistance polycrystalline silicon film 109a with a thickness of about 100 nm doped with phosphorus (P) is deposited on the gate oxide film 108 by a CVD method, and then a sputtering method is formed on the polycrystalline silicon film 109a. Then, a WN film 109b having a thickness of about 5 nm and a W film 109c having a thickness of about 50 nm are deposited, and a silicon oxide film 110a having a thickness of about 100 nm is further deposited thereon by CVD.

  Next, a heat treatment is performed at about 800 ° C. in an atmosphere of an inert gas such as nitrogen for the purpose of relaxing the stress of the W film 109c and densifying (densifying) the WN film 109b. The silicon oxide film 110a on top of the W film 109c is protected by the surface protection of the W film 109c during this heat treatment, the silicon nitride film (110b) deposited on the silicon oxide film 110a in the next step, and the lower W film 109c. It is formed for the purpose of relaxing the stress at the interface of.

  Next, as shown in FIG. 23, after a silicon nitride film 110b having a thickness of about 100 nm is deposited on the silicon oxide film 110a, the silicon nitride film 110b is dry-etched using a photoresist film (not shown) as a mask. By doing so, the silicon nitride film 110b is left in the region where the gate electrode is formed.

  This silicon nitride film 110b is formed under the same conditions as silicon nitride film 17 described in the first embodiment. That is, it is formed at a substrate temperature of 400 ° C. or higher by a plasma CVD method using monosilane and nitrogen as source gases. The silicon nitride film 110b is used when a connection hole formed in a memory cell region is subjected to self-alignment processing as described later, and functions as a cap insulating film of a gate electrode. If hydrogen is desorbed from such a cap insulating film, the same problem as described in the first embodiment occurs. That is, there are problems of poor processing of the connection hole due to peeling, increase or change in resistance of the gate electrode, source / drain, and the like, and furthermore, change in threshold voltage of the MISFET. However, in this embodiment mode, the above problem can be avoided by using a silicon nitride film which is unlikely to desorb hydrogen as the silicon nitride film 110b serving as a cap insulating film.

  Next, after removing the photoresist film, as shown in FIG. 24, the silicon oxide film 110a, the W film 109c, the WN film 109b, and the polycrystalline silicon film 109a are dry-etched using the silicon nitride film 110b as a mask. As a result, a gate electrode 109 composed of a polycrystalline silicon film 109a, a WN film 109b and a W film 109c is formed in the memory cell array and the peripheral circuit region, and a silicon oxide film 110a and a silicon nitride film 110b are formed above these gate electrodes 109. The cap insulating film 110 is formed. Note that the gate electrode 109 formed in the memory cell array functions as a word line WL. In this embodiment, the structure in which the cap insulating film 110 includes the silicon oxide film 110a is described; however, the silicon oxide film 110a is not essential. That is, the cap insulating film 110 may be composed only of the silicon nitride film 110b.

Next, as shown in FIG. 25, an n ⁻ -type semiconductor region 111 is formed by ion-implanting an n-type impurity (phosphorus or arsenic) into the p-type well 103 on both sides of the gate electrode 109, and the n-type well 104 is formed. The p ⁻ -type semiconductor region 112 is formed by ion-implanting a p-type impurity (boron).

  Next, as shown in FIG. 26, a silicon nitride film 113 having a thickness of about 50 nm is deposited on the substrate 101. Thereafter, the upper portion of the substrate 101 of the memory cell array is covered with a photoresist film (not shown), and the silicon nitride film 113 in the peripheral circuit region is anisotropically etched to form a side wall on the side wall of the gate electrode 109 in the peripheral circuit region. The wall spacer 113a is formed.

  Like the silicon nitride film 110b, the silicon nitride film 113 is formed at a substrate temperature of 400 ° C. or higher by a plasma CVD method using monosilane and nitrogen as a source gas. In the memory cell array region, the silicon nitride film 113 is used together with the silicon nitride film 110b when a connection hole formed in the memory cell array region is self-aligned. That is, it functions as a sidewall of the gate electrode of the memory cell array. If hydrogen is desorbed from such a silicon nitride film 113, the same problem as described in the first embodiment occurs. That is, there are problems of poor processing of the connection hole due to peeling, increase or change in resistance of the gate electrode, source / drain, and the like, and furthermore, change in threshold voltage of the MISFET. However, in this embodiment mode, the above-described problem can be avoided by using a silicon nitride film in which hydrogen is not easily desorbed as the silicon nitride film 113.

  Similarly, the side wall spacer 113a formed from the silicon nitride film 113 is also formed of a silicon nitride film that hardly desorbs hydrogen. Therefore, the same effect as described above can be obtained in the peripheral circuit region.

Next, an n ⁺ -type impurity (phosphor or arsenic) is ion-implanted into the p-type well 103 in the peripheral circuit region to form an n ⁺ -type semiconductor region (source, drain) 114, and the p ⁺ -type impurity is added to the n-type well 104. By implanting (boron) ions, ap ⁺ type semiconductor region (source, drain) 115 is formed. Through the steps so far, an n-channel MISFET Qn and a p-channel MISFET Qp having a source and a drain having an LDD (Lightly Doped Drain) structure are formed in the peripheral circuit region.

  Next, as shown in FIG. 27, a silicon oxide film 116 is formed on the gate electrode 109, and the surface is flattened by chemically and mechanically polishing the silicon oxide film 116.

Next, as shown in FIG. 28, the silicon oxide film 116 of the memory cell array is dry-etched using a photoresist film (not shown) as a mask, and then, as shown in FIG. By dry etching the silicon film 113, contact holes 118 and 119 are formed above the n ⁻ type semiconductor region 111.

  The etching of the silicon oxide film 116 is performed under conditions such that the etching rate of silicon oxide (silicon oxide film 116) is higher than that of silicon nitride, so that the silicon nitride film 113 is not completely removed. Further, the etching of the silicon nitride film 113 is performed under such a condition that the etching rate of silicon nitride is higher than that of silicon (substrate) or silicon oxide so that the substrate 101 or the silicon oxide film 107 is not etched deeply. Further, the etching of the silicon nitride film 113 is performed under such a condition that the silicon nitride film 113 is anisotropically etched so that the silicon nitride film 113 is left on the side wall of the gate electrode 109 (word line WL). As a result, contact holes 118 and 119 having a small diameter are formed in a self-alignment (self-alignment) with the gate electrode 109 (word line WL).

Next, as shown in FIG. 30, an n-type impurity (phosphorous or arsenic) is ion-implanted into the p-type well 103 (n ⁻ -type semiconductor region 111) of the memory cell array through the contact holes 118 and 119 to obtain n ⁺ A type semiconductor region (source, drain) 117 is formed. Through the steps so far, the memory cell selecting MISFETs Qs formed of the n-channel type are formed in the memory cell array.

  Next, as shown in FIG. 31, a plug 120 is formed inside the contact holes 118 and 119. To form the plug 120, first, the inside of the contact holes 118 and 119 is wet-cleaned using a cleaning solution containing hydrofluoric acid, and then phosphorus (P) is formed on the silicon oxide film 116 including the insides of the contact holes 118 and 119. ), A low-resistance polycrystalline silicon film doped with an n-type impurity is deposited by a CVD method, and then this polycrystalline silicon film is etched back (or polished by a CMP method) to form only the inside of the contact holes 118 and 119. Form by leaving.

Next, as shown in FIG. 32, a silicon oxide film 121 having a thickness of about 20 nm is deposited on the silicon oxide film 116 by a CVD method, and then peripherally formed by dry etching using a photoresist film (not shown) as a mask. By dry-etching the silicon oxide film 121 in the circuit region and the silicon oxide film 116 thereunder, a contact hole 122 is formed above the source and drain (n ⁺ -type semiconductor region 114) of the n-channel MISFET Qn. A contact hole 123 is formed above the source and drain (p ⁺ type semiconductor region 115) of the type MISFET Qp. At the same time, a contact hole 124 is formed above the gate electrode 109 of the p-channel MISFET Qp in the peripheral circuit region (and the gate electrode 109 in a region (not shown) of the n-channel MISFET Qp). A through hole 125 is formed in the upper part.

Next, as shown in FIG. 33, the surface of the source and drain (n ⁺ type semiconductor region 114) of the n-channel MISFET Qn, the surface of the source and drain (p ⁺ type semiconductor region 115) of the p-channel MISFET Qp and After a silicide film 126 is formed on the surface of the plug 120 inside the contact hole 118, respectively, a plug 127 is formed inside the contact holes 122, 123, and 124 and inside the through hole 125.

  The silicide film 126 includes, for example, a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the silicon oxide film 121 including the insides of the contact holes 122, 123, and 124 and the inside of the through hole 125 by a sputtering method. Is deposited, and then heat-treated at about 650 ° C. to form the substrate 101. The plug 127 is formed by depositing a TiN film having a thickness of about 50 nm and a W film having a thickness of about 300 by a CVD method on the TiN film including the insides of the contact holes 122, 123, and 124 and the inside of the through hole 125, for example. Then, the W film, the TiN film and the Ti film on the silicon oxide film 121 are polished by a CMP method, and these films are left only in the contact holes 122, 123 and 124 and the through hole 125. I do.

By forming the silicide film 126 made of Ti silicide at the interface between the source and drain (the n ⁺ type semiconductor region 114 and the p ⁺ type semiconductor region 115) and the plug 127 formed thereon, the source and the drain (n ^Since the contact resistance between the ⁺ type semiconductor region 114 and the p ⁺ type semiconductor region 115) and the plug 127 can be reduced, the operation speed of the MISFETs (n-channel MISFET Qn and p-channel MISFET Qp) constituting the peripheral circuit is improved. I do.

  Next, as shown in FIG. 34, a bit line BL is formed on the silicon oxide film 121 in the memory cell array, and first-layer wirings 130 to 133 are formed on the silicon oxide film 121 in the peripheral circuit region. . For the bit lines BL and the first-layer wirings 130 to 133, for example, a W film having a thickness of about 100 nm is deposited on the silicon oxide film 121 by a sputtering method, and the W film is dried using a photoresist film as a mask. It is formed by etching. At this time, since the silicon oxide film 116 under the bit line BL and the wirings 130 to 133 is planarized, the bit line BL and the wirings 130 to 133 can be patterned with high dimensional accuracy.

  Next, as shown in FIG. 35, a silicon oxide film 134 having a thickness of about 300 nm is formed over the bit lines BL and the first-layer wirings 130 to 133. This silicon oxide film 134 is formed in the same manner as the silicon oxide film 116.

  Next, as shown in FIG. 36, a polycrystalline silicon film 135 having a thickness of about 200 nm is deposited on the silicon oxide film 134 by a CVD method, and then, using the photoresist film as a mask, the polycrystalline silicon film 135 of the memory cell array is formed. Is dry etched to form a groove 136 in the polycrystalline silicon film 135 above the contact hole 119.

  Next, as shown in FIG. 37, after a sidewall spacer 137 is formed on the side wall of the groove 136, using the sidewall spacer 137 and the polycrystalline silicon film 135 as a mask, oxidation of the silicon oxide film 134 and the underlying layer is performed. By dry etching the silicon film 121, a through hole 138 is formed above the contact hole 119. The sidewall spacer 137 on the side wall of the groove 136 is formed by depositing a polycrystalline silicon film on the polycrystalline silicon film 135 including the inside of the groove 136 by a CVD method, and then etching the polycrystalline silicon film anisotropically. It is formed by leaving it on the side wall of the groove 136.

  By forming the through hole 138 at the bottom of the groove 136 having the sidewall spacer 137 formed on the side wall, the diameter of the through hole 138 is smaller than the diameter of the contact hole 119 below. As a result, even if the memory cell size is reduced, the alignment margin between the bit line BL and the through-hole 138 is secured, so that the plug 139 embedded in the through-hole 138 in the next step and the bit line BL are short-circuited. Can be reliably prevented.

  Next, after the polycrystalline silicon film 135 and the sidewall spacers 137 are removed by dry etching, plugs 139 are formed inside the through holes 138 as shown in FIG. The plug 139 is formed by depositing a low-resistance polycrystalline silicon film doped with an n-type impurity (phosphorus) on the silicon oxide film 134 including the inside of the through hole 138 by a CVD method, and then etching back the polycrystalline silicon film. This is formed by leaving only inside the through hole 138.

  Next, as shown in FIG. 39, a silicon nitride film 140 having a thickness of about 100 nm is deposited on the silicon oxide film 134 by a CVD method, and a silicon oxide film 141 is deposited on the silicon nitride film 140 by a CVD method. After the deposition, the silicon oxide film 141 of the memory array is dry-etched using a photoresist film (not shown) as a mask, and subsequently the silicon nitride film 140 under the silicon oxide film 141 is dry-etched, thereby forming a through-hole. A groove 142 is formed above the hole 138. Since the lower electrode of the information storage capacitance element is formed along the inner wall of the groove 142, in order to increase the surface area of the lower electrode and increase the amount of stored charges, the silicon oxide film 141 forming the groove 142 must be formed. It is necessary to deposit with a large film thickness (for example, about 1.3 μm).

  Note that as the silicon nitride film 140, a silicon nitride film formed by a plasma CVD method using monosilane and nitrogen as source gases at a substrate temperature of 400 ° C. or higher may be used.

Next, as shown in FIG. 40, an amorphous silicon film 143a having a thickness of about 50 nm doped with an n-type impurity (phosphorus) is deposited on the silicon oxide film 141 including the inside of the groove 142 by a CVD method. By etching back the amorphous silicon film 143a on the silicon oxide film 141, the amorphous silicon film 143a is left along the inner wall of the groove 142. Thereafter, the surface of the amorphous silicon film 143a remaining inside the groove 142 is wet-cleaned with a hydrofluoric acid-based cleaning solution, and then monosilane (SiH ₄ ) is supplied to the surface of the amorphous silicon film 143a in a reduced pressure atmosphere. The substrate 101 is heat-treated to polycrystallize the amorphous silicon film 143a and grow silicon grains on the surface thereof. Thus, a polycrystalline silicon film 143 having a roughened surface is formed along the inner wall of groove 142. This polycrystalline silicon film 143 is used as a lower electrode of the information storage capacitor.

Next, as shown in FIG. 41, a tantalum oxide (Ta ₂ O ₅ ) film 144 having a thickness of about 15 nm is deposited on the silicon oxide film 141 including the inside of the groove 142 by a CVD method. By performing heat treatment at about 800 ° C. for 3 minutes, the tantalum oxide film 144 is crystallized, and defects are repaired by supplying oxygen to the film. This tantalum oxide film 144 is used as a capacitance insulating film of the information storage capacitance element. Further, a TiN film 145 having a thickness of about 150 nm is deposited on the tantalum oxide film 144 including the inside of the groove 142 by using both the CVD method and the sputtering method, and then using a photoresist film (not shown) as a mask. By dry-etching the TiN film 145 and the tantalum oxide film 144, an information storage device composed of an upper electrode made of the TiN film 145, a capacitive insulating film made of the tantalum oxide film 144, and a lower electrode made of the polycrystalline silicon film 143. The capacitor C is formed. Through the steps so far, a DRAM memory cell including the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs is completed.

The capacitive insulating film of the information storage capacitive element C is not only the tantalum oxide film 144 but also a perovskite type or a composite type such as PZT, PLT, PLZT, PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , BST, SBT or Ta ₂ O _5. It may be constituted by a film containing a high dielectric or ferroelectric having a perovskite crystal structure as a main component.

  Next, as shown in FIG. 42, the wiring of the second wiring layer is formed on the information storage capacitor C by the following method.

  First, a silicon oxide film 150 having a thickness of about 100 nm is deposited on the information storage capacitor C by a CVD method. Next, dry etching is performed on the silicon oxide films 150 and 141, the silicon nitride film 140, and the silicon oxide film 134 on the first layer wirings 130 and 133 in the peripheral circuit region using a photoresist film (not shown) as a mask. After the through holes 151 and 152 are formed, a plug 153 is formed inside the through holes 151 and 152. The plug 153 is formed, for example, by depositing a TiN film with a thickness of about 100 nm on the silicon oxide film 150 by a sputtering method, further depositing a W film with a thickness of about 500 nm on the TiN film by a CVD method, and then etching these films. It is formed by backing and leaving inside the through holes 151 and 152. Further, a TiN film having a thickness of about 50 nm, an Al (aluminum) alloy film having a thickness of about 500 nm, and a Ti film having a thickness of about 50 nm are deposited on the silicon oxide film 150 by, for example, a sputtering method. The wirings 154 to 156 are formed by dry-etching these films using a mask (not shown) as a mask.

  Thereafter, an interlayer insulating film covering the wirings 154 to 156, a third-layer wiring, and a passivation film composed of a silicon oxide film and a silicon nitride film are deposited thereon, but illustration thereof is omitted. Through the above steps, the DRAM of the present embodiment is substantially completed.

  Note that the passivation film of the present embodiment is similar to the passivation film of the first embodiment. That is, at a substrate temperature of about 350 ° C., a silicon nitride film is formed by a plasma CVD method using monosilane, ammonia, and nitrogen as source gases, and this is used as a passivation film.

  Further, the inner lead of the present embodiment can be configured in the same manner as in the first embodiment. Therefore, its illustration and description are omitted.

  According to the present embodiment, monosilane and nitrogen (ie, without using ammonia) are used as the source gas at a substrate temperature of 400 ° C. or more for the silicon nitride film 110b and the silicon nitride film 113 (sidewall spacer 113a) serving as the cap insulating film. Since the silicon nitride film formed by the plasma CVD method is applied, peeling of these silicon nitride films can be suppressed, and desorption of hydrogen from the silicon nitride film can be suppressed. As a result, the performance and reliability of the DRAM can be maintained high.

  In this embodiment, an example has been described in which a polycrystalline silicon film is used as a lower electrode as a capacitor of a DRAM. However, platinum (Pt), ruthenium (Ru), iridium (Ir), or an oxide thereof may be used. good. Further, although the structure of the capacitor lower electrode has been exemplified by the cylindrical structure formed in the groove, a simple stack type structure may be used.

  In the DRAM of the second embodiment, the MISFET in the peripheral circuit region may have a dual gate structure as described in the first embodiment. That is, the gate electrode of the p-channel MISFET may be formed of a p-type polycrystalline silicon film, and the gate electrode of the n-channel MISFET may be formed of an n-type polycrystalline silicon film.

  Further, the MISFET of the first embodiment and the DRAM of the second embodiment may be formed on one substrate, and the present invention may be applied to a system LIS.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in Embodiments 1 and 2, monosilane is exemplified as the silicon-based source gas for the silicon nitride film, but dichlorosilane (SiCl ₂ H ₂ ) or disilane (Si ₂ H ₆ ) may be used.

  INDUSTRIAL APPLICABILITY The present invention is effective when applied to improvement in performance and reliability of a semiconductor device, and has industrial applicability.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps; 5 is a graph showing the hydrogen content in a silicon nitride film when the film formation temperature is changed. 4 is a graph showing a relationship between a hydrogen content change rate due to annealing of a silicon nitride film and a stress displacement before and after annealing. 4 is a graph plotting the sheet resistance value of a polycrystalline silicon film when annealing is performed on a silicon nitride film on a boron-containing polycrystalline silicon film with respect to an annealing temperature. 4 is a graph showing NBTI characteristics of a MISFET. 6 is a graph showing a shift amount of a flat band voltage. FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps; FIG. 9 is a cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps;

Explanation of reference numerals

Reference Signs List 1 semiconductor substrate 2 element isolation region 3 p-type well 4 n-type well 5 silicon oxide film 6 polycrystalline silicon film 6n n-type region 6p p-type region 7 gate electrode 8 n-type semiconductor region 9 p-type semiconductor region 10 sidewall spacer 11 n ⁺ type semiconductor region 12 p ⁺ type semiconductor region 13 insulating film 14 lead electrode 15 metal film 16 silicide layer 17 silicon nitride film 18 interlayer insulating film 19 photoresist film 20 connection hole 21 plug 22 silicon nitride film 23 insulating film 24 photoresist Film 25 wiring groove 26 wiring 27 metal laminated film 28 stopper insulating film 29 interlayer insulating film 30 connection hole 31 plug 32 silicon nitride film 33 silicon oxide film 34 wiring groove 35 wiring 36 stopper insulating film 37 interlayer insulating film 38 connection hole 39 plug 40 Wirings 41 and 42 Insulating film 43 Wiring 44 Silicon nitride film 45 Silicon oxide film 46 Connection hole 7 Under bump metal 48 Bump 101 Semiconductor substrate 102 Element isolation groove 103 P-type well 104 N-type well 107 Silicon oxide film 108 Gate oxide film 109 Gate electrode 109a Low resistance polycrystalline silicon film 109b WN film 109c W film 110 Cap insulating film 110a Silicon oxide film 110b silicon nitride film 111 n ⁻ type semiconductor region 112 p ⁻ type semiconductor region 113 silicon nitride film 113a sidewall spacer 114 n ⁺ type semiconductor region (source, drain)
115p ⁺ type semiconductor region (source, drain)
116 silicon oxide film 118, 119 contact hole 120 plug 121 silicon oxide film 122-124 contact hole 125 through hole 126 silicide film 127 plug 130-133 wiring 134 silicon oxide film 135 W film 136 groove 137 sidewall spacer 138 through hole 139 plug 140 Silicon nitride film 141 Silicon oxide film 142 Groove 143a Amorphous silicon film 143 Polycrystalline silicon film 144 Tantalum oxide film 145 TiN film 150 Silicon oxide film 151, 152 Through hole 153 Plug 154-156 Wiring C Information storage capacitor BL Bit line Qn n-channel type MISFET
Qp p-channel type MISFET
R conductor film

Claims (5)

A method of manufacturing a semiconductor device, comprising: forming a first silicon nitride film for self-alignment processing, and further forming a second silicon nitride film for passivation,
The first silicon nitride film is formed by a plasma CVD method using silane and nitrogen as source gases, and the second silicon nitride film is formed by a plasma CVD method using silane, ammonia and nitrogen as source gases. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the formation of the first silicon nitride film is performed at a higher temperature than the formation of the second silicon nitride film. .   2. The method for manufacturing a semiconductor device according to claim 1, wherein the formation of the first silicon nitride film is performed at a temperature of 400 degrees or more. A semiconductor device having a first silicon nitride film for self-alignment processing and a second silicon nitride film for passivation,
Between the Si-H / Si-N bond ratio R1 of the first silicon nitride film by FT-IR analysis and the Si-H / Si-N bond ratio R2 of FT-IR analysis of the second silicon nitride film Has a relationship of R1 <R2. The semiconductor device according to claim 4, wherein
A semiconductor device, wherein a Si—H bond of the first silicon nitride film by FT-IR analysis is 2 × 10 ²¹ cm ⁻³ or less.

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