JP2004221350A - Semiconductor chip, semiconductor wafer, semiconductor device and manufacturing method thereof, circuit board, and electronic equipment - Google Patents

Abstract

An object of the present invention is to form a through electrode into a shape suitable for good electrical connection.
A semiconductor chip includes a semiconductor substrate having first and second surfaces, and at least a portion formed at a position closer to the first surface than the second surface of the semiconductor substrate. It has an integrated circuit 16 embedded therein and a through electrode 50. The penetrating electrode 50 penetrates the first and second surfaces 12 and 14 of the semiconductor substrate 10 and has a first end surface 52 exposed on the first surface 12 and a second end surface exposed on the second surface 14. 54. The second end face 54 is formed larger than the first end face 52.
[Selection diagram] FIG.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor chip, a semiconductor wafer, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
[0002]
[Prior art]
[Patent Document 1]
JP-A-9-313295
BACKGROUND OF THE INVENTION
A three-dimensional mounting semiconductor device has been developed. It is also known to form a through electrode on a semiconductor chip to enable three-dimensional mounting. The through electrode is formed so as to protrude from the semiconductor chip. A conventionally known through electrode has a shape in which it is difficult to achieve good electrical connection.
[0004]
An object of the present invention is to form a through electrode into a shape suitable for good electrical connection.
[0005]
[Means for Solving the Problems]
(1) A semiconductor chip according to the present invention includes: a semiconductor substrate having first and second surfaces;
An integrated circuit at least partially formed at a position closer to the first surface than the second surface of the semiconductor substrate;
A first end face that penetrates the first and second faces of the semiconductor substrate and is exposed on the first face, and a second end face that is exposed on the second face; A through electrode in which the second end face is formed larger than the first end face;
Having. According to the present invention, the through electrode is formed such that the second end surface exposed on the second surface of the semiconductor substrate remote from the integrated circuit is larger than the opposite first end surface. Therefore, a good electrical connection that has not been provided in the past can be achieved.
(2) In this semiconductor chip,
The through electrode includes a first end protruding from the first surface, a second end protruding from the second surface, and an intermediate portion located between the first and second ends. And a part,
The second end may be formed to have a larger width or diameter than the first end.
(3) In this semiconductor chip,
The second end may be formed to have a larger width or diameter than the intermediate part.
(4) This semiconductor chip
A first insulating layer formed on the first surface;
A second insulating layer formed on the second surface;
May be further provided.
(5) In this semiconductor chip,
A peripheral portion of the second end may be formed on the second insulating layer.
(6) This semiconductor chip
A pad may be further provided on the first insulating layer, the pad being electrically connected to at least one of the integrated circuit and the through electrode.
(7) In this semiconductor chip,
The through electrode may penetrate the pad.
(8) A semiconductor wafer according to the present invention includes a semiconductor substrate having first and second surfaces;
A plurality of integrated circuits at least partially formed at positions closer to the first surface than the second surface of the semiconductor substrate;
A first end face that penetrates the first and second faces of the semiconductor substrate and is exposed on the first face, and a second end face that is exposed on the second face; A plurality of through electrodes each having the second end face larger than the first end face;
Having. According to the present invention, the through electrode is formed such that the second end surface exposed on the second surface of the semiconductor substrate remote from the integrated circuit is larger than the opposite first end surface. Therefore, a good electrical connection that has not been provided in the past can be achieved.
(9) In this semiconductor wafer,
Each of the through electrodes is located between a first end protruding from the first surface, a second end protruding from the second surface, and the first and second ends. And an intermediate part,
The second end may be formed to have a larger width or diameter than the first end.
(10) In this semiconductor wafer,
The second end may be formed to have a larger width or diameter than the intermediate part.
(11) This semiconductor wafer
A first insulating layer formed on the first surface;
A second insulating layer formed on the second surface;
May be further provided.
(12) In this semiconductor wafer,
A peripheral portion of the second end may be formed on the second insulating layer.
(13) This semiconductor wafer is
A pad electrically connected to at least one of the one integrated circuit and the one through electrode may be further provided on the first insulating layer.
(14) In this semiconductor wafer,
Any one of the through electrodes may penetrate the pad.
(15) A semiconductor device according to the present invention includes the plurality of stacked semiconductor chips,
Upper and lower semiconductor chips of the plurality of semiconductor chips are electrically connected by the through electrodes.
(16) A circuit board according to the present invention has the above semiconductor chip mounted thereon.
(17) A circuit board according to the present invention has the above-described semiconductor device mounted thereon.
(18) An electronic device according to the present invention includes the above semiconductor chip.
(19) An electronic apparatus according to the present invention includes the above-described semiconductor device.
(20) In the method for manufacturing a semiconductor device according to the present invention, at least a part of the integrated circuit is formed at a position having the first and second surfaces and closer to the first surface than the second surface. A semiconductor substrate having a first end surface penetrating through the first and second surfaces thereof and being exposed on the first surface, and a second end surface being exposed on the second surface. The method includes forming a through electrode in which the second end face is formed larger than the first end face. According to the present invention, the through electrode is formed such that the second end surface exposed on the second surface of the semiconductor substrate remote from the integrated circuit is larger than the opposite first end surface. This through electrode enables a good electrical connection that has not been available in the past.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0007]
1A to 3D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. In this embodiment, a semiconductor substrate 10 is used as shown in FIG. The semiconductor substrate 10 has first and second surfaces 12 and 14. The second surface 14 is a surface opposite to the first surface 12.
[0008]
At least a part (part or the whole) of an integrated circuit (for example, a circuit having a transistor or a memory) 16 is formed in the semiconductor substrate 10. At least a part of each of the plurality of integrated circuits 16 may be formed in the semiconductor substrate 10, or at least a part of one integrated circuit 16 may be formed. The integrated circuit 16 is formed at a position closer to the first surface 12 than to the second surface 14.
[0009]
On the first surface 12 of the semiconductor substrate 10, a first insulating layer (for example, a passivation film) 18 is formed. The passivation film 18 can be formed of, for example, SiO ₂ , SiN, a polyimide resin, or the like. The first insulating layer 18 is formed so as to cover the integrated circuit 16.
[0010]
A plurality of pads 20 are formed on the semiconductor substrate 10. Each pad 20 is electrically connected to the integrated circuit 16. Each pad 20 may be formed of aluminum. The shape of the surface of the pad 20 is not particularly limited, but is often rectangular. The pad 20 is formed at a position closer to the first surface 12 than the second surface 14 (for example, above the first surface 12). The pad 20 may be formed on the first insulating layer 18. A pad 20 and a wiring (not shown) for connecting the integrated circuit 16 and the pad 20 may be formed on the first insulating layer 18. Further, another passivation film (insulating film) not shown may be formed so as to avoid at least a part of the surface of the pad 20.
[0011]
As shown in FIG. 1B, a recess 22 is formed in a semiconductor substrate 10 from a first surface 20 thereof. The first surface 20 is a surface on which the pad 20 is formed (the side on which the integrated circuit 16 is formed). The recess 22 is formed so as to avoid the elements and wiring of the integrated circuit 16. A through hole 24 may be formed in the pad 20. Etching (dry etching or wet etching) may be applied to the formation of the through hole 24. The etching may be performed after a resist (not shown) patterned by a lithography process is formed. If the first insulating layer 18 is formed below the pad 20, a through hole 26 is also formed in this case. When the etching of the pad 20 stops at the first insulating layer 18, the etchant used for etching the pad 20 may be replaced with another etchant to form the through hole 26. In that case, a resist (not shown) patterned by the lithography process may be formed again.
[0012]
The recess 22 is formed in the semiconductor substrate 10 so as to communicate with the through hole 24 (and the through hole 26). The combination of the through hole 24 (and the through hole 26) and the recess 22 can also be referred to as a recess. Etching (dry etching or wet etching) can also be applied to the formation of the recess 22. The etching may be performed after a resist (not shown) patterned by a lithography process is formed. Alternatively, a laser (for example, a CO ₂ laser, a YAG laser, or the like) may be used to form the recess 22. The laser may be applied to the formation of the through holes 24, 26. The formation of the recess 22 and the through holes 24 and 26 may be performed continuously by one type of etchant or laser. Sand blasting may be applied to the formation of the recess 22.
[0013]
As shown in FIG. 1C, an insulating layer 28 may be formed inside the concave portion 22. The insulating layer 28 may be an oxide film. For example, when the semiconductor substrate 10 is formed from Si, the insulating layer 28 may be SiO ₂ or SiN. The insulating layer 28 is formed on the bottom of the recess 22. The insulating layer 28 is formed on the inner wall surface of the recess 22. However, the insulating layer 28 is formed so as not to fill the recess 22. That is, a concave portion is formed by the insulating layer 28. The insulating layer 28 may be formed on the inner wall surface of the through hole 26 of the first insulating layer 18.
[0014]
In the present embodiment, the insulating layer 28 is formed avoiding the inner wall surface of the through hole 24 of the pad 20. That is, the inner wall surface of the through hole 24 is exposed from the insulating layer 28. Note that the insulating layer 28 may be formed to cover the pad 20, and a part of the insulating layer 28 may be etched (dry etching or wet etching) to expose a part of the pad 20. The etching may be performed after a resist (not shown) patterned by a lithography process is formed.
[0015]
As shown in FIG. 1D, a resist layer 30 may be formed. The resist layer 30 may be formed of an energy-sensitive resin such as light, ultraviolet light, infrared light, or an electron beam. The resist layer 30 is formed above the first surface 12 (for example, on the first insulating film 18). The resist layer 30 is formed so as to have the opening 32. The opening 32 is formed so as to overlap the recess 22. The resist layer 30 is formed avoiding the inner wall surface of the through hole 24 of the pad 20. The resist layer 30 may be formed avoiding the opening end of the through hole 24 of the pad 20.
[0016]
As shown in FIG. 2A, a conductive portion 34 is provided in the concave portion 22 (for example, inside the insulating layer 28). The conductive portion 34 may be formed of Cu, W, or the like. After forming the outer layer portion, the conductive portion 34 may form the central portion thereof. The central portion can be formed of any of Cu, W, and doped polysilicon (for example, low-temperature polysilicon). The outer layer part may include at least a barrier layer. The barrier layer prevents the material of the central portion or the seed layer described below from diffusing into the semiconductor substrate 10 (for example, Si). The barrier layer may be formed of a different material (for example, TiW, TiN) from the central part. When the central part is formed by electrolytic plating, the outer layer part may include a seed layer. The seed layer is formed after forming the barrier layer. The seed layer is formed of the same material (for example, Cu) as the central part. The conductive portion 34 (at least the central portion) may be formed by electroless plating or an inkjet method.
[0017]
The conductive portion 34 may be formed so as to be electrically connected to the pad 20. For example, the conductive portion 34 may be formed so as to contact the inner wall surface or the opening end of the through hole 24 of the pad 20. The conductive portion 34 may be formed so as to protrude from the first surface 12 (further, from the pad 20). Note that the formation of the resist layer 30 may be omitted as long as the conductive portion 34 can be formed in a necessary region (for example, only in the concave portion 22). A conductive layer 36 may be formed on the conductive portion 34. When the conductive portion 34 is formed of a material that is easily oxidized (for example, copper), the conductive layer 36 may be formed of a material that is hardly oxidized. The conductive layer 36 may be formed of gold, tin, hard solder or soft solder (for example, solder). Then, as shown in FIG. 2B, when the resist layer 30 is formed, it is removed. Further, a reinforcing member such as a glass plate, a resin layer, or a resin tape may be provided on the first surface 20 side of the semiconductor substrate 10 (for example, attached with an adhesive or an adhesive sheet).
[0018]
As shown in FIG. 2C, when the thickness of the semiconductor substrate 10 is reduced, a second surface (a surface opposite to the first surface 12) 14 of the semiconductor substrate 10 is shaved. Then, the insulating layer 28 is exposed. For example, the semiconductor substrate 10 may be abraded by at least one of mechanical polishing / grinding and chemical polishing / grinding until the insulating layer 28 formed in the concave portion 22 is exposed. Thereafter, the semiconductor substrate 10 may be etched until the insulating layer 28 is exposed. The etching may be performed by an etchant having a property that the etching amount for the semiconductor substrate (for example, Si) 10 is larger than the etching amount for the insulating layer (for example, SiO ₂ ) 28. The etchant may be SF ₆ or CF ₄ or Cl ₂ gas. The etching may be performed using a dry etching apparatus. Alternatively, the etchant may be a mixture of hydrofluoric acid and nitric acid or a mixture of hydrofluoric acid, nitric acid and acetic acid.
[0019]
As shown in FIG. 2D, a second insulating layer 38 may be formed on the second surface 14 of the semiconductor substrate 10. The second insulating layer 38 is formed so as to have the opening 39. At least a central portion of the insulating layer 28 exposed from the second surface 14 is exposed in the opening 39. The second insulating layer 38 may be formed so as to cover the periphery of the insulating layer 28. The second insulating layer 38 may be an oxide film (for example, SiO ₂ ) or a resin (for example, polyimide).
[0020]
As shown in FIG. 3A, a resist layer 40 may be formed. The resist layer 40 may be formed of an energy-sensitive resin such as light, ultraviolet light, or an electron beam. The resist layer 40 is formed above the second surface 14 (for example, on the second insulating film 38). The resist layer 40 is formed so as to have the opening 42. The resist layer 40 is formed such that the opening 42 overlaps the region where the conductive portion 34 is formed. For example, the resist layer 40 is formed such that the entire region where the conductive portion 34 is formed is included inside the opening 42 (so that the opening 42 is larger than the region where the conductive portion 34 is formed). The second insulating layer 38 may be exposed in the opening 42. The insulating layer 28 may be exposed in the opening 42.
[0021]
As shown in FIG. 3B, a portion of the insulating layer 28 that is exposed inside the opening 42 (and inside the opening 39) is removed. Etching may be applied for the removal. As a result, the conductive portion 34 is exposed inside the opening 42 (and inside the opening 39).
[0022]
As shown in FIG. 3C, a second conductive portion 44 is provided on the conductive portion 34 on the second surface 14 side. The second conductive portion 44 is provided inside the opening 42 of the resist layer 40. The material of the second conductive portion 44 and the method for forming the same correspond to the contents of the above-described conductive portion (first conductive portion) 34. The second conductive portion 44 is formed so as to be larger (for example, larger in width or diameter) than the conductive portion 34. The second conductive portion 44 may be formed so that a part thereof (for example, a peripheral portion) is placed on the second insulating layer 38. A second conductive layer 46 may be formed on the second conductive portion 44. The content of the above-described conductive layer (first conductive layer) 36 corresponds to the second conductive layer 46. As shown in FIG. 3D, the resist layer 40 is removed.
[0023]
For example, the through-electrode 50 can be formed in the semiconductor substrate 10 as shown in FIG. The through electrode 50 may include the conductive part 34, the conductive layer 36, the second conductive part 44, and the second conductive layer 46. The through electrode 50 penetrates the first and second surfaces 12 and 14. The through electrode 50 has a first end surface 54 exposed on the first surface 12. The through electrode 50 has a second end surface 54 exposed on the second surface 14. The second end face 54 is formed larger than the first end face 52. The through electrode 50 has a first end 56 that protrudes from the first surface 12. The through electrode 50 has a second end 58 protruding from the second surface 14. The through electrode 50 has an intermediate portion 60 located between the first and second ends 56 and 58. The second end 58 may be formed to have a greater width or diameter than the first end 56. The second end 58 may be formed to have a greater width or diameter than the middle 60. The peripheral edge of the second end 58 may be formed on the second insulating layer 38.
[0024]
For example, a semiconductor wafer 70 having a through electrode 50 (see FIG. 4) is obtained through the above steps. In this case, a plurality of integrated circuits 16 are formed on the semiconductor substrate 10, and through electrodes 50 are formed corresponding to the respective integrated circuits 16. The detailed structure can be derived from the above-described manufacturing method. Alternatively, a semiconductor chip 80 having the through electrode 50 (see FIG. 6) is obtained. In this case, one integrated circuit 16 is formed on the semiconductor substrate 10. The detailed structure can be derived from the above-described manufacturing method.
[0025]
The semiconductor wafer 70 may be cut (for example, dicing). For example, as shown in FIG. 4, the semiconductor wafer 70 is cut (for example, dicing). For cutting, a cutter (for example, a dicer) 72 or a laser (for example, a CO ₂ laser, a YAG laser, or the like) may be used. Thus, a semiconductor chip 80 having the through electrodes 50 (see FIG. 6) is obtained. The structure is a content that can be derived from the above-described manufacturing method.
[0026]
The method for manufacturing a semiconductor device may include stacking a plurality of semiconductor substrates 10. For example, as shown in FIG. 5, a plurality of semiconductor wafers 70 having through electrodes 50 may be stacked. Alternatively, as shown in FIG. 6, a plurality of semiconductor chips 80 having through electrodes 50 may be stacked. Alternatively, a semiconductor chip 80 having the through electrode 50 and a plurality of semiconductor wafers 70 having the through electrode 50 may be stacked.
[0027]
The upper and lower semiconductor substrates 10 of the stacked semiconductor substrates 10 are electrically connected through the through electrodes 50. Specifically, the upper and lower through electrodes 50 may be electrically connected to each other. For electrical connection, solder bonding or metal bonding may be applied, an anisotropic conductive material (such as an anisotropic conductive film or an anisotropic conductive paste) may be used, and an insulating adhesive may be used. May be applied by utilizing the contraction force, or a combination thereof.
[0028]
FIG. 7 is a diagram showing a semiconductor device (stacked semiconductor device) according to an embodiment of the present invention. The stacked semiconductor device includes a plurality of semiconductor chips 80 having the through electrodes 50 described above. The plurality of semiconductor chips 80 are stacked. The upper and lower through electrodes 50 may be brazed. An insulating material (for example, an adhesive, a resin, or an underfill material) 84 may be provided between the upper and lower semiconductor chips 80. The bonding state of the through electrode 50 is maintained or reinforced by the insulating material 84. The content that can be derived from the method for manufacturing a semiconductor device according to this embodiment can be applied to the semiconductor device according to this embodiment.
[0029]
The plurality of stacked semiconductor chips 80 may be mounted on the wiring board 100. One semiconductor chip (the outermost semiconductor chip 80 of the stacked semiconductor chips 80) may be mounted on a wiring board (for example, an interposer) 100. Face-down bonding may be applied to the mounting. In that case, the semiconductor chip 80 having the outermost (eg, lowermost) through electrode 50 in the direction of the first surface 12 is mounted on the wiring board 100. For example, a protruding portion (for example, the first end 56) of the through electrode 50 from the first surface 12 may be electrically connected (for example, joined) to the wiring pattern 102. An insulating material (for example, an adhesive, a resin, or an underfill material) 84 may be provided between the semiconductor chip 80 and the wiring board 100.
[0030]
According to the present embodiment, since the area of the second end face 54 of the through electrode 50 is large, there is room for the positional deviation when the semiconductor chips 80 are stacked. Further, as shown in FIG. 7, when the semiconductor chip 80 is face-down bonded, the second end face 54 faces upward. Then, the first end face 52 of the through electrode 50 of another semiconductor chip 80 is joined to the second end face 54. The second end face 54 is larger than the first end face 52. Since the second end face 54 faces upward, even when a concave portion is formed, a void is unlikely to be formed when the first and second end faces 52 and 54 are joined. Further, a short circuit between the upper and lower semiconductor chips 80 can be prevented by the second insulating layer 38 formed on the semiconductor chip 80. Furthermore, even if a part of the through electrode 50 (for example, the conductive part 34) is formed of a metal (for example, Cu) that is easily oxidized, at least one of the first and second end surfaces 52 and 54 is oxidized such as gold. If it is formed of a difficult metal, a good electrical connection can be obtained, and a high yield can be secured.
[0031]
Alternatively, as an example (not shown), the stacked semiconductor chips 80 may be face-up bonded to the wiring board 100. In that case, the protrusion (for example, the second end 58) of the through electrode 50 from the second surface 14 may be electrically connected (for example, joined) to the wiring pattern 102. External terminals (for example, solder balls) 104 that are electrically connected to the wiring pattern 102 are provided on the wiring substrate 100. Alternatively, a stress relaxation layer may be formed on the semiconductor chip 80, a wiring pattern may be formed from the pad 20 thereon, and external terminals may be formed thereon. Other details can be derived from the manufacturing method described above.
[0032]
FIG. 8 shows a circuit board 1000 on which the semiconductor device 1 formed by stacking a plurality of semiconductor chips is mounted. The plurality of semiconductor chips are electrically connected by the through electrodes 50 described above. As an electronic apparatus having the above-described semiconductor device, a notebook personal computer 2000 is shown in FIG. 9, and a mobile phone 3000 is shown in FIG.
[0033]
The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the invention includes configurations substantially the same as the configurations described in the embodiments (for example, a configuration having the same function, method, and result, or a configuration having the same object and result). Further, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. Further, the invention includes a configuration having the same operation and effect as the configuration described in the embodiment, or a configuration capable of achieving the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIGS. 1A to 1D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2A to 2D are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 3A to 3D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a diagram showing a circuit board according to the embodiment of the present invention.
FIG. 9 is a diagram showing an electronic apparatus according to the embodiment of the present invention.
FIG. 10 is a diagram showing an electronic apparatus according to the embodiment of the present invention.
[Explanation of symbols]
10 semiconductor substrate, 12 first surface, 14 second surface, 16 integrated circuit,
18 first insulating layer, 20 pads, 38 second insulating layer,
50 through electrode, 52 first end face, 54 second end face,
56 first end, 58 second end, 60 middle

Claims (20)

A semiconductor substrate having first and second surfaces;
An integrated circuit at least partially formed at a position closer to the first surface than the second surface of the semiconductor substrate;
A first end face that penetrates the first and second faces of the semiconductor substrate and is exposed on the first face, and a second end face that is exposed on the second face; A through electrode in which the second end face is formed larger than the first end face;
A semiconductor chip having: The semiconductor chip according to claim 1,
The through electrode includes a first end protruding from the first surface, a second end protruding from the second surface, and an intermediate portion located between the first and second ends. And a part,
A semiconductor chip, wherein the second end is formed to have a larger width or diameter than the first end. The semiconductor chip according to claim 2,
A semiconductor chip wherein the second end is formed to have a larger width or diameter than the intermediate part. The semiconductor chip according to claim 2 or 3,
A first insulating layer formed on the first surface;
A second insulating layer formed on the second surface;
A semiconductor chip further comprising: The semiconductor chip according to claim 4,
A semiconductor chip in which a peripheral edge of the second end is formed on the second insulating layer. The semiconductor chip according to claim 4 or 5,
A semiconductor chip further comprising a pad on the first insulating layer, the pad being electrically connected to at least one of the integrated circuit and the through electrode. The semiconductor chip according to claim 6,
A semiconductor chip, wherein the through electrode penetrates the pad. A semiconductor substrate having first and second surfaces;
A plurality of integrated circuits each at least partially formed at a position closer to the first surface than the second surface of the semiconductor substrate;
A first end face that penetrates through the first and second faces of the semiconductor substrate and is exposed on the first face; and a second end face that is exposed on the second face. A plurality of through electrodes each having the second end face larger than the first end face;
A semiconductor wafer having: The semiconductor wafer according to claim 8,
Each of the through electrodes is located between a first end protruding from the first surface, a second end protruding from the second surface, and the first and second ends. And an intermediate part,
A semiconductor wafer wherein the second end is formed to have a larger width or diameter than the first end. The semiconductor wafer according to claim 9,
A semiconductor wafer wherein the second end is formed to have a larger width or diameter than the intermediate part. The semiconductor wafer according to claim 9 or claim 10,
A first insulating layer formed on the first surface;
A second insulating layer formed on the second surface;
A semiconductor wafer further comprising: The semiconductor wafer according to claim 11,
A semiconductor wafer wherein a peripheral edge of the second end is formed on the second insulating layer. 13. The semiconductor wafer according to claim 11, further comprising a pad on the first insulating layer, the pad being electrically connected to at least one of the one integrated circuit and the one through electrode. . The semiconductor wafer according to claim 13,
A semiconductor wafer in which any one of the through electrodes penetrates the pad. It has a plurality of semiconductor chips according to any one of claims 1 to 7, which are stacked,
A semiconductor device in which upper and lower semiconductor chips of the plurality of semiconductor chips are electrically connected by the through electrodes. A circuit board on which the semiconductor chip according to claim 1 is mounted. A circuit board on which the semiconductor device according to claim 15 is mounted. An electronic device comprising the semiconductor chip according to claim 1. An electronic apparatus comprising the semiconductor device according to claim 15. A semiconductor substrate having first and second surfaces and having at least a part of an integrated circuit formed at a position closer to the first surface than the second surface; It has a first end face penetrating and exposed to the first face and a second end face exposed to the second face, and the second end face is formed larger than the first end face. A method for manufacturing a semiconductor device, comprising forming a through electrode formed as described above.

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