JP2004215048A - Solid-state imaging device - Google Patents

Abstract

An object of the present invention is to reduce the size of a photoelectric conversion cell without reducing the area of a photoelectric conversion unit.
A first charge signal and a second charge signal accumulated in a first pair of photoelectric conversion units (PD unit 1B and PD unit 1C) located in adjacent rows are shared by a common amplification transistor 11B. The signal is amplified and output to the common signal output line 39 as a first amplified charge signal and a second amplified charge signal. On the other hand, the third charge signal and the fourth charge signal accumulated in the second pair of photoelectric conversion units located in adjacent rows are amplified by the common amplification transistor, and the third charge signal and the fourth charge signal are amplified. 4 is output to the common signal output line 38 as an amplified charge signal. The first amplified charge signal and the third amplified charge signal are output from the first output line at different timings, and the second amplified charge signal and the fourth amplified charge signal are output at different timings from the second output line. Output from
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device in which a plurality of photoelectric conversion cells each having a photoelectric conversion unit arranged in a plurality of rows are arranged in a row direction, and more particularly, to an improvement in an area of the photoelectric conversion unit in the photoelectric conversion cell and a photoelectric conversion. The present invention relates to a solid-state imaging device that can reduce the size of a cell.
[0002]
[Prior art]
2. Description of the Related Art As a solid-state imaging device, there is known a solid-state imaging device having a common amplifier that amplifies a charge signal accumulated in photoelectric conversion units arranged over a plurality of rows (see Patent Document 1).
[0003]
Hereinafter, a solid-state imaging device having the above-described common amplifier will be described with reference to FIG.
[0004]
In FIG. 10, reference numerals 201a, 201b, 201c, and 201d denote photoelectric conversion units each including a photodiode for performing photoelectric conversion of each pixel, reference numeral 206 denotes an amplifying transistor serving as a common amplifier, and reference numerals 202a, 202b, 202c, and 202d denote photoelectric conversion units. Transfer transistors for transferring the charge signals accumulated in the conversion units 201a to 201d to the input unit of the amplifying transistor 206. Transfer signals 203a, 203b, 203c, and 203d output transfer signals to the transfer transistors 202a to 202d. Reference numeral 204 denotes a reset transistor for resetting an input portion of the amplification transistor 206. Reference numeral 205 denotes a gate bias of the reset transistor 204, and reference numeral 207 denotes a selection transistor for selecting the amplification transistor 206. The amplification transistor 206 and the selection transistor 207 constitute a source follower circuit. Reference numeral 208 denotes an output line, and 209 denotes a power supply.
[0005]
As described above, in the photoelectric conversion cell having the amplification transistor 206 serving as a common amplifier, the charge signals output from the four photoelectric conversion units 201a to 201d constituting one photoelectric conversion cell are amplified by the amplification transistor 206. Is done. Each pixel includes one photoelectric conversion unit 201a, 201b, 201c, or 201d and one transfer transistor 202a, 202b, 202c, or 202d, and includes an amplifying transistor 206, a reset transistor 204, and a selecting transistor 207. Includes part of the circuit. When reading a color signal, a G filter is arranged in the photoelectric conversion units 201a and 201d, a B filter is arranged in the photoelectric conversion unit 201c, and an R filter is arranged in the photoelectric conversion unit 201b.
[0006]
In the above-described solid-state imaging device, when a transfer signal is applied to the transfer transistor 202a from the transfer signal line 203a, the charge signal accumulated in the photoelectric conversion unit 201a is transferred to the gate of the amplification transistor 206, The signal is output to the output line 208 via a source follower circuit configured by the amplification transistor 206 and the selection transistor 207. In this case, by shifting the application timing of the transfer signal applied to the transfer signal lines 203a to 203d, the signals from the photoelectric conversion units 201a to 201d are output to the output line 208 to be mixed at the timing of applying the transfer signal. Is done.
[0007]
[Patent Document 1]
JP 2001-292453 A
[0008]
[Problems to be solved by the invention]
By the way, miniaturization of the size of the photoelectric conversion cell is required, but even in this case, it is preferable that the area of the photoelectric conversion units 201a to 201d is not reduced.
[0009]
However, in the conventional solid-state imaging device, transfer signal lines 203a, 203b, 203c, and 203d are required for each of the photoelectric conversion units 201a to 201d. That is, when the photoelectric conversion cell has four photoelectric conversion units 201a to 201d, four transfer signal lines 203a to 203d are required. For this reason, since the area of the transfer signal lines 203a to 203d cannot be reduced, there is a problem that the area of the photoelectric conversion units 201a to 201d must be reduced when miniaturizing the size of the photoelectric conversion cells. . However, it is preferable that the area of the photoelectric conversion units 201a to 201d is not reduced as described above.
[0010]
In view of the above, it is an object of the present invention to enable the miniaturization of the size of the photoelectric conversion cell without reducing the area of the photoelectric conversion unit.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a first solid-state imaging device according to the present invention includes at least two photoelectric conversion cells each having a photoelectric conversion unit arranged over two or more rows, and at least two photoelectric conversion cells. The first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the cell are amplified at different timings to obtain the first amplified charge. A first common amplifier that outputs a signal and a second amplified charge signal, and a second pair of photoelectric conversion units located in adjacent rows among photoelectric conversion units that constitute at least two photoelectric conversion cells. A second common amplifier that amplifies the third charge signal and the fourth charge signal at different timings and outputs the amplified signal as a third amplified charge signal and a fourth amplified charge signal; and a first amplified charge signal and a third amplified charge signal. Amplification power And it includes a first output line for outputting a signal at different timings, and a second output line for outputting at different timings the second amplifying charge signal and the fourth amplified signal.
[0012]
According to the first solid-state imaging device of the present invention, the first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units are amplified by the first common amplifier, and the first charge signal and the second charge signal are amplified by the first common amplifier. The third charge signal and the fourth charge signal that are output as the amplified charge signal and the second amplified charge signal and stored in the second pair of photoelectric conversion units are amplified by the second common amplifier. Thus, they are output as a third amplified charge signal and a fourth amplified charge signal. Thereafter, the first amplified charge signal and the third amplified charge signal are output at different timings from the first output line, and the second amplified charge signal and the fourth amplified charge signal are output from the second output line. Output at different timing.
[0013]
For this reason, a transfer signal line for transferring one charge signal output via the first common amplifier and a transfer signal for transferring one charge signal output via the second common amplifier Lines can be shared. That is, for example, a transfer signal line for transferring the second signal charge and a transfer signal line for transferring the third signal charge can be shared.
[0014]
Therefore, the area occupied by the transfer signal line in the photoelectric conversion cell can be reduced, so that the size of the photoelectric conversion cell can be reduced without reducing the area of the photoelectric conversion unit.
[0015]
The second solid-state imaging device according to the present invention includes at least three photoelectric conversion cells each having a photoelectric conversion unit arranged over two or more rows, and a photoelectric conversion unit forming at least three photoelectric conversion cells. The first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units located in adjacent rows are amplified at different timings, and the first amplified charge signal and the second amplified charge signal are amplified. And a third charge signal and a fourth charge signal stored in a second pair of photoelectric conversion units located in adjacent rows among photoelectric conversion units constituting at least three photoelectric conversion cells. And a second common amplifier that amplifies the charge signal at different timings and outputs the amplified signal as a third amplified charge signal and a fourth amplified charge signal, and a photoelectric conversion unit that is adjacent to at least three photoelectric conversion cells. The fifth charge signal and the sixth charge signal accumulated in the third pair of photoelectric conversion units located in the row are amplified at different timings and output as the fifth amplified charge signal and the sixth amplified charge signal. A third common amplifier, a first output line that outputs the first amplified charge signal and the third amplified charge signal at different timings, and a second output signal that outputs the second amplified charge signal and the fifth amplified signal at different timings And a third output line for outputting the fourth amplified charge signal and the sixth amplified signal at different timings.
[0016]
According to the second solid-state imaging device of the present invention, the first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units are amplified by the first common amplifier, and the first charge signal and the second charge signal are amplified by the first common amplifier. The third charge signal and the fourth charge signal that are output as the amplified charge signal and the second amplified charge signal and stored in the second pair of photoelectric conversion units are amplified by the second common amplifier, The fifth and sixth charge signals output as the third and fourth amplified charge signals and stored in the third pair of photoelectric conversion units are amplified by the third common amplifier. Then, they are output as a fifth amplified charge signal and a sixth amplified charge signal. Thereafter, the first amplified charge signal and the third amplified charge signal are output at different timings from the first output line, and the second amplified charge signal and the fifth amplified signal are output at different timings from the second output line. The fourth amplified charge signal and the sixth amplified signal are output at different timings from the third output line.
[0017]
For this reason, a transfer signal line for transferring one charge signal output via the first common amplifier and a transfer signal line for transferring one charge signal output via the second common amplifier And a transfer signal line for transferring one charge signal output via the second common amplifier and one transfer signal output via the third common amplifier. Transfer signal lines can be shared.
[0018]
Therefore, the area occupied by the transfer signal line in the photoelectric conversion cell can be reduced, so that the size of the photoelectric conversion cell can be reduced without reducing the area of the photoelectric conversion unit.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, as shown in FIG. 9A, four solid-state imaging devices having four color filters of R, G, B, and G are repeatedly arranged in units of four pixels. It is intended for a solid-state imaging device having a structure.
[0020]
FIG. 1 shows a circuit configuration of a photoelectric conversion cell constituting a solid-state imaging device according to a first embodiment of the present invention. In FIG. 1, 1A, 1B, 1C, 1D, 2A, 2B, 2C, 2D Denotes a photoelectric conversion unit (hereinafter, referred to as a PD unit) composed of a photodiode that performs photoelectric conversion, and 9A, 9B, and 9C denote floating diffusions that store charges obtained in the PD units 1A to 1D and 2A to 2D. 3A, 3B, 3C, 3D, 4A, 4B, 4C, and 4D are transfer transistors that transfer charges from the PD units 1A to 1D and 2A to 2D to the FD units 9A and 9B. , 10A and 10B are reset transistors for sweeping out the charges stored in the FD sections 9A and 9B, and 11A and 11B detect the charges stored in the FD sections 9A and 9B. An amplification transistor as elementary amplifiers, 15 and 16 is a load transistor amplifying transistor 11A, with 11B constitute a source follower amplifier.
[0021]
In FIG. 1, reference numeral 31 denotes a power supply line (hereinafter, referred to as VDDCEL) dedicated to the photoelectric conversion cell, and reference numerals 32, 33, 34, and 35 apply a pulse voltage to the transfer transistors 3A to 3D and 4A to 4D. Read pulse lines (hereinafter referred to as READ), 36 and 37 are reset pulse lines for sweeping out the charges in the FD sections 9A and 9B, and 38 and 39 are common signals for transferring the voltages detected in the FD sections 9A and 9B. An output line (hereinafter, referred to as a VO line), 40 is a load gate line (hereinafter, referred to as LGCEL) for applying a signal to the gates of the load transistors 15 and 16, and 41 is a load gate line of the load transistors 15 and 16. This is a source power supply line (hereinafter, referred to as SCEL).
[0022]
FIG. 2 shows a circuit that converts signals output from two common signal output lines 38 and 39 to four signal output lines 67, 68, 69 and 70 corresponding to a row direction or a column direction and outputs the converted signals. Is shown.
[0023]
As shown in FIG. 2, transistors 50 and 52 are controlled by an applied signal on a gate signal line 62, transistors 51 and 53 are controlled by an applied signal on a gate signal line 63, and transistors 54, 56, 58 and 60 are controlled by a gate signal. The transistors 55, 57, 59, 61 are controlled by the applied signal on line 64, and the transistors 55, 57, 59, 61 are controlled by the applied signal on the gate signal line 65. Note that the common signal output line 38 corresponds to the VO line 38 in FIG. 1, and the common signal output line 39 corresponds to the VO line 39 in FIG.
[0024]
FIGS. 3 and 4 show the drive timing of the photoelectric conversion cell shown in FIG. 1, and this drive timing completes a series of operations during the horizontal blanking period. The detection of the charge signal is performed on the PD units on the first and second rows and then on the PD units on the third and fourth rows.
[0025]
Hereinafter, the drive timing will be described with reference to FIGS.
[0026]
First, a predetermined voltage is applied to the LGCEL 40 to set the load transistors 15 and 16 to a constant current. Then, the VDDCEL 31 is set to the HIGH voltage. Sweep out. At this time, the signal level at the time of reset is detected by the amplification transistors 11A and 11B, and an initial voltage is set via the VDDCEL 31.
[0027]
Next, after the reset transistors 10A and 10B are turned off, a HIGH voltage is applied to the READ 32 and the transfer transistors 3A and 3B are turned on, so that the charges accumulated in the PD unit 1A are transferred to the FD unit 9A. At the same time, the charge stored in the PD section 1B is transferred to the FD section 9B. At this time, if the PD section to be subjected to the charge transfer is located in a different row, the transfer transistors that are turned on when a HIGH voltage is applied to READ 32 are replaced with transfer transistors 3A and 3B instead of transfer transistors 3A and 3B. 4B may be used. In this case, the charges accumulated in the PD unit 1A and the PD unit 2B are transferred.
[0028]
Next, the charge transferred to the FD unit 9A is detected by the amplifying transistor 11A to detect the accumulation signal level and output to the VO line 38, and the charge transferred to the FD unit 9B is detected by the amplification transistor 11B to detect the accumulation signal level. And outputs it to the VO line 39. In this case, the difference between the output to the VO line 38 or VO line 39 and the output at the time of the initial charge transfer is used as the output signal. By doing so, it is possible to detect an output signal from which the threshold variation and the noise component in the amplification transistors 11A and 11B have been removed.
[0029]
Next, when the VDDCEL 31 is turned off and the RESETs 36 and 37 are turned on, the FD section 9A and the FD section 9B have the same off level as the VDDCEL 31, so that the amplification transistors 11A and 11B do not operate.
[0030]
After that, the amplification transistors 11A and 11B do not operate until the RESETs 36 and 37 and the READs 32 and 33 are selected in the vertical line scanning circuit. During the next horizontal blanking period, the reset transistors 10A and 10B are turned on again to sweep out the charges in the FD sections 9A and 9B. At this time, the signal level at the time of reset is detected by the amplification transistors 11A and 11B, and the initial voltage is set via the VDDCEL31.
[0031]
Next, after the reset transistors 10A and 10B are turned off, a HIGH voltage is applied to the READ 33, and the transfer transistors 4A and 4B are turned on, so that the charges accumulated in the PD unit 2A are transferred to the FD unit 9A. At the same time, the charge stored in the PD section 2B is transferred to the FD section 9B. Note that, as described above, instead of applying the HIGH voltage to the READ 32 and turning on the transfer transistors 3A and 3B, instead of applying the HIGH voltage to the READ 32 and turning on the transfer transistors 3A and 4B, here, , And transfers the charge stored in the PD unit 1B to the FD unit 9A and transfers the charge stored in the PD unit 2A to the FD unit 9B.
[0032]
Next, the charge transferred to the FD section 9A and the FD section 9B is detected by the amplifying transistor 11A and the amplifying transistor 11B, respectively, and is output to the VO line 38 and the VO line 39.
[0033]
FIG. 4 is a timing chart for switching output signals from the amplification transistors 11A and 11B to a plurality of signal lines or switching output signals.
[0034]
READ32 to READ35 in FIG. 4 correspond to READ32 to READ35 in FIG. Incidentally, READ42 to READ45 in FIG. 4 are omitted in FIG. Further, PULSEs 62 and 63 perform switching of column direction pixels, and PULSEs 64 and 65 perform replacement of row direction pixels.
[0035]
In the period T1, the charge signal of the PD section 1A output from the VO line 38 is guided to the output line 67 via the transistors 50 and 54, and the charge signal of the PD section 1B output from the VO line 39 is output from the transistor 52, It is led to an output line 68 via 56. In the period T2, the charge signal of the PD unit 2A output from the VO line 38 is guided to the output line 69 via the transistors 51 and 58, and the charge signal of the PD unit 2B output from the VO line 39 is output from the transistor VO. It is led to the output line 70 via 53 and 60. In the period T3, the charge signal of the PD unit 1C output from the VO line 39 is guided to the output line 67 via the transistors 52 and 57, and the charge signal of the PD unit 1D output from the VO line 38 is output from the transistor It is led to an output line 68 via 50 and 55. In the period T4, the charge signal of the PD unit 2C output from the VO line 39 is guided to the output line 69 via the transistors 53 and 61, and the charge signal of the PD unit 2D output from the VO line 38 is It is guided to an output line 70 via 51 and 60.
[0036]
When two pixels (two PD units) in the row direction and two pixels (two PD units) in the column direction among the PD units 1A to 1D and 2A to 2D shown in FIG. The output signals of the PD units 1A and 1C, the output signals of the PD units 1B and 1D, the output signals of the PD units 2A and 2C, and the outputs of the PD units 2C and 2D which have the same positional relationship in the group. The signals are output from the same output lines 67, 68, 69, 70, respectively.
[0037]
(Modification of First Embodiment)
Hereinafter, a modified example of the solid-state imaging device according to the modified example of the first embodiment of the present invention will be described with reference to FIG.
[0038]
FIG. 5 shows a circuit for converting output signals output from the two common signal output lines 38 and 39 into four output lines 79, 80, 81 and 82 corresponding to the row direction or the column direction. In FIG. 5, transistors 71 and 73 are controlled by an applied signal on a gate signal line 83, transistors 72 and 74 are controlled by an applied signal on a gate signal line 84, and transistors 75 and 77 are controlled by an applied signal on a gate signal line 85. The transistors 76 and 78 are controlled by a signal applied to the gate signal line 86. Note that the common signal output line 38 corresponds to the VO line 38 in FIG. 1, and the common signal output line 39 corresponds to the VO line 39 in FIG.
[0039]
By applying the PULSE 64 shown in FIG. 4 to the gate signal line 83 by the same operation as the conversion circuit shown in FIG. 2, the charge signals of the PD units 1A and 1C are guided to the output line 79, and the PULSE 65 is connected to the gate signal line. The charge signals of the PD unit 1B and the PD unit 1D are guided to the output line 80 by applying to the output line 84, and the charge signals of the PD units 2A and 2C are applied to the output line 81 by applying the PULSE 66 to the gate signal line 85. By applying the PULSE 67 to the gate signal line 86, the charge signals of the PD unit 2B and the PD unit 2D are guided to the output line 82.
[0040]
When two pixels (two PD units) in the row direction and two pixels (two PD units) in the column direction among the PD units 1A to 1D and 2A to 2D shown in FIG. The output signals of the PD units 1A and 1C, the output signals of the PD units 1B and 1D, the output signals of the PD units 2A and 2C, and the outputs of the PD units 2B and 2D which have the same positional relationship in the group. The signals are output from the same output lines 79, 80, 81, 82, respectively.
[0041]
(Second embodiment)
Hereinafter, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, as shown in FIG. 9B, four solid-state imaging devices having four color filters of G, Ye, Mg, and Cy are repeatedly arranged in units of eight pixels. It is intended for a solid-state imaging device having a structure.
[0042]
FIG. 6 shows a circuit configuration of a photoelectric conversion cell constituting a solid-state imaging device according to a second embodiment of the present invention. In FIG. 6, 1A, 1B, 1C, 1D, 1E, 1F2A, 2B, 2C Reference numerals 2D, 2E, and 2F denote photoelectric conversion units (hereinafter, referred to as PD units) including photodiodes that perform photoelectric conversion. 9A, 9B, 9C, and 9D are obtained in PD units 1A to 1E and 2A to 2E. 3A, 3B, 3C, 3D, 3E, 4A, 4B, 4C, 4D, and 4E transfer charges from the PD units 1A to 1E and 2A to 2E. Transfer transistors for transferring to the FD units 9A, 9B, and 9C, and reset transistors 10A, 10B, and 10C for discharging electric charges accumulated in the FD units 9A, 9B, and 9C. Reference numerals A, 11B, and 11C denote amplification transistors as pixel amplifiers for detecting charges accumulated in the FD sections 9A, 9B, and 9C. It is a transistor.
[0043]
In FIG. 6, reference numeral 31 denotes a power supply line (hereinafter, referred to as VDDCEL) dedicated to the photoelectric conversion cell, and reference numerals 32, 33, 34, 35, 42, and 43 apply pulses to the transfer transistors 3A to 3E and 4A to 4E. Read pulse lines (hereinafter referred to as READ) for applying a voltage, reset pulse lines 36 and 37 for sweeping out the charges of the FD sections 9A and 9B, and 38 and 39 for reading the voltages detected by the FD sections 9A and 9B. A common signal output line (hereinafter, referred to as a VO line) to be transferred, 40 is a load gate line (hereinafter, referred to as LGCEL) for applying a signal to the gates of the load transistors 15 and 16, and 41 is a load transistor. 15 and 16 are source power lines (hereinafter, referred to as SCEL).
[0044]
FIG. 7 shows a circuit that converts signals output from the two common signal output lines 38 and 39 to four signal output lines 131, 132, 133 and 134 corresponding to the row direction or the column direction and outputs the converted signals. Is shown.
[0045]
As shown in FIG. 7, transistors 101 and 104 are controlled by an applied signal of a gate signal line 121, transistors 102 and 105 are controlled by an applied signal of a gate signal line 123, and transistors 103 and 106 are applied by an applied signal of a gate signal line 122. The transistors 107, 109, 111, and 113 are controlled by signals applied to the gate signal line 124, and the transistors 108, 110, 112, and 114 are controlled by signals applied to the gate signal line 124. The common signal output line 38 corresponds to the VO line 38 in FIG. 6, and the common signal output line 39 corresponds to the VO line 39 in FIG.
[0046]
FIG. 8 is a timing chart for switching output signals from the amplifying transistors 11A, 11B, and 11C to a plurality of signal lines or switching output signals.
[0047]
READs 32 to 35 and READs 42 and 43 in FIG. 8 correspond to READs 32 to 35 and READs 42 and 43 in FIG. Note that READ44 and D45 in FIG. 7 are omitted in FIG. PULSEs 121, 122, and 123 perform switching of column direction pixels, and PULSEs 124 and 125 perform replacement of row direction pixels.
[0048]
In the period T1, the charge signal of the PD unit 1A output from the VO line 38 is guided to the output line 131 via the transistors 101 and 107, and the charge signal of the PD unit 1B output from the VO line 39 is output from the transistor 104. It is led to the output line 132 via 109. In the period T2, the charge signal of the PD unit 2A output from the VO line 38 is guided to the output line 133 via the transistors 103 and 111, and the charge signal of the PD unit 2B output from the VO line 39 is It is guided to an output line 134 via 106 and 113. In the period T3, the charge signal of the PD unit 1C output from the VO line 39 is guided to the output line 133 via the transistors 105 and 111, and the charge signal of the PD unit 1D output from the VO line 38 is It is led to the output line 132 via 102 and 109. In the period T4, the charge signal of the PD unit 2C output from the VO line 39 is guided to the output line 133 via the transistors 106 and 114, and the charge signal of the PD unit 2D output from the VO line 38 is It is led to an output line 134 via 103 and 112.
[0049]
【The invention's effect】
According to the first solid-state imaging device of the present invention, one transfer signal line for transferring the charge signal output via the first common amplifier and the charge output via the second common amplifier Since one transfer signal line for transferring a signal can be shared, the size of the photoelectric conversion cell can be reduced without reducing the area of the photoelectric conversion unit.
[0050]
Further, according to the second solid-state imaging device of the present invention, one transfer signal line for transferring the charge signal output via the first common amplifier and the output signal via the second common amplifier are provided. One transfer signal line for transferring a charge signal, and one transfer signal line for transferring a charge signal output via a second common amplifier, and a third common amplifier. Can be shared with one transfer signal line for transferring the charge signal output through the photoelectric conversion unit, so that the size of the photoelectric conversion cell can be reduced without reducing the area of the photoelectric conversion unit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a photoelectric conversion cell of a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an output conversion circuit in the solid-state imaging device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing drive timings of photoelectric conversion cells of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating drive timings of photoelectric conversion cells of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating a modified example of the output conversion circuit in the solid-state imaging device according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram of a photoelectric conversion cell of a solid-state imaging device according to a second embodiment of the present invention.
FIG. 7 is a diagram illustrating an output conversion circuit in a solid-state imaging device according to a second embodiment of the present invention.
FIG. 8 is a diagram illustrating drive timings of photoelectric conversion cells of a solid-state imaging device according to a second embodiment of the present invention.
9A is a diagram illustrating an arrangement of color filters of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 9B is a diagram illustrating an arrangement of the solid-state imaging device according to the second embodiment of the present invention; FIG. 3 is a diagram illustrating an arrangement of color filters.
FIG. 10 is a circuit diagram of a photoelectric conversion cell of a conventional solid-state imaging device.
[Explanation of symbols]
1A, 1B, 1C, 1D, 1E, 1F Photoelectric conversion unit
2A, 2B, 2C, 2D, 2E, 2F Photoelectric conversion unit
3A, 3B, 3C, 3D, 3E transfer transistor
4A, 4B, 4C, 4D, 4E transfer transistor
9A, 9B, 9C, 9D Floating diffusion
10A, 10B, 10C reset transistor
11A, 11B, 11C amplifying transistor
15 Load transistor
16 Load transistor
31 Power line
32, 33, 34, 35, 42, 43 Readout pulse line
36, 37 Reset pulse line
38, 39 Common signal output line
40 Load gate line
41 Source power line
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61 transistors
62, 63, 64, 65 gate signal lines
67, 68, 69, 70 signal output line
71, 72, 73, 74, 75, 76, 77, 78 transistors
83, 84, 85, 86 Gate signal line
79, 80, 81, 82 signal output line
101, 102, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 transistors
121, 122, 123, 124, 125 Gate signal line
131, 132, 133, 134 signal output line

Claims (2)

At least two photoelectric conversion cells each having a photoelectric conversion unit arranged over two or more rows,
Amplifying the first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the at least two photoelectric conversion cells at different timings. A first common amplifier for outputting a first amplified charge signal and a second amplified charge signal,
Amplifying the third charge signal and the fourth charge signal accumulated in the second pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the at least two photoelectric conversion cells at different timings. A second common amplifier for outputting as a third amplified charge signal and a fourth amplified charge signal,
A first output line that outputs the first amplified charge signal and the third amplified charge signal at different timings;
A solid-state imaging device comprising: a second output line that outputs the second amplified charge signal and the fourth amplified signal at different timings. At least three photoelectric conversion cells each having a photoelectric conversion unit arranged over two or more rows,
Amplifying the first charge signal and the second charge signal accumulated in the first pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the at least three photoelectric conversion cells at different timings. A first common amplifier for outputting a first amplified charge signal and a second amplified charge signal,
The third charge signal and the fourth charge signal accumulated in the second pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the at least three photoelectric conversion cells are amplified at different timings. A second common amplifier for outputting as a third amplified charge signal and a fourth amplified charge signal,
The fifth charge signal and the sixth charge signal accumulated in the third pair of photoelectric conversion units located in adjacent rows among the photoelectric conversion units constituting the at least three photoelectric conversion cells are amplified at different timings. A third common amplifier for outputting as a fifth amplified charge signal and a sixth amplified charge signal,
A first output line that outputs the first amplified charge signal and the third amplified charge signal at different timings;
A second output line that outputs the second amplified charge signal and the fifth amplified signal at different timings;
And a third output line that outputs the fourth amplified charge signal and the sixth amplified signal at different timings.

Images