JP2004212940A - Array substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

A method for forming a gate wiring and a data wiring with copper having a low resistance value and a chemically strong corrosion resistance is provided.
The present invention relates to a method of manufacturing an array substrate for a liquid crystal display device, and uses a metal material that is chemically highly resistant to corrosion and has a small resistance value when forming gate wiring and data wiring on the array substrate. It relates to a method for simplifying the process. The present invention improves the adhesion characteristics between copper and the glass substrate by using copper as the metal material as described above. Furthermore, in order to prevent copper from reacting with the silicon component, a copper compound layer is further formed below the copper layer. Such a configuration makes it possible to use copper as the wiring, and has an advantage that the process can be simplified unlike the conventional case, particularly when the gate wiring is formed of copper.
[Selection] Figure 4E

Description

  The present invention relates to a liquid crystal display device, and more particularly to an array substrate for a liquid crystal display device in which a gate wiring and a data wiring are formed of a metal material having a small resistance value, and a manufacturing method thereof.

  In general, a liquid crystal display device expresses an image using the optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of the liquid crystal changes, and the changed liquid crystal Depending on the arrangement direction of the light, the property of transmitting light also changes.

  Generally, in a liquid crystal display device, both substrates on which electric field generating electrodes are formed are arranged so that the surfaces on which both electrodes are formed face each other, and after injecting a liquid crystal substance between the two substrates, both electrodes A voltage is applied to generate an electric field, and liquid crystal molecules are moved by this electric field to change the light transmittance, thereby expressing an image.

  FIG. 1 is a diagram schematically showing a configuration of a general liquid crystal display device. As shown in the drawing, a general color liquid crystal display device 11 includes an upper substrate 5 and a lower substrate 22. The upper substrate 5 is formed of a color filter 7 including a black matrix 6 formed between the sub color filters 8 and a common electrode 18 deposited on the color filter 7. On the other hand, the lower substrate 22 is formed of a pixel region P in which the pixel electrode 17 and the switching element Tr are configured, and an array wiring around the pixel region P. Further, a liquid crystal 14 is filled between the upper substrate 5 and the lower substrate 22.

  The lower substrate 22 is also called an array substrate, and thin film transistors serving as switching elements Tr are arranged in a matrix form. A gate wiring 13 and a data wiring 15 are formed so as to cross the plurality of thin film transistors arranged in this way.

  At this time, the pixel region P is a region defined by the intersecting gate wiring 13 and data wiring 15, and the transparent pixel electrode 17 is formed on the pixel region P as described above. The pixel electrode 17 is made of a transparent conductive metal having a relatively excellent light transmittance, such as indium-tin-oxide (ITO).

  A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate line 13. A part of the gate wiring 13 is used for the first electrode of the storage capacitor C, and an island-like source / drain metal layer 30 formed of the same material as the source electrode and the drain electrode is used for the second electrode. . At this time, the source / drain metal layer 30 is in contact with the pixel electrode 17 and is configured to receive a signal of the pixel electrode.

  FIG. 2 is an enlarged plan view showing one pixel of a general array substrate for a liquid crystal display device. As shown in the figure, a gate wiring 62 extending in one direction on the substrate 50 and a data wiring 76 defining the pixel region P intersecting with the gate wiring 62 are formed. The gate wiring 62 and the data wiring 76 are referred to as signal lines.

  A thin film transistor which is a switching element Tr including a gate electrode 60, an active layer 66, a source electrode 70 and a drain electrode 72 is formed at the intersection of the gate line 62 and the data line 76. A pixel electrode 80 is formed in the pixel region P in contact with the drain electrode 72. Further, the pixel electrode 80 and the metal layer 74 are connected to form a storage capacitor C.

  In the configuration described above, the gate wiring 62 is mainly made of aluminum (Al) or aluminum alloy (AlNd), which is a low resistance metal, in order to prevent signal delay. However, the aluminum metal is chemically weak in corrosion resistance, and in order to protect it, a double metal layer having chromium (Cr) or molybdenum (Mo) as a protective layer is formed.

  However, the aluminum (Al) and chromium (Cr), or aluminum (Al) and molybdenum (Mo) layers do not match even if they are etched with the same solution. The process is accompanied.

  Hereinafter, a description will be given with reference to FIGS. 3A to 3F. 3A to 3F are process cross-sectional views of a typical array substrate for a liquid crystal display device. In the cross-section taken along III-III in FIG. A cross-sectional view is shown. First, as shown in FIG. 3A, a switching region T and a pixel region P are defined on the substrate 50. Then, aluminum (Al) and molybdenum (Mo) are sequentially deposited on the entire surface of the substrate 50 in which such regions T and P are defined, thereby forming the first metal layer 52 and the second metal layer 54.

  Next, a photoresist (photoresistor: hereinafter referred to as “PR”) is applied and patterned on the entire surface of the substrate 50 on which the first metal layer 52 and the second metal layer 54 are stacked, and the one of the switching regions T is formed. A PR pattern 56 is formed on the edge of the pixel area P and the pixel area.

  If the second metal layer 54 exposed between the PR patterns 56 and the first metal layer 52 therebelow are etched with the same etching solution, as shown in FIG. 3B, the lower portions of the two PR patterns 56 are formed. Only the first metal layer 58a and the second metal layer 58b remain.

  However, the etching rate of the first metal layer (aluminum layer) 58a is faster than that of the second metal layer (molybdenum layer) 58b. As a result, the first metal layer (aluminum layer) 58a is over-etched under the second metal layer (molybdenum layer) 58b as shown in the drawing, and both metal layers form an overhang structure.

  If the overhang structure is used as it is, the insulation characteristics are deteriorated due to disconnection or vapor deposition failure of the structure formed in the subsequent process, and there is a possibility that the etching solution flows and induces corrosion of the metal layer.

  Therefore, it is necessary to arrange the side surfaces of the first metal layer 58a and the second metal layer 58b forming the overhang structure so as to have a continuous inclined surface. To this end, as shown in FIG. 3C, a side surface of the second metal layer 58b and the second metal layer 58b are removed by cutting the periphery of the PR pattern 56 and the second metal layer 58b below the dry pattern. A structure in which the side surface of one metal layer 58a has a continuous inclined surface, that is, a structure in which an overhang is eliminated can be obtained.

  Next, a process of removing the remaining PR pattern 56 on the first metal layer 58a and the second metal layer 58b is performed. As a result, as shown in FIG. 3D, a gate electrode 60 made of aluminum (Al) / molybdenum (Mo) is formed in the switching region T, and is connected to the gate electrode 60 to form a part of the pixel region P. A gate wiring 62 extending to the side is formed.

Subsequently, an inorganic insulating material group represented by silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is selected on the entire surface of the substrate 50 on which the gate electrode 60 and the gate wiring 62 are formed. One is deposited to form the gate insulating film 64.

  Next, as shown in FIG. 3E, an amorphous silicon layer (n-Si: H) and an amorphous silicon layer (n) containing impurities are formed on the entire surface of the substrate 50 on which the gate insulating film 64 is formed. + a-Si: H) are stacked and patterned to form an active layer 66 and an ohmic contact layer 68 on the gate insulating film 64 above the gate electrode 60.

  Next, aluminum (Al) or an aluminum alloy and a conductive metal such as tungsten (W), molybdenum (Mo), or chromium (Cr) are deposited on the entire surface of the substrate 50 on which the ohmic contact layer 68 is formed. Pattern. As a result, a source electrode 70 and a drain electrode 72 that are in contact with the ohmic contact layer 68 and spaced apart by a predetermined distance are formed, and a data wiring 76 that extends from the source electrode 70 and perpendicularly intersects the gate wiring 62 is formed. It is formed. At the same time, an island-shaped metal layer 74 is formed on the gate wiring 62.

  Next, as shown in FIG. 3F, benzocyclobutene (BCB) or acrylic resin (resin) is formed on the entire surface of the substrate 50 on which the source electrode 70, the drain electrode 72, and the data wiring 76 are formed. A protective film 78 is formed by applying one selected from the group of organic insulating materials represented by the above.

  Subsequently, a patterning process is performed on the protective layer 78 to expose a part of the drain electrode 72 and a part of the island-shaped metal layer 74.

  Next, a transparent conductive metal group represented by indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is selected on the entire surface of the substrate 50 on which the protective film 78 is formed. The pixel electrode 80 is formed by depositing and patterning one of them. The pixel electrode 80 is in contact with the drain electrode 72 and the island-shaped metal layer 74 and is disposed in the pixel region P.

  By passing through the processes as described above, an array substrate for a liquid crystal display device can be manufactured. However, the above-described process requires two etching steps to pattern the gate electrode and the gate wiring, and thus the process becomes long, which is disadvantageous in terms of cost and causes a decrease in yield. .

  In addition, since aluminum is included as an electrode material, the problem of resistance increases as the liquid crystal display device has a larger area and higher resolution, resulting in a problem that image quality deteriorates due to signal delay caused by this.

  The present invention has been proposed to solve the above-described problems, and proposes a method of forming the gate wiring and the data wiring with copper (Cu) having a low resistance value and a chemically strong corrosion resistance. To do.

  Copper (Cu) does not have good interface characteristics with a glass substrate, and is liable to cause a chemical reaction with a silicon (Si) component, resulting in an increase in resistance. Therefore, in order to solve this problem, a copper compound is formed under the copper layer. Since the copper and the copper compound can be collectively etched, the process is not complicated.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention includes a substrate, a thin film transistor having a signal line composed of a double layer of a copper compound and copper, and a pixel electrode connected to the thin film transistor. Is included. Here, the copper compound may include nitrogen, and the copper compound may be formed by a reaction between copper and a reaction gas such as NH ₃ or N ₂ . According to another aspect of the present invention, a step of forming a copper compound layer on a substrate, a step of forming a copper layer on the copper compound layer, and etching the copper compound layer and the copper layer to form a signal line There is provided a method of manufacturing an array substrate for a liquid crystal display device, comprising: forming, forming a thin film transistor including the signal line, and forming a pixel electrode connected to the thin film transistor.

  The array substrate for a liquid crystal display device according to the present invention has a configuration in which copper (Cu) having a low resistance is used to form gate wiring and data wiring, and a copper compound layer is further formed below the copper wiring. A large-area liquid crystal display device having a high resolution can be manufactured, and unlike the conventional method, the process is simplified and the yield is improved.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  The present invention is characterized in that the gate wiring and the data wiring are formed of copper, and at this time, a copper compound layer is further formed below the copper wiring.

  Hereinafter, a manufacturing process of the array substrate for a liquid crystal display according to the present invention will be described with reference to FIGS. 4A to 4E. 4A to 4E are process cross-sectional views of the array substrate for a liquid crystal display device according to the present invention. In the cross section taken along the line III-III in FIG. 2, the sequence of the manufacturing process of the array substrate of the present invention is followed. Process sectional drawing is shown. Since the planar configuration is the same as that in FIG.

First, as shown in FIG. 4A, a switching region T and a pixel region P are defined on the substrate 150. Then, copper is deposited on the entire surface of the substrate 150 in which such regions T and P are defined by sputtering. At this time, a reactive gas such as NH ₃ or N _{2 is} allowed to flow in the deposition chamber, thereby allowing the substrate 150 to be exposed. Then, a copper compound (Cu _x N) layer 152 is formed.

  The copper compound layer 152 has the same etching ratio as the copper layer, and has an advantage of reacting in the same manner as copper by an etchant. Subsequently, a copper layer 154 is formed on the copper compound layer 152 in a non-reactive gas atmosphere such as argon (Ar). Further, a photoresist is applied and patterned on the entire surface of the substrate 150 on which the copper layer 154 is formed, and is unidirectionally passed through a part of the switching region T and one side of the pixel region P. PR patterns 156 are formed at two locations in the extended portion.

  Next, as shown in FIG. 4A, the copper layer 154 exposed between the PR patterns 156 and the copper compound layer 152 therebelow are etched together. Thus, as shown in FIG. 4B, patterning is performed so that only the copper compound layer 158a and the copper layer 158b corresponding to the portions covered with the two PR patterns 156 remain, and the side surfaces thereof have continuous inclined surfaces. The gate electrode 160 and the gate wiring 162 thus formed are formed. Thereafter, the PR pattern 156 is removed.

  As a result, a patterned copper compound layer 158a exists below the gate electrode 160 and the gate wiring 162. These copper compound layers 158 a play a role of preventing defects in which the gate electrode 160 and the gate wiring 162 formed of the copper layer 158 b are lifted from the substrate 150.

As shown in FIG. 4C, an inorganic insulating material group represented by silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 150 on which the gate electrode 160 and the gate wiring 162 are formed. A gate insulating film 164 is formed by depositing one selected from the above.

  Next, an amorphous silicon layer (a-Si: H) and an amorphous silicon layer (n + a-Si: H) containing impurities are formed on the entire surface of the substrate 150 on which the gate insulating film 164 is formed. An active layer 166 and an ohmic contact layer 168 are formed on the gate insulating film 164 above the gate electrode 160 by stacking and patterning.

  Next, as shown in FIG. 4D, as described above, a copper compound layer and a copper layer are stacked and patterned on the entire surface of the substrate 150 on which the ohmic contact layer 168 is formed. As a result, a source electrode 170 and a drain electrode 172 are formed on the ohmic contact layer 168 so as to be spaced apart from each other, and a data wiring 176 extending from the source electrode 170 is formed. At the same time, an island-shaped metal layer 174 is formed on a part of the upper portion of the gate wiring 162.

  That is, the source electrode 170, the drain electrode 172, the data wiring 176, and the island-shaped metal layer 174 all form a double layer of copper and a copper compound. Here, the lower copper compound layer serves to prevent the copper layer from reacting with the silicon component of the ohmic contact layer 168.

  On the entire surface of the substrate 150 on which the source electrode 170 and the drain electrode 172 are formed, an organic insulating material group represented by benzocyclobutene (BCB) or acrylic resin (resin) is selected. One is applied to form a protective film 178.

  Subsequently, the protective film 178 is patterned to expose part of the drain electrode 172 and part of the island-shaped metal layer 174, thereby forming a drain contact hole 132 and a storage contact hole 134.

  Next, as shown in FIG. 4E, a transparent conductive metal group such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed on the entire surface of the substrate 150 on which the protective film 178 is formed. A selected one of them is deposited and patterned to form a pixel electrode 180. The pixel electrode 80 is in contact with the drain electrode 172 and the island-shaped metal layer 174 and is disposed in the pixel region P.

  The array substrate for a liquid crystal display device according to the present invention can be manufactured through the above-described steps. In the process as described above, a copper compound layer is further formed under the copper wiring (gate wiring, data wiring) to prevent the copper wiring from floating and the copper wiring from reacting with silicon components. it can. Thereby, copper wiring can be used as gate wiring and data wiring.

1 is a diagram schematically illustrating a configuration of a general liquid crystal display device. It is the enlarged plan view which expanded and showed one pixel of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the common array substrate for liquid crystal display devices. It is process sectional drawing of the array substrate for liquid crystal display devices which concerns on this invention. It is process sectional drawing of the array substrate for liquid crystal display devices which concerns on this invention. It is process sectional drawing of the array substrate for liquid crystal display devices which concerns on this invention. It is process sectional drawing of the array substrate for liquid crystal display devices which concerns on this invention. It is process sectional drawing of the array substrate for liquid crystal display devices which concerns on this invention.

Explanation of symbols

  5 Upper substrate, 6 Black matrix, 7 Color filter, 8 Sub color filter, 11 Color liquid crystal display device, 13 Gate wiring, 14 Liquid crystal, 15 Data wiring, 17 Pixel electrode, 18 Common electrode, 22 Lower substrate, 30 Island-shaped Source / drain metal layer, 50 substrate, 52 first metal layer, 54 second metal layer, 56 PR pattern, 58a first metal layer, 58b second metal layer, 60 gate electrode, 62 gate wiring, 64 gate insulating film, 66 active layer, 68 ohmic contact layer, 70 source electrode, 72 drain electrode, 74 metal layer, 76 data wiring, 78 protective film, 80 pixel electrode, 132 drain contact hole, 134 storage contact hole, 150 substrate, 152 copper compound layer 154 Copper layer, 1 6 PR pattern, 158a copper compound layer, 158b copper layer, 160 gate electrode, 162 gate wiring, 164 gate insulating film, 166 active layer, 168 ohmic contact layer, 170 source electrode, 172 drain electrode, 174 island-like metal layer, 176 Data wiring, 178 protective film, 180 pixel electrode.

Claims (9)

A substrate,
A thin film transistor having a signal line composed of a double layer of copper compound and copper;
An array substrate for a liquid crystal display device, comprising: a pixel electrode connected to the thin film transistor.   The array substrate for a liquid crystal display device according to claim 1, wherein the copper compound contains nitrogen.   The array substrate for a liquid crystal display device according to claim 1, wherein the copper compound is formed by a reaction between copper and a reaction gas. The array substrate for a liquid crystal display device according to claim 3, wherein the reaction gas is NH ₃ or N ₂ .   The array substrate for a liquid crystal display device according to claim 1, wherein the signal line is a gate line or a data line. Forming a copper compound layer on the substrate;
Forming a copper layer on the copper compound layer; etching the copper compound layer and the copper layer to form a signal line;
Forming a thin film transistor including the signal line;
Forming a pixel electrode connected to the thin film transistor. A method of manufacturing an array substrate for a liquid crystal display device.   The method of manufacturing an array substrate for a liquid crystal display device according to claim 6, wherein the copper compound is formed in a state where a gas capable of being chemically bonded to copper flows in a reaction chamber. The method of manufacturing an array substrate for a liquid crystal display device according to claim 7, wherein the gas is NH ₃ or N ₂ .   7. The method of manufacturing an array substrate for a liquid crystal display device according to claim 6, wherein the signal line includes a gate line and a data line.

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