JP2004296774A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device having a silicide film having a small contact resistance on an N-type diffusion layer, and a method of manufacturing the same. A semiconductor device is provided on a silicon substrate on which high concentration source / drain regions are formed. After forming the silicide films 116n and 116p, the first interlayer insulating film 145, and the first plugs 150n and 150p, a Ti / TiN / W laminated film 151 is formed. The Ti / TiN / W laminated film 151 is patterned to form the stress relaxing metal pad 152 on the first plug 150n on the N-type diffusion layer. Thereafter, a second interlayer insulating film 147 is deposited on the substrate, and a metal pad 152 for stress relaxation penetrating through the second interlayer insulating film 147 and reaches the first plug 160p on the P-type diffusion layer. The upper second plug 170n and the second plug 170p on the P-type diffusion layer are formed.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a silicide film and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, as the miniaturization of semiconductor devices has progressed, the need for a DRAM mixed technology for forming both a logic element and a DRAM element on a common substrate has been increasing. However, since a high-temperature heat treatment at about 800 ° C. is performed for several hours when forming a DRAM memory cell, a semiconductor device that can withstand such a high-temperature heat treatment is usually used to form a transistor in a logic section prior to a DRAM section. Is required to have thermal stability.
[0003]
On the other hand, a transistor having a silicide film is generally formed in the logic part (not used in the I / O part) in order to improve the performance of the transistor in the logic part. It is a crystal and has a coefficient of thermal expansion significantly different from that of silicon. For this reason, the silicide film is liable to cause agglomeration during the high-temperature heat treatment and to be easily disconnected. Therefore, cobalt is used as the metal film for silicide so that disconnection hardly occurs even if a little. This is because cobalt silicide has almost the same lattice constant as silicon and has good lattice matching with the silicon substrate, so that cobalt silicide easily grows epitaxially on the silicon substrate.
[0004]
As a method for forming a cobalt silicide film (more precisely, a cobalt disilicide film) epitaxially grown on a silicon substrate, a method of sandwiching a Ti or oxide film at a Co / Si interface or a method of sandwiching a Ti and oxide film has been proposed. Non-Patent Document 1 discloses a method of sandwiching Ti, Non-Patent Document 2 reports a method of sandwiching an oxide film, and Non-Patent Document 3 reports a method of sandwiching Ti and an oxide film. ing.
[0005]
However, the cobalt silicide film is slightly epitaxially grown on the silicon substrate without using the technique of actively growing epitaxially as disclosed in these documents.
[0006]
FIGS. 5A to 6C are cross-sectional views showing a manufacturing process of a conventional DRAM embedded semiconductor device including a process of forming a metal plug in a silicide film on a diffusion layer. 5A to 6C, the left half is an NMISFET region Rnt which is a region for forming an N-channel MIS transistor, and the right half is a PMISFET formation region Rpt which is a region for forming a P-channel MIS transistor. Are respectively shown.
[0007]
First, in a step shown in FIG. 5A, a shallow trench 1011 which is an element isolation region surrounding an active region is formed on a silicon substrate 1000 (wafer) having at least an upper portion serving as a semiconductor layer. Then, in the NMISFET formation region Rnt, a gate oxide film 1021, a polysilicon gate electrode 1022 made of an N-type polysilicon film, and an insulating sidewall 1023 made of a nitride film are formed. In the PMISFET formation region Rpt, a gate oxide film 1031, a polysilicon gate electrode 1032 made of a P-type polysilicon film, and an insulating sidewall 1033 made of a nitride film are formed. In the NMISFET formation region Rnt, an N-type low-concentration source / drain diffusion layer 1001a and an N-type high-concentration source / drain diffusion layer 1001b are formed. In the PMISFET formation region Rpt, a P-type low-concentration source / drain diffusion layer is formed. A layer 1002a and a P-type high concentration source / drain diffusion layer 1002b are formed.
[0008]
Next, in the step shown in FIG. 5B, before forming the Co film, sputter etching using argon plasma (pressure 0.4 mTorr, plasma power 400 W, bias power 260 W, substrate bias -120 V, etching time 5 seconds). To remove the natural oxide film by physical sputtering of argon ions. Thereafter, when the sputter etching is completed, the wafer is transferred to a Co sputtering chamber in a vacuum. Sputtering is performed in a Co sputtering chamber to deposit a Co film 1014 on the wafer. Subsequently, the wafer is transferred to a Ti sputtering chamber in a vacuum, and a TiN film 1015 is deposited on the wafer by a reactive sputtering method in the Ti sputtering chamber, and thereafter, the wafer is exposed to the atmosphere.
[0009]
Next, in a step shown in FIG. 5C, a first RTA process is performed on the wafer that has been exposed to the air after the deposition of the TiN film 1015 by using an RTA apparatus, and the unreacted Co film 1014 and the TiN film 1015 are removed. Selectively remove. The removal of the unreacted Co film 1014 and TiN film 1015 can be performed, for example, by using an acidic chemical solution obtained by mixing sulfuric acid or hydrochloric acid with hydrogen peroxide solution, or an alkaline chemical solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution. Can be performed. After that, the wafer is subjected to a second RTA process so that the upper part of the N-type high concentration source / drain diffusion layer 1002b and the upper part of the P-type high concentration source / drain diffusion layer 1002b, An occupied silicide film 1016p on the P-type diffusion layer and a silicide film 1016b on the gate are formed. The silicide film 1016n on the N-type diffusion layer and the silicide film 1016p on the P-type diffusion layer function as source / drain regions together with the N-type high-concentration source / drain diffusion layers 1001b and 1002b, respectively. The on-gate silicide film 1016b functions as a gate electrode together with the polysilicon gate electrodes 1022 and 1032.
[0010]
Next, in the step shown in FIG. 5D, the LP-SiN film 1017 and the HDP-SiO ₂ A first interlayer insulating film 1045 including a film 1018 (an oxide film formed by high-density plasma CVD) is formed, and the first interlayer insulating film 1045 is planarized by a CMP method. Further, a connection hole 1050 penetrating the first interlayer insulating film 1045 and reaching each of the silicide films 1016n and 1016p is formed.
[0011]
Next, in a step shown in FIG. 6A, a first tungsten plug 1060 is formed by burying a base film 1061 made of a Ti film, a barrier film 1062 made of a TiN film, and a W film 1063 in the connection holes.
[0012]
Next, in the step shown in FIG. 6B, HDP-SiO 2 is formed on the first interlayer insulating film 1045 and the first tungsten plug 1060. ₂ A second interlayer insulating film 1047 made of a film is formed, and the second interlayer insulating film 1047 is planarized by a CMP method. Then, after forming a connection hole reaching the first tungsten plug 1060 through the second interlayer insulating film 1047, a base film 107 made of a Ti film, a barrier film 1072 made of a TiN film, and W The second tungsten plug 1070 is formed by burying the film 1073.
[0013]
Next, in the step shown in FIG. 6C, HDP-SiO 2 is formed on the second interlayer insulating film 1047 and the second tungsten plug 1070. ₂ A third interlayer insulating film 1049 made of a film is formed, and the third interlayer insulating film 1049 is planarized by a CMP method. Although illustration of subsequent steps is omitted, a memory cell forming step, a multilayer wiring forming step, and the like are performed. In a subsequent step, the stack contact structure including the first and second tungsten plugs 1060, 1070,... Is three-dimensionally surrounded by an interlayer insulating film, and is subjected to a high temperature and a long time in a memory cell forming step. Heat treatment is performed.
[0014]
[Non-patent document 1]
Appl. Phys. Lett. 58, 1308 (1991)
[Non-patent document 2]
Appl. Phys. Lett. 68 (24), 3461 (1996)
[Non-Patent Document 3]
Appl. Phys. Lett. 74 (20), 2930 (1999)
[0015]
[Problems to be solved by the invention]
However, the above-described conventional DRAM-embedded semiconductor device having a stack contact structure provided on a cobalt silicide layer (cobalt silicide film) on a diffusion layer has the following problems.
[0016]
FIG. 7 is a diagram showing a measurement result of a contact resistance of a tungsten plug in the conventional DRAM embedded semiconductor device. In the sample of the DRAM-embedded semiconductor device from which the data of FIG. 7 has been collected, a high-temperature and long-time heat treatment in a memory cell forming step is performed after each tungsten plug is formed. In FIG. 7, data indicated by Δ indicates the contact resistance to the cobalt silicide film on the N-type diffusion layer, and data indicated by ○ indicates the contact resistance to the cobalt silicide film on the P-type diffusion layer. In FIG. 7, the horizontal axis represents the contact resistance, and the vertical axis represents the cumulative frequency distribution. Referring to FIG. 7, it can be seen that the contact resistance to the cobalt silicide film on the N-type diffusion layer is larger than that of the cobalt silicide film on the P-type diffusion layer, and that the variation in the resistance value is larger.
[0017]
From this, it was found that the tungsten plug has low heat resistance to the cobalt silicide film on the N-type diffusion layer.
[0018]
FIG. 8 is a cross-sectional TEM photograph taken for failure analysis of a contact portion between the cobalt silicide film on the N-type diffusion layer and the tungsten plug. The sample from which the data of FIG. 8 is collected is a sample having a contact resistance of about 1000Ω among the many samples shown in FIG. Referring to FIG. 8, it can be seen that voids presumed to be caused by agglomeration of silicide are present at the interface between the cobalt silicide film and the contact metal Ti film. That is, it is considered that the contact area between the tungsten plug and the cobalt silicide film was reduced due to the void, and the contact resistance value was increased. The generation of the voids is considered to be caused by the aggregation of the silicide crystal grains constituting the cobalt silicide film.
[0019]
Here, the present inventors have found that while agglomeration of silicide crystal grains hardly occurs in the cobalt silicide film on the P-type diffusion layer, agglomeration of silicide crystal grains easily occurs in the cobalt silicide film on the N-type diffusion layer. As a result of analyzing the factors, the following factors were suggested. The factor is the degree of epitaxial growth of the cobalt silicide film on the silicon substrate (hereinafter referred to as epi intensity). In the epitaxial growth of a cobalt silicide film on a silicon substrate, the relationship between the crystal orientation of the cobalt silicide film and the silicon substrate is CoSi. ₂ It is considered to occur when (100) ‖Si (100) is satisfied.
[0020]
On the other hand, the degree of epitaxial growth depends on CoSi of the cobalt silicide film. ₂ (400) X-ray diffraction intensity (hereinafter simply referred to as “XRD intensity”). That is, in XRD measurement, CoSi ₂ No peak of (100) is detected, and CoSi detected near 2θ = 34 ° ₂ Since the peak of (200) is extremely low, CoSi detected near 2θ = 71 ° ₂ The degree of epitaxial growth is represented by the XRD intensity of the (400) peak.
[0021]
Aggregation of silicide crystal grains is more likely to occur because the crystal grains of the silicide film are finer because the number of grain boundaries is large. Therefore, it is presumed that the reason for aggregation in the cobalt silicide film on the N-type diffusion layer is that the degree of epitaxial growth of the cobalt silicide film on the N-type diffusion layer is lower than that of the cobalt silicide film on the P-type diffusion layer.
[0022]
Therefore, the present inventors have developed a sample of a substrate (N-type diffusion substrate) in which high-concentration N-type impurities are ion-implanted on the entire surface, and a substrate (P-type diffusion substrate) in which high-concentration P-type impurities are ion-implanted in the entire surface. And a sample of the substrate were separately prepared, and the degree of epitaxial growth was measured for each sample.
[0023]
FIG. 9 is a table showing the measurement results of XRD intensity (degree of epitaxial growth) for a sample of an N-type diffusion substrate and a sample of a P-type diffusion substrate. As shown in the figure, the degree of epitaxial growth of the silicide film is more than twice as high for the P-type diffusion substrate as for the N-type diffusion substrate, and the degree of epitaxial growth for the silicide film on the N-type diffusion substrate is also low. It was found that they easily aggregated.
[0024]
Further, factors other than the epi-strength of the cobalt silicide film may be considered as factors related to the decrease in the heat resistance of the contact.
[0025]
It is an object of the present invention to suppress an increase in contact resistance in a semiconductor device and a method of manufacturing the same, by taking measures for suppressing agglomeration of crystal grains of a silicide film on an N-type diffusion layer during a high-temperature heat treatment.
[0026]
[Means for Solving the Problems]
The first semiconductor device of the present invention extends from the first plug on the N-type diffusion layer, which penetrates the first interlayer insulating film and contacts the silicide film on the N-type diffusion layer, to a part of the first interlayer insulating film. A stress relaxation pad made of a metal film is provided on the region.
[0027]
This alleviates the stress applied to the contact portion between the silicide film on the N-type diffusion layer and the first plug on the N-type diffusion layer, thereby suppressing the aggregation of silicide crystal grains even in a relatively high-temperature heat treatment. Is done. Therefore, it is possible to suppress an increase in contact resistance due to, for example, generation of a void near the interface between the silicide film on the N-type diffusion layer and the first plug on the N-type diffusion layer.
[0028]
A stress relaxation pad may or may not be provided on the first plug on the P-type diffusion layer.
[0029]
The area of the stress relaxation pad is preferably at least 1.5 times the area of the first plug on the N-type diffusion layer.
[0030]
When the first and second interlayer insulating films are deposited by high-density plasma CVD, the contact between the silicide film on the N-type diffusion layer and the first plug on the N-type diffusion layer during high-temperature heat treatment. A particularly large thermal stress is applied to the portion, and even in that case, an increase in contact resistance can be suppressed.
[0031]
The same applies to the case where a third interlayer insulating film deposited by high-density plasma CVD is provided on the second interlayer insulating film.
[0032]
In the second semiconductor device of the present invention, nitrogen is introduced into a region of the silicide film on the N-type diffusion layer which is in contact with the first plug on the N-type diffusion layer.
[0033]
Thereby, diffusion of each atom in the silicide film on the N-type diffusion layer is prevented, so that aggregation of crystal grains of the silicide film on the N-type diffusion layer is suppressed. Therefore, it is possible to suppress an increase in contact resistance due to, for example, generation of a void near the interface between the silicide film on the N-type diffusion layer and the first plug on the N-type diffusion layer.
[0034]
In that case, nitrogen may or may not be introduced into a region of the silicide film on the P-type diffusion layer that contacts the first plug on the P-type diffusion layer.
[0035]
The first and second semiconductor devices of the present invention include a DRAM memory cell and a logic transistor, and when the N-type diffusion layer and the P-type diffusion layer are the source / drain regions of the logic transistor, The effect of suppressing an increase in contact resistance can be exhibited in a DRAM-embedded semiconductor device that is subjected to a high-temperature heat treatment after forming a transistor for use.
[0036]
According to a first method of manufacturing a semiconductor device of the present invention, first connection holes are formed to penetrate a first interlayer insulating film and reach a silicide film on an N-type diffusion layer and a silicide film on a P-type diffusion layer, respectively. Forming a first plug on the N-type diffusion layer and a first plug on the P-type diffusion layer by burying a conductive material in the first connection hole, and then forming a first interlayer insulating film from the first plug on the N-type diffusion layer; A stress relaxation pad made of a conductive material is formed on a region extending over a part of the second interlayer insulating film, and thereafter, a second interlayer insulating film and a second plug on an N-type diffusion layer are formed. Thus, the first semiconductor device can be easily manufactured.
[0037]
According to the second method of manufacturing a semiconductor device of the present invention, first connection holes are formed to penetrate the first interlayer insulating film and reach the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer, respectively. Then, nitrogen is introduced into the silicide film on the N-type diffusion layer. According to this method, the second semiconductor device can be easily manufactured.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
1A to 2C are cross-sectional views illustrating a manufacturing process of a first embodiment of a semiconductor device having a stress relaxation pad provided in a stack contact structure. 1A to 2C, the left half is an NMISFET region Rnt which is a region for forming an N-channel MIS transistor, and the right half is a PMISFET formation region Rpt which is a region for forming a P-channel MIS transistor. Are respectively shown.
[0039]
The semiconductor device of the present embodiment is a DRAM-embedded semiconductor device, and a DRAM memory cell having a memory cell capacitor having a stack capacitance is arranged in a region (not shown). As the structure of the memory cell, various known structures can be employed.
[0040]
First, in a step shown in FIG. 1A, a shallow trench 111 which is an element isolation region surrounding an active region is formed on a silicon substrate 100 (wafer) having at least an upper portion serving as a semiconductor layer. In the NMISFET formation region Rnt, a gate oxide film 121 having a thickness of 5 nm, a polysilicon gate electrode 122 formed of an N-type polysilicon film having a thickness of 100 nm, and a nitride film having a lateral thickness of 70 nm are formed. An insulating sidewall 123 is formed. In the PMISFET formation region Rpt, a gate oxide film 131 having a thickness of 5 nm, a polysilicon gate electrode 132 formed of a P-type polysilicon film having a thickness of 100 nm, and an insulating film formed of a nitride film having a thickness of 70 nm in a lateral direction are provided. A sidewall 133 is formed. It should be noted that the silicon substrate 100 may be a bulk silicon substrate in which the entire substrate is formed of a semiconductor, or that the upper portion is formed of a semiconductor layer and the entire lower region of the upper semiconductor layer is formed of an insulating layer. Alternatively, an SOI substrate in which an insulating layer is formed in an intermediate portion of a semiconductor substrate and a semiconductor layer is provided above the insulating layer may be used.
[0041]
However, after forming the gate oxide films 121 and 131 and the polysilicon gate electrodes 122 and 132, before forming the insulating sidewalls 123 and 133, the NMISFET formation region Rnt and the PMISFET formation region Rpt are individually reduced. In the NMISFET formation region Rnt, an N-type low-concentration source / drain diffusion layer 101a (extension layer or LDD layer) is formed in a self-alignment manner with the polysilicon gate electrode 122 by ion implantation of a concentration impurity. In Rpt, a P-type low concentration source / drain diffusion layer 102a (extension layer or LDD layer) is formed in a self-aligned manner with the polysilicon gate electrode 132. Thereafter, after the insulating sidewalls 123 and 133 are formed, high-concentration impurity ions are individually implanted into the NMISFET forming region Rnt and the PMISFET forming region Rpt, and the insulating sidewall 123 is formed in the NMISFET forming region Rnt. An N-type high-concentration source / drain diffusion layer 101b is formed in a self-aligned manner, and a P-type high-concentration source / drain diffusion layer 102b is formed in a self-aligned manner on an insulating sidewall 133 in a PMISFET formation region Rpt.
[0042]
Further, an N-type impurity such as arsenic or phosphorus may be introduced into the polysilicon electrode 122 of the NMISFET by ion implantation in a state of a polysilicon film. However, an N-type impurity (arsenic or phosphorus) and a P-type impurity (boron) are introduced into each of the polysilicon gate electrodes 122 and 132 by ion implantation for forming a high concentration source / drain diffusion layer.
[0043]
Next, in the step shown in FIG. 1B, before the Co film is formed, sputter etching using argon plasma (pressure 0.4 mTorr, plasma power 400 W, bias power 260 W, substrate bias -120 V, etching time 5 seconds). To remove the natural oxide film by physical sputtering of argon ions. Thereafter, when the sputter etching is completed, the wafer is transferred to a Co sputtering chamber in a vacuum. In a Co sputtering chamber, sputtering is performed under the conditions of a pressure of 2.0 mTorr and a DC power of 100 W to deposit a 7 nm-thick Co film 114 on the wafer. Subsequently, the wafer is transferred to a Ti sputtering chamber in a vacuum, and the wafer is subjected to reactive sputtering in the Ti sputtering chamber under the conditions of a pressure of 4.5 mTorr, a DC power of 7200 W, and an argon flow rate / nitrogen flow rate = 2/3. A TiN film 115 having a thickness of 20 nm is deposited thereon, and then the wafer is exposed to the air.
[0044]
Next, in the step shown in FIG. 1C, the first RTA treatment is performed on the wafer exposed to the air after the deposition of the TiN film 115 at 470 ° C. for 60 seconds by the RTA apparatus, and unreacted. The Co film 114 and the TiN film 115 are selectively removed. The removal of the unreacted Co film 114 and the TiN film 115 is performed by, for example, an acidic chemical solution obtained by mixing sulfuric acid or hydrochloric acid with hydrogen peroxide solution, or an alkaline chemical solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution. Can be performed. Thereafter, the wafer is subjected to a second RTA process at 850 ° C. for 60 seconds, and a silicide film 116n on the N-type diffusion layer is deposited on the N-type high-concentration source / drain diffusion layer 101b. A silicide film 116p on the P-type diffusion layer is formed on the drain diffusion layer 102b, and a silicide film 116b on the gate is formed on the polysilicon gate electrodes 122 and 132. Source / drain regions are constituted by the silicide films 116n and 116p on the respective diffusion layers, the high concentration source / drain diffusion layers 101b and 102b, and the low concentration source / drain regions 101a and 102a. A gate electrode is formed by the on-gate silicide film 116b and the polysilicon gate electrodes 122 and 132.
[0045]
Next, in the step shown in FIG. 1D, an LP-SiN film 117 having a thickness of 50 nm (a nitride film formed by low-pressure CVD) and an HDP-SiO film having a thickness of 400 nm are formed on the substrate. ₂ A first interlayer insulating film 145 including the film 118 (an oxide film formed by high-density plasma CVD) is formed, and the first interlayer insulating film 145 is planarized by a CMP method. Further, first connection holes (not shown) reaching the silicide film 116n on the N-type diffusion layer and the silicide film 116p on the P-type diffusion layer through the first interlayer insulating film 145 by photolithography and dry etching. Is formed, a base film 161 made of a Ti film, a barrier film 162 made of a TiN film, and a W film 163 are buried in each first connection hole, so that the N-type diffusion layer is in contact with the silicide film 116n. A first plug 160n and a first plug 160p on the P-type diffusion layer that is in contact with the P-type diffusion layer silicide film 116p are formed. At this time, a Ti film having a thickness of 20 nm was deposited by a sputtering method under the conditions of a pressure of 1.5 mTorr and a DC power of 11000 W, and by a sputtering method, a pressure of 4.5 mTorr, a DC power of 7200 W and an argon flow rate / nitrogen flow rate = 3/7. A TiN film having a thickness of 50 nm is deposited on the Ti film under the conditions described above, and a W film having a thickness of 200 nm is sequentially formed by the CVD method. After that, the W film, the TiN film, and the Ti film on the first interlayer insulating film 145 are polished and removed by using the CMP method, so that the Ti film, the TiN film, and the W film are embedded in the respective first connection holes.
[0046]
Next, in the step shown in FIG. 2A, a 5 nm-thick Ti film, a 10 nm-thick TiN film and a 10 nm-thick TiN film are formed on the first interlayer insulating film 145 and the first plugs 160n and 160p by sputtering. A 50 nm-thick W film is sequentially deposited to form a Ti / TiN / W laminated film 151. Thereafter, a resist film 153 is formed on the Ti / TiN / W laminated film 151 to cover a pad formation region (a region including the first plug 160n on the N-type diffusion layer).
[0047]
Next, using the resist film 153 as a mask, the Ti / TiN / W laminated film 151 is patterned to form a stress relaxing metal pad 152 covering the first plug 160n on the N-type diffusion layer. On the other hand, no metal pad for stress relaxation is formed above the first plug 160p on the P-type diffusion layer.
[0048]
Next, in the step shown in FIG. 2B, after removing the resist film 153, a thickness is formed on the first interlayer insulating film 145, the metal pad 152 for stress relaxation, and the first plug 160p on the P-type diffusion layer. 300 nm HDP-SiO ₂ A second interlayer insulating film 147 made of a film is deposited, and the second interlayer insulating film 147 is planarized by a CMP method. Thereafter, by photolithography and dry etching, the second connection on the N-type diffusion layer that penetrates through the second interlayer insulating film 147 and reaches the first plug 160p on the P-type diffusion layer and the metal pad 152 for stress relaxation respectively. After forming a hole and second connection holes on the P-type diffusion layer (both not shown), a base film 171 made of a Ti film, a barrier film 172 made of a TiN film, and a W film 173 are formed in each second connection hole. By burying, a second plug 170n on the N-type diffusion layer contacting the metal pad 152 for stress relaxation and a second plug 170p on the P-type diffusion layer contacting the first plug 160p on the P-type diffusion layer are formed. At this time, after depositing a Ti film, a TiN film, and a W film under the same conditions as those shown in FIG. 1D, the Ti film, the TiN film, and the W film are buried in each second connection hole by the CMP method. . As a result, a stack contact consisting of the metal pad 152 for stress relaxation, the first plug 160n on the N-type diffusion layer and the second plug 170n on the N-type diffusion layer sandwiching the metal pad 152 for stress relaxation is provided above the silicide film 116n on the N-type diffusion layer. A structure is formed. On the other hand, above the silicide film 116p on the P-type diffusion layer, a stack contact structure including the first plug 160p on the P-type diffusion layer and the second plug 170p on the P-type diffusion layer without sandwiching the metal pad for stress relaxation is formed. You.
[0049]
Next, in the step shown in FIG. 2C, a 300 nm-thick HDP-layer is formed on the second interlayer insulating film 147, the second plug 170n on the N-type diffusion layer and the second plug 170p on the P-type diffusion layer. SiO ₂ After depositing the third interlayer insulating film 149 made of a film, the second interlayer insulating film 149 is planarized by the CMP method. Although illustration of the subsequent steps is omitted, a third connection hole is formed in the third interlayer insulating film through the memory cell forming step, and the N-type diffusion layer is connected to the second plug 170n. The formation of the third plug on the P-type diffusion layer connected to the third plug and the second plug 170p on the P-type diffusion layer, the formation of an upper multilayer wiring layer by the subsequent damascene method, and the like are performed. Thus, the first plug 160n on the N-type diffusion layer, the metal plug 152 for stress relaxation, the second plug 170n on the N-type diffusion layer, and the N above the silicide film 116n on the N-type diffusion layer containing high-concentration nitrogen. A stack contact structure including the third plug is formed on the mold diffusion layer. On the other hand, a stack contact structure including the first plug 160p on the P-type diffusion layer, the second plug 170p on the P-type diffusion layer, and the third plug on the P-type diffusion layer is formed above the silicide film 116p on the P-type diffusion layer. Is done.
[0050]
In a step subsequent to the step shown in FIG. 2C, the respective stack contact structures above the silicide film 116n on the N-type diffusion layer and the silicide film 116p on the P-type diffusion layer are three-dimensionally first and second. And the third interlayer insulating films 145, 147, and 149, and are subjected to a high-temperature and long-time heat treatment in the memory cell forming step.
[0051]
Here, in the stack contact structure above the silicide film 116n on the N-type diffusion layer formed by the manufacturing process of this embodiment, the first plug 160n on the N-type diffusion layer and the second plug 170n on the N-type diffusion layer Since the stress relaxing metal pad 152 is interposed between the first, second and third interlayer insulating films 145 and 147 even after a high-temperature and long-time memory cell forming process after the formation of the stack contact structure. , 149 are relieved by the metal pad 152 for relieving stress. Therefore, even if a high-temperature and long-time heat treatment process is subsequently performed, the problem that the contact resistance increases due to aggregation of silicide crystal grains as in the conventional silicide film on the N-type high-concentration source / drain diffusion layer is avoided. Therefore, the heat resistance of the stack contact structure can be improved.
[0052]
In particular, in a DRAM / logic embedded semiconductor device (DRAM embedded device), after forming a first interlayer insulating film, a second interlayer insulating film, each first plug, and each second plug of a logic transistor, In a process of forming a capacitor of a DRAM memory cell (for example, a thermal oxidation process for forming an ON film, an ONO film, etc.), a heat treatment at a high temperature of about 800 ° C. for a long time is often performed. In this case, the contact resistance is likely to increase particularly due to the aggregation of the crystal grains of the silicide film on the N-type diffusion layer. Therefore, the present embodiment can exert a remarkable effect in the DRAM embedded semiconductor device.
[0053]
Note that the metal film for the metal pad according to the present embodiment can be used as a wiring (for example, a local wiring). Further, even when a titanium silicide film or a nickel silicide film is used as the silicide film on the N-type diffusion layer, contact resistance may increase due to aggregation of crystal grains as in the case of the cobalt silicide film. Therefore, the present embodiment can exhibit the above-described effects when any one of a titanium silicide film, a cobalt silicide film, and a nickel silicide film is formed as the silicide film.
[0054]
FIGS. 10A to 10C are a diagram showing data of contact resistance in a stack contact structure on an N-type diffusion layer according to the related art and the first embodiment, respectively, and a cross-sectional view showing a conventional stack contact structure. FIG. 2 is a cross-sectional view illustrating a stack contact structure according to the first embodiment. The data of the first embodiment shown in FIG. 10A shows that a Ti / TiN / 5 nm / 10 nm / 50 nm thick Ti / TiN / 50 nm is provided between the first plug on the N-type diffusion layer and the second plug on the N-type diffusion layer. It is made of W laminated film and has an area of 1μm ² Obtained by using a stack contact structure sandwiching the metal pad.
[0055]
Referring to FIG. 10A, it can be seen that the stack contact structure of the present embodiment has a smaller contact resistance and a smaller variation in resistance value than the conventional stack contact structure. That is, by forming a stack contact structure sandwiching the stress relaxation metal pad, it is possible to suppress the generation of voids in the silicide film on the N-type diffusion layer having essentially low heat resistance. This is because the high-temperature and long-time processing in the memory cell forming step causes the first, second, and third interlayer insulating films to pass through the second plug on the N-type diffusion layer, the first plug on the N-type diffusion layer, and the N-type diffusion layer. This is presumed to be because the thermal stress acting on the upper silicide film is reduced by the metal pad for stress relaxation, thereby suppressing the aggregation of crystal grains in the silicide film on the N-type diffusion layer.
[0056]
In the steps shown in FIGS. 2A and 2B of the first embodiment, a stress relaxation metal pad may be formed also on the first plug 160p on the P-type diffusion layer.
[0057]
The diameter of the metal pad for stress relaxation is preferably at least 1.2 times the diameter of each connection hole in consideration of the displacement of the mask in photolithography, enlargement of the connection hole by etching, and reduction of the metal pad by etching. That is, the area of the metal pad for stress relaxation is preferably at least 1.5 times the area of the connection hole on the N-type diffusion layer or the plug on the N-type diffusion layer.
[0058]
(Second embodiment)
FIGS. 3A to 4C are cross-sectional views illustrating manufacturing steps of a second embodiment of a semiconductor device in which nitrogen is injected into a silicide film on an N-type diffusion layer. 3A to 4C, the left half is an NMISFET region Rnt which is a region for forming an N-channel MIS transistor, and the right half is a PMISFET formation region Rpt which is a region for forming a P-channel MIS transistor. Are respectively shown.
[0059]
The semiconductor device of the present embodiment is a DRAM-embedded semiconductor device, and a DRAM memory cell having a memory cell capacitor having a stack capacitance is arranged in a region (not shown). As the structure of this memory cell, various well-known structures can be adopted.
[0060]
First, in a step shown in FIG. 3A, a shallow trench 111 which is an element isolation region surrounding an active region is formed on a silicon substrate 100 (wafer) having at least an upper portion serving as a semiconductor layer. In the NMISFET formation region Rnt, a gate oxide film 121 having a thickness of 5 nm, a polysilicon gate electrode 122 formed of an N-type polysilicon film having a thickness of 100 nm, and a nitride film having a lateral thickness of 70 nm are formed. An insulating sidewall 123 is formed. In the PMISFET formation region Rpt, a gate oxide film 131 having a thickness of 5 nm, a polysilicon gate electrode 132 formed of a P-type polysilicon film having a thickness of 100 nm, and an insulating film formed of a nitride film having a thickness of 70 nm in a lateral direction are provided. A sidewall 133 is formed. It should be noted that the silicon substrate 100 may be a bulk silicon substrate in which the entire substrate is formed of a semiconductor, or that the upper portion is formed of a semiconductor layer and the entire lower region of the upper semiconductor layer is formed of an insulating layer. Alternatively, an SOI substrate in which an insulating layer is formed in an intermediate portion of a semiconductor substrate and a semiconductor layer is provided above the insulating layer may be used.
[0061]
However, after forming the gate oxide films 121 and 131 and the polysilicon gate electrodes 122 and 132, before forming the insulating sidewalls 123 and 133, the NMISFET formation region Rnt and the PMISFET formation region Rpt are individually reduced. In the NMISFET formation region Rnt, an N-type low-concentration source / drain diffusion layer 101a (extension layer or LDD layer) is formed in a self-alignment manner with the polysilicon gate electrode 122 by ion implantation of a concentration impurity. In Rpt, a P-type low concentration source / drain diffusion layer 102a (extension layer or LDD layer) is formed in a self-aligned manner with the polysilicon gate electrode 132. Thereafter, after the insulating sidewalls 123 and 133 are formed, high-concentration impurity ions are individually implanted into the NMISFET forming region Rnt and the PMISFET forming region Rpt, and the insulating sidewall 123 is formed in the NMISFET forming region Rnt. An N-type high-concentration source / drain diffusion layer 101b is formed in a self-aligned manner, and a P-type high-concentration source / drain diffusion layer 102b is formed in a self-aligned manner on an insulating sidewall 133 in a PMISFET formation region Rpt.
[0062]
Further, an N-type impurity such as arsenic or phosphorus may be introduced into the polysilicon electrode 122 of the NMISFET by ion implantation in a state of a polysilicon film. However, an N-type impurity (arsenic or phosphorus) and a P-type impurity (boron) are introduced into each of the polysilicon gate electrodes 122 and 132 by ion implantation for forming a high concentration source / drain diffusion layer.
[0063]
Next, in the step shown in FIG. 3B, the same steps as those shown in FIGS. 1B and 1C in the first embodiment are performed. First, before forming a Co film, sputter etching is performed by argon plasma (pressure 0.4 mTorr, plasma power 400 W, bias power 260 W, substrate bias -120 V, etching time 5 seconds), and natural sputtering by physical sputtering of argon ions. The oxide film is removed. Thereafter, when the sputter etching is completed, the wafer is transferred to a Co sputtering chamber in a vacuum. In a Co sputtering chamber, sputtering is performed under the conditions of a pressure of 2.0 mTorr and a DC power of 100 W to deposit a 7 nm-thick Co film 114 on the wafer. Subsequently, the wafer is transferred to a Ti sputtering chamber in a vacuum, and the wafer is subjected to reactive sputtering in the Ti sputtering chamber under the conditions of a pressure of 4.5 mTorr, a DC power of 7200 W, and an argon flow rate / nitrogen flow rate = 2/3. A TiN film 115 having a thickness of 20 nm is deposited thereon, and then the wafer is exposed to the air.
[0064]
Further, the first RTA treatment is performed on the wafer exposed to the atmosphere after the deposition of the TiN film 115 at 470 ° C. for 60 seconds by the RTA apparatus, and the unreacted Co film 114 and the TiN film 115 are selectively formed. To be removed. The removal of the unreacted Co film 114 and the TiN film 115 is performed by, for example, an acidic chemical solution obtained by mixing sulfuric acid or hydrochloric acid with hydrogen peroxide solution, or an alkaline chemical solution obtained by mixing ammonium hydroxide and hydrogen peroxide solution. Can be performed. Thereafter, the wafer is subjected to a second RTA process at 850 ° C. for 60 seconds, and a silicide film 116n on the N-type diffusion layer is placed above the N-type high-concentration source / drain diffusion layer 101b. A silicide film 116p on the P-type diffusion layer is formed above the drain diffusion layer 102b, and a silicide film 116b on the gate is formed on the polysilicon gate electrodes 122 and 132, respectively. Source / drain regions are constituted by the silicide films 116n and 116p on the respective diffusion layers, the high concentration source / drain diffusion layers 101b and 102b, and the low concentration source / drain regions 101a and 102a. A gate electrode is formed by the on-gate silicide film 116b and the polysilicon gate electrodes 122 and 132.
[0065]
Next, in a step shown in FIG. 3C, an LP-SiN film 117 having a thickness of 50 nm and an HDP-SiO film having a thickness of 400 nm are formed on the substrate. ₂ A first interlayer insulating film 145 including the film 118 is formed, and the first interlayer insulating film 145 is planarized by a CMP method. Further, by photolithography and dry etching, the first connection hole 150n on the N-type diffusion layer reaching the silicide film 116n on the N-type diffusion layer through the first interlayer insulation film 145, and the first interlayer insulation film 145 And a first connection hole 150p on the P-type diffusion layer reaching the silicide film 116p on the P-type diffusion layer.
[0066]
Next, in the step shown in FIG. 3D, an acceleration voltage of 10 keV and a dose of 8.0 × 10 ¹⁴ cm ^-2 Under the condition, nitrogen ion (N ⁺ Inject). Thereby, nitrogen is introduced into the silicide film 116n on the N-type diffusion layer and the silicide film 116p on the P-type diffusion layer.
[0067]
Next, in a step shown in FIG. 4A, a base film 161 made of a Ti film, a barrier film 162 made of a TiN film, and a W film 163 are buried in the first connection holes 150n and 150p to form an N-type diffusion layer. A first plug 160n on the N-type diffusion layer contacting the silicide film 116n and a first plug 160p on the P-type diffusion layer contacting the P-type diffusion layer silicide film 116p are formed. At this time, a Ti film having a thickness of 20 nm was deposited by a sputtering method under the conditions of a pressure of 1.5 mTorr and a DC power of 11000 W, and by a sputtering method, a pressure of 4.5 mTorr, a DC power of 7200 W and an argon flow rate / nitrogen flow rate = 3/7. A TiN film having a thickness of 50 nm is deposited on the Ti film under the conditions described above, and a W film having a thickness of 200 nm is sequentially formed by the CVD method. After that, the W film, the TiN film, and the Ti film on the first interlayer insulating film 145 are polished and removed by using the CMP method, so that the Ti film, the TiN film, and the W film are embedded in the respective first connection holes.
[0068]
Next, in the step shown in FIG. 4B, a 300 nm-thick HDP-film is formed on the first interlayer insulating film 145, the first plug 160n on the N-type diffusion layer and the first plug 160p on the P-type diffusion layer. SiO ₂ A second interlayer insulating film 147 made of a film is deposited, and the second interlayer insulating film 147 is planarized by a CMP method. After that, by photolithography and dry etching, the first plug 160n on the N-type diffusion layer and the first plug 160n on the N-type diffusion layer reaching the first plug 160p on the P-type diffusion layer through the second interlayer insulating film 147, respectively. After forming two connection holes and second connection holes (not shown) on the P-type diffusion layer, a base film 171 made of a Ti film, a barrier film 172 made of a TiN film, and a W film are formed in each second connection hole. 173 are buried, the second plug 170n on the N-type diffusion layer contacting the first plug 160n on the N-type diffusion layer, and the second plug 170p on the P-type diffusion layer contacting the first plug 160p on the P-type diffusion layer. To form
[0069]
Next, in the step shown in FIG. 4C, a 300 nm-thick HDP-layer is formed on the second interlayer insulating film 147, the second plug 170n on the N-type diffusion layer and the second plug 170p on the P-type diffusion layer. SiO ₂ After depositing the third interlayer insulating film 149 made of a film, the second interlayer insulating film 149 is planarized by the CMP method. Although illustration of the subsequent steps is omitted, a third connection hole is formed in the third interlayer insulating film through the memory cell forming step, and the N-type diffusion layer is connected to the second plug 170n. The formation of the third plug on the P-type diffusion layer connected to the third plug and the second plug 170p on the P-type diffusion layer, the formation of an upper multilayer wiring layer by the subsequent damascene method, and the like are performed. Thus, the first plug 160n on the N-type diffusion layer, the second plug 170n on the N-type diffusion layer, and the third plug on the N-type diffusion layer are located above the silicide film 116n on the N-type diffusion layer containing high-concentration nitrogen. Is formed. On the other hand, a stack contact structure including the first plug 160p on the P-type diffusion layer, the second plug 170p on the P-type diffusion layer, and the third plug on the P-type diffusion layer is formed above the silicide film 116p on the P-type diffusion layer. Is done.
[0070]
In a step subsequent to the step shown in FIG. 4C, each of the stack contact structures above the silicide film 116n on the N-type diffusion layer and the silicide film 116p on the P-type diffusion layer is three-dimensionally first and second. And the third interlayer insulating films 145, 147, and 149, and are subjected to a high-temperature and long-time heat treatment in the memory cell forming step.
[0071]
Here, nitrogen is implanted into a region of the silicide film 116n on the N-type diffusion layer 116n formed by the manufacturing process of the present embodiment, which is in contact with the first plug 160n on the N-type diffusion layer. Since nitrogen atoms are present in the silicide crystal grains and at grain boundaries in the upper silicide film 116n, diffusion of cobalt atoms and silicon atoms is prevented. Therefore, even if a high-temperature and long-time heat treatment process is subsequently performed, the problem that the contact resistance increases due to aggregation of silicide crystal grains as in the conventional silicide film on the N-type high-concentration source / drain diffusion layer is avoided. Therefore, the heat resistance of the stack contact structure can be improved.
[0072]
In particular, in a DRAM / logic embedded semiconductor device (DRAM embedded device), after forming a first interlayer insulating film, a second interlayer insulating film, each first plug, and each second plug of a logic transistor, In a process of forming a capacitor of a DRAM memory cell (for example, a thermal oxidation process for forming an ON film, an ONO film, etc.), a heat treatment at a high temperature of about 800 ° C. for a long time is often performed. In this case, the contact resistance is likely to increase particularly due to the aggregation of the crystal grains of the silicide film on the N-type diffusion layer. Therefore, the present embodiment can exert a remarkable effect in the DRAM embedded semiconductor device.
[0073]
Note that the metal film for the metal pad according to the present embodiment can be used as a wiring (for example, a local wiring). Further, even when a titanium silicide film or a nickel silicide film is used as the silicide film on the N-type diffusion layer, contact resistance may increase due to aggregation of crystal grains as in the case of the cobalt silicide film. Therefore, the present embodiment can exhibit the above-described effects when any one of a titanium silicide film, a cobalt silicide film, and a nickel silicide film is formed as the silicide film.
[0074]
In the step shown in FIG. 3D in the second embodiment, a region including the first connection hole 150n on the N-type diffusion layer is opened, and a resist film for closing the first connection hole 150p on the P-type diffusion layer is formed. Then, using this resist film as an implantation mask, nitrogen ions (N ⁺ ) May be injected. In this case, nitrogen is introduced into the silicide film 116n on the N-type diffusion layer, but nitrogen is not introduced into the silicide film 116p on the P-type diffusion layer. In this method, since nitrogen is not introduced into the silicide film 116p on the P-type diffusion layer compared to the second embodiment, it is advantageous in that the resistance in the stack contact structure on the silicide film 116p on the P-type diffusion layer is reduced. However, it is disadvantageous in that an additional photolithography step is required.
[0075]
In the second embodiment, instead of ion implantation of nitrogen into the silicide film, nitrogen may be introduced into the silicide film by heat treatment in a plasma containing nitrogen radicals or in an atmosphere containing nitrogen.
[0076]
In the first and second embodiments, HDP-SiO is used as the first to third interlayer insulating films 145, 147, and 149. ₂ Although the films are deposited, all of the interlayer insulating films or any one or more of the interlayer insulating films may be formed of a BPSG film, a BSG film, or a PSG film. However, HDP-SiO ₂ The film is more advantageous than the BPSG film in terms of denseness and burying property in a narrow groove portion, but generates a larger thermal stress than the BPSG film. ₂ When a film is used, each of the embodiments of the present invention can exert a remarkable effect.
[0077]
【The invention's effect】
According to the semiconductor device of the present invention or the method of manufacturing the same, a stress relaxation pad is interposed in the stack contact of the silicide film on the N-type diffusion layer to relieve the thermal stress of the interlayer insulating film, or By injecting nitrogen into the region near the boundary with the plug to suppress grain boundary diffusion, it is possible to prevent agglomeration of crystal grains of the silicide film on the N-type diffusion layer even after a high-temperature and long-time heat treatment step. An increase in resistance can be suppressed.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views showing a first half of a manufacturing process of a first embodiment of a semiconductor device provided with a stress relaxation pad.
FIGS. 2A to 2C are cross-sectional views showing the latter half of the manufacturing process of the first embodiment of the semiconductor device provided with the stress relaxation pad.
FIGS. 3A to 3D are cross-sectional views illustrating a first half of a manufacturing process according to a second embodiment of a semiconductor device in which nitrogen is implanted into a silicide film on an N-type diffusion layer.
FIGS. 4A to 4C are cross-sectional views illustrating a second half of a manufacturing process of a second embodiment of a semiconductor device in which nitrogen is implanted into a silicide film on an N-type diffusion layer.
FIGS. 5A to 5D are cross-sectional views showing a first half of a manufacturing process of a conventional DRAM embedded semiconductor device including a process of forming a metal plug in a silicide film on a diffusion layer.
FIGS. 6A to 6C are cross-sectional views showing a latter half of a manufacturing process of a conventional DRAM-embedded semiconductor device including a process of forming a metal plug in a silicide film on a diffusion layer.
FIG. 7 is a diagram showing a measurement result of a contact resistance of a tungsten plug in a conventional DRAM embedded semiconductor device.
FIG. 8 is a cross-sectional TEM photograph taken for failure analysis of a contact portion between a silicide film on an N-type diffusion layer and a tungsten plug.
FIG. 9 is a table showing measurement results of XRD intensity (degree of epitaxial growth) for a sample of an N-type diffusion substrate and a sample of a P-type diffusion substrate.
FIGS. 10A to 10C are a diagram showing data of contact resistance on an N-type diffusion layer according to the conventional technique and the first embodiment, a cross-sectional view showing a conventional stack contact structure, and FIGS. FIG. 2 is a cross-sectional view illustrating a stack contact structure according to one embodiment.
[Explanation of symbols]
100 silicon substrate
101a N-type low concentration source / drain diffusion layer
101b N-type high concentration source / drain diffusion layer
102a P-type low concentration source / drain diffusion layer
102b P-type high concentration source / drain diffusion layer
111 shallow trench
114 Co film
115 TiN film
116n silicide film on N-type diffusion layer
116p silicide film on P-type diffusion layer
116b Silicide film on gate
117 LP-SiN film
118 HDP-SiO ₂ film
121 Gate oxide film
122 Gate electrode
123 Sidewall
131 Gate oxide film
132 Gate electrode
133 Sidewall
145 first interlayer insulating film
147 Second interlayer insulating film
149 Third Interlayer Insulating Film
150n First connection hole on N-type diffusion layer
150p First connection hole on P-type diffusion layer
151 Ti / TiN / W laminated film
152 stress relief metal pad
153 resist film
160n First plug on N-type diffusion layer
160p First plug on P-type diffusion layer
161 Underlayer
162 barrier film
163 W film
170n Second plug on N-type diffusion layer
170p Second plug on P-type diffusion layer
171 Underlayer
172 barrier film
173 W film

Claims (24)

A semiconductor layer;
An N-type diffusion layer and a P-type diffusion layer provided in the semiconductor layer;
A silicide film on the N-type diffusion layer provided on the N-type diffusion layer, and a silicide film on the P-type diffusion layer provided on the P-type diffusion layer;
A first interlayer insulating film formed above the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer;
A first plug on the N-type diffusion layer connected to the silicide film on the N-type diffusion layer through the first interlayer insulating film;
A first plug on a P-type diffusion layer connected to the silicide film on the P-type diffusion layer through the first interlayer insulating film;
A stress relaxation pad made of a metal film formed on a region extending from the first plug on the N-type diffusion layer to a part of the first interlayer insulating film;
A second interlayer insulating film formed above the first interlayer insulating film, the stress relaxation pad, and the first plug on the P-type diffusion layer;
A semiconductor device comprising: a second plug on an N-type diffusion layer which reaches the stress relaxation pad through the second interlayer insulating film. The semiconductor device according to claim 1,
A semiconductor device further comprising a second plug on a P-type diffusion layer that penetrates the first interlayer insulating film and directly contacts the P-type diffusion layer. The semiconductor device according to claim 1,
Another stress relaxation pad made of a metal film formed on a region extending from the first plug on the P-type diffusion layer to a part of the first interlayer insulating film;
A second plug on a P-type diffusion layer which penetrates through the second interlayer insulating film and is connected to the another stress relaxation pad. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein an area of the stress relaxation pad is 1.5 times or more of the first plug on the N-type diffusion layer. The semiconductor device according to any one of claims 1 to 4,
At least one of the first and second interlayer insulating films is deposited by high-density plasma CVD. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the silicide film on the N-type diffusion layer is one film selected from a titanium silicide film, a cobalt silicide film, and a nickel silicide film. The semiconductor device according to any one of claims 1 to 6,
It has a DRAM memory cell and a logic transistor,
The semiconductor device, wherein the N-type diffusion layer and the P-type diffusion layer are source / drain regions of the logic transistor. A semiconductor layer;
An N-type diffusion layer and a P-type diffusion layer provided in the semiconductor layer;
A silicide film on the N-type diffusion layer provided on the N-type diffusion layer, and a silicide film on the P-type diffusion layer provided on the P-type diffusion layer;
A first interlayer insulating film formed above the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer;
A first plug on the N-type diffusion layer connected to the silicide film on the N-type diffusion layer through the first interlayer insulating film;
A first plug on a P-type diffusion layer connected to the silicide film on the P-type diffusion layer through the first interlayer insulating film;
A semiconductor device, wherein nitrogen is introduced into a region of the silicide film on the N-type diffusion layer which is in contact with the first plug on the N-type diffusion layer. The semiconductor device according to claim 8,
A semiconductor device, wherein nitrogen is introduced into a region of the silicide film on the P-type diffusion layer which is in contact with the first plug on the P-type diffusion layer. The semiconductor device according to claim 8, wherein
A second interlayer insulating film formed above the first interlayer insulating film, the first plug on the N-type diffusion layer, and the first plug on the P-type diffusion layer;
A second plug on the N-type diffusion layer that reaches the first plug on the N-type diffusion layer through the second interlayer insulating film;
And a second plug on the P-type diffusion layer that reaches the first plug on the P-type diffusion layer through the second interlayer insulating film. The semiconductor device according to claim 10,
At least one of the first and second interlayer insulating films is deposited by high-density plasma CVD. The semiconductor device according to any one of claims 8 to 11,
The semiconductor device, wherein the silicide film on the N-type diffusion layer is one film selected from a titanium silicide film, a cobalt silicide film, and a nickel silicide film. The semiconductor device according to any one of claims 8 to 12,
It has a DRAM memory cell and a logic transistor,
The semiconductor device, wherein the N-type diffusion layer and the P-type diffusion layer are source / drain regions of the logic transistor. (A) forming a P-type diffusion layer and an N-type diffusion layer by introducing a P-type impurity and an N-type impurity into each part of the semiconductor layer;
Forming a silicide film on the N-type diffusion layer and a silicide film on the P-type diffusion layer by silicidizing the upper portions of the N-type diffusion layer and the P-type diffusion layer (b);
After forming a first interlayer insulating film covering the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer, the silicide film on the N-type diffusion layer and the P layer penetrate the first interlayer insulating film. (C) forming first connection holes each reaching the silicide film on the type diffusion layer;
(D) forming a first plug on the N-type diffusion layer and a first plug on the P-type diffusion layer by burying a conductive material in the first connection hole;
After forming a metal film that covers the first plug on the first interlayer insulating film, the N-type diffusion layer, and the P-type diffusion layer, the metal film is patterned and the first plug on the N-type diffusion layer is formed. (E) forming a stress relaxation pad made of a conductive material on a region over a part of the first interlayer insulating film;
(F) forming a second interlayer insulating film covering the first interlayer insulating film, the stress relaxation pad, and the first plug on the P-type diffusion layer;
(G) forming a second connection hole penetrating the second interlayer insulating film and reaching the stress relaxation pad;
And (h) forming a second plug on the N-type diffusion layer made of a conductive film filling the second connection hole. The method for manufacturing a semiconductor device according to claim 14,
In the step (e), another stress relaxation pad made of a conductive material is formed on a region extending from the first plug on the P-type diffusion layer to a part of the first interlayer insulating film;
In the step (f), the second stress relaxation pad is covered with the second interlayer insulating film;
In the step (g), another second connection hole penetrating the second interlayer insulating film and reaching the another stress relaxation pad is formed,
In the step (h), a method of manufacturing a semiconductor device, wherein a second plug is formed on a P-type diffusion layer made of a conductive film filling the second connection hole. The method for manufacturing a semiconductor device according to claim 14,
In the step (e), a portion of the metal film located above the first plug on the P-type diffusion layer is removed.
In the step (g), another second connection hole that penetrates through the second interlayer insulating film and reaches the first plug on the P-type diffusion layer is formed.
In the above step (h). A method of manufacturing a semiconductor device, wherein a second plug is formed on a P-type diffusion layer made of a conductor film filling the second connection hole. The method of manufacturing a semiconductor device according to claim 14,
In the steps (c) and (f), at least one of the first interlayer insulating film and the second interlayer insulating film is deposited using a high-density plasma CVD method. . The method of manufacturing a semiconductor device according to claim 14,
In the step (b), a method of manufacturing a semiconductor device, wherein any one of a titanium silicide film, a cobalt silicide film, and a nickel silicide film is formed as the silicide film. The method of manufacturing a semiconductor device according to claim 14,
The above steps (a) to (h) are performed in a logic transistor formation region,
A method of manufacturing a semiconductor device, comprising, after the step (h), a step of forming a capacitor of a DRAM memory cell. (A) forming a P-type diffusion layer and an N-type diffusion layer by introducing a P-type impurity and an N-type impurity into each part of the semiconductor layer;
Forming a silicide film on the N-type diffusion layer and a silicide film on the P-type diffusion layer by silicidizing the upper portions of the N-type diffusion layer and the P-type diffusion layer (b);
After the step (c), after forming a first interlayer insulating film covering the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer, the first interlayer insulating film penetrates the first interlayer insulating film. (C) forming first connection holes that respectively reach the silicide film on the N-type diffusion layer and the silicide film on the P-type diffusion layer;
A step (d) of introducing nitrogen into the silicide film on the N-type diffusion layer after the step (c);
(E) after the step (d), forming a first plug on the N-type diffusion layer and a first plug on the P-type diffusion layer by burying a conductive material in each of the first connection holes;
(F) forming a second interlayer insulating film covering the first interlayer insulating film, the first plug on the N-type diffusion layer, and the first plug on the P-type diffusion layer;
(G) forming a second connection hole that penetrates through the second interlayer insulating film and reaches the first plug on the N-type diffusion layer and the first plug on the P-type diffusion layer;
And (h) forming a second plug on the N-type diffusion layer made of a conductive film filling the second connection hole. The method for manufacturing a semiconductor device according to claim 20,
In the step (d), a method for manufacturing a semiconductor device, wherein nitrogen is also introduced into the silicide film on the P-type diffusion layer. 22. The method of manufacturing a semiconductor device according to claim 20, wherein
In the steps (c) and (e), a method of manufacturing a semiconductor device, wherein at least one of the first interlayer insulating film and the second interlayer insulating film is deposited by using a high-density plasma CVD method. The method of manufacturing a semiconductor device according to claim 20,
In the step (b), a method of manufacturing a semiconductor device, wherein any one of a titanium silicide film, a cobalt silicide film, and a nickel silicide film is formed as the silicide film. The method of manufacturing a semiconductor device according to claim 20,
The above steps (a) to (h) are performed in a logic transistor formation region,
A method of manufacturing a semiconductor device, comprising, after the step (h), a step of forming a capacitor of a DRAM memory cell.

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